Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\SERDES_IP\IPlib\RORALINK\data\RoraLink_64B66B_Top.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\SERDES_IP\IPlib\RORALINK\data\RoraLink_64B66B_Core_encryption.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12.01 (64-bit) |
| Part Number | GW5AST-LV138FPG676AC2/I1 |
| Device | GW5AST-138 |
| Device Version | B |
| Created Time | Tue Dec 30 15:30:34 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | RoraLink_64B66B_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.984s, Elapsed time = 0h 0m 1s, Peak memory usage = 133.871MB Running netlist conversion: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.101s, Peak memory usage = 133.871MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.402s, Peak memory usage = 133.871MB Optimizing Phase 1: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.23s, Peak memory usage = 133.871MB Optimizing Phase 2: CPU time = 0h 0m 0.39s, Elapsed time = 0h 0m 0.388s, Peak memory usage = 133.871MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.243s, Peak memory usage = 133.871MB Inferring Phase 1: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.101s, Peak memory usage = 133.871MB Inferring Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.056s, Peak memory usage = 133.871MB Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.026s, Peak memory usage = 133.871MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.322s, Peak memory usage = 133.871MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.097s, Peak memory usage = 133.871MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.042s, Peak memory usage = 133.871MB Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 140.430MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.359s, Peak memory usage = 140.430MB Generate output files: CPU time = 0h 0m 0.39s, Elapsed time = 0h 0m 0.404s, Peak memory usage = 169.750MB |
| Total Time and Memory Usage | CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 169.750MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 659 |
| I/O Buf | 625 |
| IBUF | 296 |
| OBUF | 329 |
| Register | 4838 |
| DFFSE | 251 |
| DFFRE | 3761 |
| DFFPE | 9 |
| DFFCE | 817 |
| LUT | 4874 |
| LUT1 | 64 |
| LUT2 | 391 |
| LUT3 | 1780 |
| LUT4 | 2019 |
| LUT5 | 172 |
| LUT6 | 448 |
| ALU | 272 |
| ALU | 272 |
| INV | 55 |
| INV | 55 |
| BSRAM | 2 |
| SDPX9B | 2 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 6717(6445 LUT, 272 ALU) / 138240 | 5% |
| Register | 4838 / 139140 | 4% |
| --Register as Latch | 0 / 139140 | 0% |
| --Register as FF | 4838 / 139140 | 4% |
| BSRAM | 2 / 340 | <1% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | sys_clk_i | Base | 10.000 | 100.000 | 0.000 | 5.000 | sys_clk_i_ibuf/I | ||
| 2 | serdes_lanex_pcs_rx_fabric_clk_i[0] | Base | 10.000 | 100.000 | 0.000 | 5.000 | serdes_lanex_pcs_rx_fabric_clk_i_0_ibuf/I | ||
| 3 | init_clk_i | Base | 10.000 | 100.000 | 0.000 | 5.000 | init_clk_i_ibuf/I |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | sys_clk_i | 100.000(MHz) | 153.610(MHz) | 7 | TOP |
| 2 | serdes_lanex_pcs_rx_fabric_clk_i[0] | 100.000(MHz) | 254.194(MHz) | 5 | TOP |
| 3 | init_clk_i | 100.000(MHz) | 312.598(MHz) | 4 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 3.490 |
| Data Arrival Time | 6.789 |
| Data Required Time | 10.279 |
| From | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[27] |
| To | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[3] |
| Launch Clk | sys_clk_i[R] |
| Latch Clk | sys_clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | sys_clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | sys_clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 3036 | sys_clk_i_ibuf/O |
| 0.330 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[27]/CLK |
| 0.636 | 0.306 | tC2Q | RR | 5 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[27]/Q |
| 0.966 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_450/I1 |
| 1.549 | 0.583 | tINS | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_450/F |
| 1.879 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_357/I1 |
| 2.531 | 0.652 | tINS | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_357/F |
| 2.861 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_197/I1 |
| 3.513 | 0.652 | tINS | RR | 31 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_197/F |
| 3.843 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_313/I1 |
| 4.495 | 0.652 | tINS | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_313/F |
| 4.825 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_157/I0 |
| 5.477 | 0.652 | tINS | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_157/F |
| 5.807 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_30/I0 |
| 6.459 | 0.652 | tINS | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_30/F |
| 6.789 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[3]/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | sys_clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | sys_clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 3036 | sys_clk_i_ibuf/O |
| 10.330 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[3]/CLK |
| 10.279 | -0.051 | tSu | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[3] |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.330, 100.000% |
| Arrival Data Path Delay: | cell: 3.843, 59.498%; route: 2.310, 35.764%; tC2Q: 0.306, 4.738% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.330, 100.000% |
Path 2
Path Summary:| Slack | 3.490 |
| Data Arrival Time | 6.789 |
| Data Required Time | 10.279 |
| From | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[27] |
| To | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[26] |
| Launch Clk | sys_clk_i[R] |
| Latch Clk | sys_clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | sys_clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | sys_clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 3036 | sys_clk_i_ibuf/O |
| 0.330 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[27]/CLK |
| 0.636 | 0.306 | tC2Q | RR | 5 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[27]/Q |
| 0.966 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_450/I1 |
| 1.549 | 0.583 | tINS | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_450/F |
| 1.879 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_357/I1 |
| 2.531 | 0.652 | tINS | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_357/F |
| 2.861 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_197/I1 |
| 3.513 | 0.652 | tINS | RR | 31 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_197/F |
| 3.843 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_244/I0 |
| 4.495 | 0.652 | tINS | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_244/F |
| 4.825 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_59/I0 |
| 5.477 | 0.652 | tINS | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_59/F |
| 5.807 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_7/I0 |
| 6.459 | 0.652 | tINS | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_7/F |
| 6.789 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[26]/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | sys_clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | sys_clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 3036 | sys_clk_i_ibuf/O |
| 10.330 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[26]/CLK |
| 10.279 | -0.051 | tSu | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[26] |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.330, 100.000% |
| Arrival Data Path Delay: | cell: 3.843, 59.498%; route: 2.310, 35.764%; tC2Q: 0.306, 4.738% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.330, 100.000% |
Path 3
Path Summary:| Slack | 3.490 |
| Data Arrival Time | 6.789 |
| Data Required Time | 10.279 |
| From | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[27] |
| To | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[15] |
| Launch Clk | sys_clk_i[R] |
| Latch Clk | sys_clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | sys_clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | sys_clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 3036 | sys_clk_i_ibuf/O |
| 0.330 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[27]/CLK |
| 0.636 | 0.306 | tC2Q | RR | 5 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[27]/Q |
| 0.966 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_425/I1 |
| 1.549 | 0.583 | tINS | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_425/F |
| 1.879 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_321/I1 |
| 2.531 | 0.652 | tINS | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_321/F |
| 2.861 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_171/I0 |
| 3.513 | 0.652 | tINS | RR | 31 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_171/F |
| 3.843 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_287/I0 |
| 4.495 | 0.652 | tINS | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_287/F |
| 4.825 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_104/I0 |
| 5.477 | 0.652 | tINS | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_104/F |
| 5.807 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_18/I0 |
| 6.459 | 0.652 | tINS | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_18/F |
| 6.789 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[15]/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | sys_clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | sys_clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 3036 | sys_clk_i_ibuf/O |
| 10.330 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[15]/CLK |
| 10.279 | -0.051 | tSu | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[15] |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.330, 100.000% |
| Arrival Data Path Delay: | cell: 3.843, 59.498%; route: 2.310, 35.764%; tC2Q: 0.306, 4.738% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.330, 100.000% |
Path 4
Path Summary:| Slack | 3.490 |
| Data Arrival Time | 6.789 |
| Data Required Time | 10.279 |
| From | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[27] |
| To | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[14] |
| Launch Clk | sys_clk_i[R] |
| Latch Clk | sys_clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | sys_clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | sys_clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 3036 | sys_clk_i_ibuf/O |
| 0.330 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[27]/CLK |
| 0.636 | 0.306 | tC2Q | RR | 5 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[27]/Q |
| 0.966 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_425/I1 |
| 1.549 | 0.583 | tINS | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_425/F |
| 1.879 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_321/I1 |
| 2.531 | 0.652 | tINS | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_321/F |
| 2.861 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_171/I0 |
| 3.513 | 0.652 | tINS | RR | 31 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_171/F |
| 3.843 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_264/I1 |
| 4.495 | 0.652 | tINS | RR | 2 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_264/F |
| 4.825 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_109/I0 |
| 5.477 | 0.652 | tINS | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_109/F |
| 5.807 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_19/I0 |
| 6.459 | 0.652 | tINS | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/msg_inferred_i_19/F |
| 6.789 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[14]/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | sys_clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | sys_clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 3036 | sys_clk_i_ibuf/O |
| 10.330 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[14]/CLK |
| 10.279 | -0.051 | tSu | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/crcreg_reg[14] |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.330, 100.000% |
| Arrival Data Path Delay: | cell: 3.843, 59.498%; route: 2.310, 35.764%; tC2Q: 0.306, 4.738% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.330, 100.000% |
Path 5
Path Summary:| Slack | 3.490 |
| Data Arrival Time | 6.789 |
| Data Required Time | 10.279 |
| From | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/tx_crc_gen_inst[0].tx_crc_gen/crcreg_reg[27] |
| To | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/tx_crc_gen_inst[0].tx_crc_gen/crcreg_reg[3] |
| Launch Clk | sys_clk_i[R] |
| Latch Clk | sys_clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | sys_clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | sys_clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 3036 | sys_clk_i_ibuf/O |
| 0.330 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/tx_crc_gen_inst[0].tx_crc_gen/crcreg_reg[27]/CLK |
| 0.636 | 0.306 | tC2Q | RR | 5 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/tx_crc_gen_inst[0].tx_crc_gen/crcreg_reg[27]/Q |
| 0.966 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/tx_crc_gen_inst[0].tx_crc_gen/msg_inferred_i_450/I1 |
| 1.549 | 0.583 | tINS | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/tx_crc_gen_inst[0].tx_crc_gen/msg_inferred_i_450/F |
| 1.879 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/tx_crc_gen_inst[0].tx_crc_gen/msg_inferred_i_357/I1 |
| 2.531 | 0.652 | tINS | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/tx_crc_gen_inst[0].tx_crc_gen/msg_inferred_i_357/F |
| 2.861 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/tx_crc_gen_inst[0].tx_crc_gen/msg_inferred_i_197/I1 |
| 3.513 | 0.652 | tINS | RR | 31 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/tx_crc_gen_inst[0].tx_crc_gen/msg_inferred_i_197/F |
| 3.843 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/tx_crc_gen_inst[0].tx_crc_gen/msg_inferred_i_313/I1 |
| 4.495 | 0.652 | tINS | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/tx_crc_gen_inst[0].tx_crc_gen/msg_inferred_i_313/F |
| 4.825 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/tx_crc_gen_inst[0].tx_crc_gen/msg_inferred_i_157/I0 |
| 5.477 | 0.652 | tINS | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/tx_crc_gen_inst[0].tx_crc_gen/msg_inferred_i_157/F |
| 5.807 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/tx_crc_gen_inst[0].tx_crc_gen/msg_inferred_i_30/I0 |
| 6.459 | 0.652 | tINS | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/tx_crc_gen_inst[0].tx_crc_gen/msg_inferred_i_30/F |
| 6.789 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/tx_crc_gen_inst[0].tx_crc_gen/crcreg_reg[3]/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | sys_clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | sys_clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 3036 | sys_clk_i_ibuf/O |
| 10.330 | 0.330 | tNET | RR | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/tx_crc_gen_inst[0].tx_crc_gen/crcreg_reg[3]/CLK |
| 10.279 | -0.051 | tSu | 1 | u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/tx_crc_gen_inst[0].tx_crc_gen/crcreg_reg[3] |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.330, 100.000% |
| Arrival Data Path Delay: | cell: 3.843, 59.498%; route: 2.310, 35.764%; tC2Q: 0.306, 4.738% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.330, 100.000% |