Timing Messages

Report Title	Timing Analysis Report
Design File	F:\138k_serdes\20251230\Gowin_RoraLink_64B66B_RefDesign\project\impl\gwsynthesis\serial_64b66b.vg
Physical Constraints File	F:\138k_serdes\20251230\Gowin_RoraLink_64B66B_RefDesign\project\src\top.cst
Timing Constraint File	F:\138k_serdes\20251230\Gowin_RoraLink_64B66B_RefDesign\project\src\top.sdc
Tool Version	V1.9.12.01 (64-bit)
Part Number	GW5AST-LV138FPG676AC2/I1
Device	GW5AST-138
Device Version	B
Created Time	Tue Dec 30 15:37:05 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.855V 0C C2/I1
Hold Delay Model	Fast 0.945V 85C C2/I1
Numbers of Paths Analyzed	16200
Numbers of Endpoints Analyzed	25902
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	osc_clk_i	Base	20.000	50.000	0.000	10.000			osc_clk_i
2	cfg_clk	Base	20.000	50.000	0.000	10.000			cfg_clk
3	sys_clk	Base	20.480	48.828	0.000	10.240			sys_clk
4	u_SerDes_Top/q1_lane1_fabric_rx_clk	Base	10.000	100.000	0.000	5.000			u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	cfg_clk	50.000(MHz)	90.657(MHz)	10	TOP
2	sys_clk	48.828(MHz)	89.708(MHz)	7	TOP
3	u_SerDes_Top/q1_lane1_fabric_rx_clk	100.000(MHz)	186.445(MHz)	3	TOP

No timing paths to get frequency of osc_clk_i!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
osc_clk_i	Setup	0.000	0
osc_clk_i	Hold	0.000	0
cfg_clk	Setup	0.000	0
cfg_clk	Hold	0.000	0
sys_clk	Setup	0.000	0
sys_clk	Hold	0.000	0
u_SerDes_Top/q1_lane1_fabric_rx_clk	Setup	0.000	0
u_SerDes_Top/q1_lane1_fabric_rx_clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	4.637	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence3_1d_2_s0/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_24_s0/D	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	10.000	0.007	5.305
2	4.639	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence3_1d_2_s0/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_20_s0/D	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	10.000	0.007	5.303
3	4.669	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence3_1d_2_s0/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_22_s0/D	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	10.000	-0.001	5.281
4	4.988	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence3_1d_2_s0/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_8_s0/D	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	10.000	0.007	4.954
5	5.028	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence3_1d_2_s0/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_18_s0/D	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	10.000	0.001	4.920
6	5.073	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence3_1d_2_s0/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_21_s0/D	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	10.000	0.003	4.873
7	5.149	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence3_1d_2_s0/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_14_s0/D	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	10.000	0.009	4.796
8	5.206	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence3_1d_0_s0/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_53_s0/D	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	10.000	-0.019	4.762
9	5.248	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence3_1d_0_s0/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_50_s0/D	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	10.000	-0.020	4.722
10	5.260	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_3_s2/RESET	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	10.000	0.023	4.419
11	5.260	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_7_s2/RESET	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	10.000	0.023	4.419
12	5.260	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_8_s2/RESET	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	10.000	0.023	4.419
13	5.260	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/descrambler_1_s0/RESET	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	10.000	0.023	4.419
14	5.260	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/descrambler_2_s0/SET	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	10.000	0.023	4.419
15	5.260	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/descrambler_3_s0/RESET	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	10.000	0.023	4.419
16	5.267	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_0_s2/RESET	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	10.000	0.016	4.419
17	5.267	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_2_s2/RESET	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	10.000	0.016	4.419
18	5.267	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_9_s2/RESET	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	10.000	0.016	4.419
19	5.267	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_21_s2/RESET	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	10.000	0.016	4.419
20	5.267	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_22_s2/RESET	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	10.000	0.016	4.419
21	5.267	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_39_s2/RESET	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	10.000	0.016	4.419
22	5.267	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_41_s2/RESET	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	10.000	0.016	4.419
23	5.273	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_5_s2/RESET	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	10.000	0.010	4.419
24	5.273	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_12_s2/RESET	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	10.000	0.010	4.419
25	5.273	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_13_s2/RESET	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	10.000	0.010	4.419

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.251	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_50_s0/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[14]	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	0.000	-0.014	0.302
2	0.251	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_49_s0/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[13]	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	0.000	-0.014	0.302
3	0.251	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_48_s0/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[12]	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	0.000	-0.014	0.302
4	0.275	u_frame_check/RX_D_R_59_s3/Q	u_frame_check/RX_D_R_59_s3/D	sys_clk:[R]	sys_clk:[R]	0.000	0.000	0.300
5	0.275	u_frame_check/RX_D_R_55_s3/Q	u_frame_check/RX_D_R_55_s3/D	sys_clk:[R]	sys_clk:[R]	0.000	0.000	0.300
6	0.275	u_frame_check/RX_D_R_53_s3/Q	u_frame_check/RX_D_R_53_s3/D	sys_clk:[R]	sys_clk:[R]	0.000	0.000	0.300
7	0.275	u_frame_check/RX_D_R_51_s3/Q	u_frame_check/RX_D_R_51_s3/D	sys_clk:[R]	sys_clk:[R]	0.000	0.000	0.300
8	0.275	u_frame_check/RX_D_R_13_s3/Q	u_frame_check/RX_D_R_13_s3/D	sys_clk:[R]	sys_clk:[R]	0.000	0.000	0.300
9	0.275	u_ufc_axi_to_ll/new_pkt_r_s0/Q	u_ufc_axi_to_ll/new_pkt_r_s0/D	sys_clk:[R]	sys_clk:[R]	0.000	0.000	0.300
10	0.275	u_data_axi_to_ll/u0_axi_register_slice/sel_wr_s2/Q	u_data_axi_to_ll/u0_axi_register_slice/sel_wr_s2/D	sys_clk:[R]	sys_clk:[R]	0.000	0.000	0.300
11	0.275	u_data_axi_to_ll/new_pkt_r_s0/Q	u_data_axi_to_ll/new_pkt_r_s0/D	sys_clk:[R]	sys_clk:[R]	0.000	0.000	0.300
12	0.275	u_frame_gen/count_for_fc_en_1_s0/Q	u_frame_gen/count_for_fc_en_1_s0/D	sys_clk:[R]	sys_clk:[R]	0.000	0.000	0.300
13	0.275	u_frame_gen/data_cycle_r_s0/Q	u_frame_gen/data_cycle_r_s0/D	sys_clk:[R]	sys_clk:[R]	0.000	0.000	0.300
14	0.275	u_frame_gen/ifg_size_r_7_s0/Q	u_frame_gen/ifg_size_r_7_s0/D	sys_clk:[R]	sys_clk:[R]	0.000	0.000	0.300
15	0.275	u_ufc_ll_to_axi/u_axi_register_slice/sel_rd_s2/Q	u_ufc_ll_to_axi/u_axi_register_slice/sel_rd_s2/D	sys_clk:[R]	sys_clk:[R]	0.000	0.000	0.300
16	0.275	u_ufc_ll_to_axi/u_axi_register_slice/sel_wr_s1/Q	u_ufc_ll_to_axi/u_axi_register_slice/sel_wr_s1/D	sys_clk:[R]	sys_clk:[R]	0.000	0.000	0.300
17	0.275	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/gen_roralink_lane[0].u0_duplex_mode/u0_sym_dec/rx_na_idles_cntr_0_s1/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/gen_roralink_lane[0].u0_duplex_mode/u0_sym_dec/rx_na_idles_cntr_0_s1/D	sys_clk:[R]	sys_clk:[R]	0.000	0.000	0.300
18	0.275	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/gen_roralink_lane[0].u0_duplex_mode/u0_duplex_init_sm/counter1_r_1_s0/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/gen_roralink_lane[0].u0_duplex_mode/u0_duplex_init_sm/counter1_r_1_s0/D	sys_clk:[R]	sys_clk:[R]	0.000	0.000	0.300
19	0.275	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_standard_cc/count_16d_flop_r_s9/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_standard_cc/count_16d_flop_r_s9/D	sys_clk:[R]	sys_clk:[R]	0.000	0.000	0.300
20	0.275	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rem_out_2_s1/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rem_out_2_s1/D	sys_clk:[R]	sys_clk:[R]	0.000	0.000	0.300
21	0.275	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_tx_ll/u_duplex_tx_ll_control_sm/flg_for_ufc_header_r_s2/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_tx_ll/u_duplex_tx_ll_control_sm/flg_for_ufc_header_r_s2/D	sys_clk:[R]	sys_clk:[R]	0.000	0.000	0.300
22	0.275	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_axi_to_ll_data/new_pkt_r_s0/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_axi_to_ll_data/new_pkt_r_s0/D	sys_clk:[R]	sys_clk:[R]	0.000	0.000	0.300
23	0.275	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_global_logic/u_duplex_ch_bond_code_gen/free_count_r_1_s0/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_global_logic/u_duplex_ch_bond_code_gen/free_count_r_1_s0/D	sys_clk:[R]	sys_clk:[R]	0.000	0.000	0.300
24	0.275	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_global_logic/u_duplex_channel_init_sm/chan_bond_timer_8_s0/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_global_logic/u_duplex_channel_init_sm/chan_bond_timer_8_s0/D	sys_clk:[R]	sys_clk:[R]	0.000	0.000	0.300
25	0.275	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/head_err_cnt_0_s0/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/head_err_cnt_0_s0/D	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	0.000	0.000	0.300

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	4.373	u1_reset_gen/o_rst1_s1/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_rst_srl_0_s0/PRESET	cfg_clk:[R]	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	10.000	-0.012	5.326
2	4.373	u1_reset_gen/o_rst1_s1/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_rst_srl_1_s0/PRESET	cfg_clk:[R]	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	10.000	-0.012	5.326
3	4.373	u1_reset_gen/o_rst1_s1/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_rst_srl_2_s0/PRESET	cfg_clk:[R]	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	10.000	-0.012	5.326
4	6.976	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/o_serdes_rx_blocksync_s2/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_srl_2_s0/PRESET	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	cfg_clk:[R]	10.000	0.006	2.705
5	6.976	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/o_serdes_rx_blocksync_s2/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_srl_0_s0/PRESET	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	cfg_clk:[R]	10.000	0.006	2.705
6	6.976	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/o_serdes_rx_blocksync_s2/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_srl_1_s0/PRESET	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	cfg_clk:[R]	10.000	0.006	2.705
7	7.773	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/fsm_st_curr_1_s0/CLEAR	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	10.000	-0.049	1.999
8	7.910	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/fsm_st_curr_0_s0/CLEAR	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	10.000	-0.003	1.815
9	8.108	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/fsm_st_curr_2_s0/CLEAR	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]	10.000	-0.026	1.640
10	15.664	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wp_rd_g2b_ptr_3_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	20.000	-0.025	4.083
11	15.667	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wp_rd_gray_ptr_3_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	20.000	-0.027	4.083
12	15.667	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wp_rd_gray_ptr1_3_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	20.000	-0.027	4.083
13	15.828	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wp_rd_g2b_ptr_2_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	20.000	-0.021	3.915
14	15.995	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wp_rd_g2b_ptr_1_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	20.000	-0.019	3.747
15	16.158	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wp_rd_g2b_ptr_0_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	20.000	-0.008	3.572
16	16.158	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wp_rd_gray_ptr1_0_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	20.000	-0.008	3.572
17	16.236	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/rd_gray_ptr_2_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	20.000	-0.004	3.490
18	16.404	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/rd1_ptr_1_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	20.000	-0.004	3.322
19	16.411	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/rd1_ptr_0_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	20.000	-0.011	3.322
20	16.515	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tx_data_reg_1_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	20.000	-0.008	3.214
21	16.515	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tx_data_reg_4_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	20.000	-0.008	3.214
22	16.515	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	20.000	-0.008	3.214
23	16.586	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/rp_wr_g2b_ptr_1_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	20.000	-0.004	3.140
24	16.586	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/rp_wr_g2b_ptr_2_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	20.000	-0.004	3.140
25	16.586	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/rp_wr_g2b_ptr_3_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	20.000	-0.004	3.140

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.321	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_reset_cbcc/cbcc_reset_cbstg2_rd_clk_s0/Q	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/master.master/alignment_done_r_s1/CLEAR	sys_clk:[R]	sys_clk:[R]	0.000	-0.013	0.281
2	0.397	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/addr_param_3_s1/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	-0.004	0.348
3	0.397	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/addr_param_7_s1/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	-0.004	0.348
4	0.397	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/addr_param_11_s1/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	-0.004	0.348
5	0.397	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/addr_param_15_s1/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	-0.004	0.348
6	0.397	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/rx_fifo_wdata_35_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	-0.004	0.348
7	0.397	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/rx_fifo_wdata_43_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	-0.004	0.348
8	0.397	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/rx_fifo_wdata_47_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	-0.004	0.348
9	0.401	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/fsm_st_curr_0_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	0.000	0.348
10	0.401	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/fsm_st_curr_1_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	0.000	0.348
11	0.401	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/fsm_st_curr_2_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	0.000	0.348
12	0.409	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_4_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	0.004	0.352
13	0.409	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_6_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	0.004	0.352
14	0.409	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_7_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	0.004	0.352
15	0.409	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_11_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	0.004	0.352
16	0.411	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/data_param_9_s1/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	0.012	0.346
17	0.411	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/data_param_13_s1/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	0.012	0.346
18	0.411	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/data_param_17_s1/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	0.012	0.346
19	0.411	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/data_param_21_s1/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	0.012	0.346
20	0.411	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/data_param_25_s1/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	0.012	0.346
21	0.411	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/data_param_29_s1/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	0.012	0.346
22	0.413	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_1_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	0.008	0.352
23	0.413	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_5_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	0.008	0.352
24	0.413	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_8_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	0.008	0.352
25	0.413	u1_reset_gen/o_rst1_s1/Q	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_12_s0/CLEAR	cfg_clk:[R]	cfg_clk:[R]	0.000	0.008	0.352

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	2.886	3.748	0.862	Low Pulse Width	u_SerDes_Top/q1_lane1_fabric_rx_clk	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s
2	2.890	3.752	0.862	Low Pulse Width	u_SerDes_Top/q1_lane1_fabric_rx_clk	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s
3	2.890	3.752	0.862	Low Pulse Width	u_SerDes_Top/q1_lane1_fabric_rx_clk	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/gowin_add_SDPX9B_mem_data_mem_data_0_1_s
4	2.893	3.755	0.862	Low Pulse Width	u_SerDes_Top/q1_lane1_fabric_rx_clk	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/gowin_add_SDPX9B_mem_data_mem_data_0_0_s
5	2.894	3.756	0.862	High Pulse Width	u_SerDes_Top/q1_lane1_fabric_rx_clk	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s
6	2.897	3.759	0.862	High Pulse Width	u_SerDes_Top/q1_lane1_fabric_rx_clk	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s
7	2.897	3.759	0.862	High Pulse Width	u_SerDes_Top/q1_lane1_fabric_rx_clk	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/gowin_add_SDPX9B_mem_data_mem_data_0_1_s
8	2.901	3.763	0.862	High Pulse Width	u_SerDes_Top/q1_lane1_fabric_rx_clk	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/gowin_add_SDPX9B_mem_data_mem_data_0_0_s
9	3.508	3.708	0.200	Low Pulse Width	u_SerDes_Top/q1_lane1_fabric_rx_clk	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/serdes_rx_data_59_s0
10	3.508	3.708	0.200	Low Pulse Width	u_SerDes_Top/q1_lane1_fabric_rx_clk	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/serdes_rx_data_12_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	4.637
Data Arrival Time	8.255
Data Required Time	12.892
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence3_1d_2_s0
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_24_s0
Launch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.950	2.950	tNET	RR	1	R24C99[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence3_1d_2_s0/CLK
3.256	0.306	tC2Q	RR	77	R24C99[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence3_1d_2_s0/Q
7.425	4.169	tNET	RR	1	R42C94[3][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n1111_s9/I2
7.790	0.365	tINS	RR	1	R42C94[3][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n1111_s9/F
7.792	0.002	tNET	RR	1	R42C94[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n1111_s7/I3
8.255	0.463	tINS	RR	1	R42C94[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n1111_s7/F
8.255	0.000	tNET	RR	1	R42C94[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_24_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.943	2.943	tNET	RR	1	R42C94[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_24_s0/CLK
12.892	-0.051	tSu		1	R42C94[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_24_s0

Path Statistics:

Clock Skew	-0.007
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.950, 100.000%
Arrival Data Path Delay	cell: 0.828, 15.608%; route: 4.171, 78.624%; tC2Q: 0.306, 5.768%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.943, 100.000%

Path2

Path Summary:

Slack	4.639
Data Arrival Time	8.253
Data Required Time	12.892
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence3_1d_2_s0
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_20_s0
Launch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.950	2.950	tNET	RR	1	R24C99[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence3_1d_2_s0/CLK
3.256	0.306	tC2Q	RR	77	R24C99[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence3_1d_2_s0/Q
7.256	4.000	tNET	RR	1	R40C94[3][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n1115_s9/I3
7.621	0.365	tINS	RR	1	R40C94[3][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n1115_s9/F
7.790	0.169	tNET	RR	1	R42C94[1][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n1115_s7/I3
8.253	0.463	tINS	RR	1	R42C94[1][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n1115_s7/F
8.253	0.000	tNET	RR	1	R42C94[1][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_20_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.943	2.943	tNET	RR	1	R42C94[1][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_20_s0/CLK
12.892	-0.051	tSu		1	R42C94[1][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_20_s0

Path Statistics:

Clock Skew	-0.007
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.950, 100.000%
Arrival Data Path Delay	cell: 0.828, 15.614%; route: 4.169, 78.616%; tC2Q: 0.306, 5.770%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.943, 100.000%

Path3

Path Summary:

Slack	4.669
Data Arrival Time	8.231
Data Required Time	12.900
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence3_1d_2_s0
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_22_s0
Launch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.950	2.950	tNET	RR	1	R24C99[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence3_1d_2_s0/CLK
3.256	0.306	tC2Q	RR	77	R24C99[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence3_1d_2_s0/Q
7.089	3.833	tNET	RR	1	R38C94[3][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n1113_s10/I3
7.322	0.233	tINS	RR	1	R38C94[3][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n1113_s10/F
7.777	0.455	tNET	RR	1	R38C98[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n1113_s7/I3
8.231	0.454	tINS	RR	1	R38C98[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n1113_s7/F
8.231	0.000	tNET	RR	1	R38C98[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_22_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.951	2.951	tNET	RR	1	R38C98[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_22_s0/CLK
12.900	-0.051	tSu		1	R38C98[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_22_s0

Path Statistics:

Clock Skew	0.001
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.950, 100.000%
Arrival Data Path Delay	cell: 0.687, 13.009%; route: 4.288, 81.197%; tC2Q: 0.306, 5.794%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.951, 100.000%

Path4

Path Summary:

Slack	4.988
Data Arrival Time	7.904
Data Required Time	12.892
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence3_1d_2_s0
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_8_s0
Launch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.950	2.950	tNET	RR	1	R24C99[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence3_1d_2_s0/CLK
3.256	0.306	tC2Q	RR	77	R24C99[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence3_1d_2_s0/Q
7.089	3.833	tNET	RR	1	R38C93[1][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n1127_s10/I3
7.552	0.463	tINS	RR	1	R38C93[1][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n1127_s10/F
7.673	0.121	tNET	RR	1	R38C93[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n1127_s7/I3
7.904	0.231	tINS	RR	1	R38C93[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n1127_s7/F
7.904	0.000	tNET	RR	1	R38C93[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.943	2.943	tNET	RR	1	R38C93[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_8_s0/CLK
12.892	-0.051	tSu		1	R38C93[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_8_s0

Path Statistics:

Clock Skew	-0.007
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.950, 100.000%
Arrival Data Path Delay	cell: 0.694, 14.009%; route: 3.954, 79.814%; tC2Q: 0.306, 6.177%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.943, 100.000%

Path5

Path Summary:

Slack	5.028
Data Arrival Time	7.870
Data Required Time	12.898
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence3_1d_2_s0
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_18_s0
Launch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.950	2.950	tNET	RR	1	R24C99[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence3_1d_2_s0/CLK
3.256	0.306	tC2Q	RR	77	R24C99[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence3_1d_2_s0/Q
6.920	3.664	tNET	RR	1	R39C93[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n1117_s9/I3
7.326	0.406	tINS	RR	1	R39C93[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n1117_s9/F
7.464	0.138	tNET	RR	1	R39C94[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n1117_s7/I3
7.870	0.406	tINS	RR	1	R39C94[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n1117_s7/F
7.870	0.000	tNET	RR	1	R39C94[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_18_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.948	2.949	tNET	RR	1	R39C94[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_18_s0/CLK
12.898	-0.051	tSu		1	R39C94[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_18_s0

Path Statistics:

Clock Skew	-0.001
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.950, 100.000%
Arrival Data Path Delay	cell: 0.812, 16.504%; route: 3.802, 77.276%; tC2Q: 0.306, 6.220%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.949, 100.000%

Path6

Path Summary:

Slack	5.073
Data Arrival Time	7.823
Data Required Time	12.896
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence3_1d_2_s0
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_21_s0
Launch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.950	2.950	tNET	RR	1	R24C99[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence3_1d_2_s0/CLK
3.256	0.306	tC2Q	RR	77	R24C99[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence3_1d_2_s0/Q
6.423	3.167	tNET	RR	1	R35C94[2][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n1114_s9/I2
6.877	0.454	tINS	RR	1	R35C94[2][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n1114_s9/F
7.360	0.483	tNET	RR	1	R40C94[1][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n1114_s7/I1
7.823	0.463	tINS	RR	1	R40C94[1][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n1114_s7/F
7.823	0.000	tNET	RR	1	R40C94[1][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_21_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.946	2.947	tNET	RR	1	R40C94[1][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_21_s0/CLK
12.896	-0.051	tSu		1	R40C94[1][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_21_s0

Path Statistics:

Clock Skew	-0.003
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.950, 100.000%
Arrival Data Path Delay	cell: 0.917, 18.818%; route: 3.650, 74.903%; tC2Q: 0.306, 6.279%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.947, 100.000%

Path7

Path Summary:

Slack	5.149
Data Arrival Time	7.746
Data Required Time	12.895
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence3_1d_2_s0
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_14_s0
Launch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.950	2.950	tNET	RR	1	R24C99[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence3_1d_2_s0/CLK
3.256	0.306	tC2Q	RR	77	R24C99[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence3_1d_2_s0/Q
6.769	3.513	tNET	RR	1	R36C93[2][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n1121_s16/I3
7.175	0.406	tINS	RR	1	R36C93[2][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n1121_s16/F
7.491	0.316	tNET	RR	1	R39C93[3][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n1121_s15/I3
7.746	0.255	tINS	RF	1	R39C93[3][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n1121_s15/F
7.746	0.000	tNET	FF	1	R39C93[3][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.941	2.941	tNET	RR	1	R39C93[3][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_14_s0/CLK
12.895	-0.046	tSu		1	R39C93[3][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_14_s0

Path Statistics:

Clock Skew	-0.009
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.950, 100.000%
Arrival Data Path Delay	cell: 0.661, 13.782%; route: 3.829, 79.837%; tC2Q: 0.306, 6.380%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.941, 100.000%

Path8

Path Summary:

Slack	5.206
Data Arrival Time	7.678
Data Required Time	12.884
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence3_1d_0_s0
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_53_s0
Launch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.917	2.917	tNET	RR	1	R31C99[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence3_1d_0_s0/CLK
3.223	0.306	tC2Q	RR	78	R31C99[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence3_1d_0_s0/Q
5.431	2.208	tNET	RR	1	R25C97[3][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n1078_s8/I2
5.795	0.365	tINS	RR	4	R25C97[3][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n1078_s8/F
6.768	0.973	tNET	RR	1	R42C101[0][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n1082_s9/I0
7.222	0.454	tINS	RR	1	R42C101[0][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n1082_s9/F
7.224	0.002	tNET	RR	1	R42C101[2][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n1082_s7/I3
7.678	0.454	tINS	RR	1	R42C101[2][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n1082_s7/F
7.678	0.000	tNET	RR	1	R42C101[2][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_53_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.935	2.935	tNET	RR	1	R42C101[2][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_53_s0/CLK
12.884	-0.051	tSu		1	R42C101[2][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_53_s0

Path Statistics:

Clock Skew	0.019
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.917, 100.000%
Arrival Data Path Delay	cell: 1.273, 26.732%; route: 3.183, 66.842%; tC2Q: 0.306, 6.426%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.935, 100.000%

Path9

Path Summary:

Slack	5.248
Data Arrival Time	7.638
Data Required Time	12.886
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence3_1d_0_s0
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_50_s0
Launch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.917	2.917	tNET	RR	1	R31C99[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence3_1d_0_s0/CLK
3.223	0.306	tC2Q	RR	78	R31C99[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx_sequence3_1d_0_s0/Q
5.759	2.537	tNET	RR	1	R20C95[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n1081_s8/I2
6.165	0.406	tINS	RR	4	R20C95[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n1081_s8/F
6.810	0.645	tNET	RR	1	R23C94[3][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n1085_s9/I0
7.269	0.459	tINS	RR	1	R23C94[3][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n1085_s9/F
7.407	0.138	tNET	RR	1	R23C93[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n1085_s7/I3
7.638	0.231	tINS	RR	1	R23C93[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/n1085_s7/F
7.638	0.000	tNET	RR	1	R23C93[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_50_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.937	2.937	tNET	RR	1	R23C93[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_50_s0/CLK
12.886	-0.051	tSu		1	R23C93[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/rx3_66b_data_50_s0

Path Statistics:

Clock Skew	0.020
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.917, 100.000%
Arrival Data Path Delay	cell: 1.096, 23.211%; route: 3.320, 70.309%; tC2Q: 0.306, 6.480%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.937, 100.000%

Path10

Path Summary:

Slack	5.260
Data Arrival Time	7.339
Data Required Time	12.599
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_3_s2
Launch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.920	2.920	tNET	RR	1	R34C110[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/CLK
3.226	0.306	tC2Q	RR	17	R34C110[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/Q
4.591	1.365	tNET	RR	1	R33C91[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/n487_s0/I0
5.045	0.454	tINS	RR	122	R33C91[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/n487_s0/F
7.339	2.294	tNET	RR	1	R48C93[1][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_3_s2/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.897	2.897	tNET	RR	1	R48C93[1][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_3_s2/CLK
12.599	-0.298	tSu		1	R48C93[1][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_3_s2

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.920, 100.000%
Arrival Data Path Delay	cell: 0.454, 10.274%; route: 3.659, 82.801%; tC2Q: 0.306, 6.925%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.897, 100.000%

Path11

Path Summary:

Slack	5.260
Data Arrival Time	7.339
Data Required Time	12.599
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_7_s2
Launch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.920	2.920	tNET	RR	1	R34C110[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/CLK
3.226	0.306	tC2Q	RR	17	R34C110[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/Q
4.591	1.365	tNET	RR	1	R33C91[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/n487_s0/I0
5.045	0.454	tINS	RR	122	R33C91[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/n487_s0/F
7.339	2.294	tNET	RR	1	R48C93[0][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_7_s2/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.897	2.897	tNET	RR	1	R48C93[0][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_7_s2/CLK
12.599	-0.298	tSu		1	R48C93[0][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_7_s2

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.920, 100.000%
Arrival Data Path Delay	cell: 0.454, 10.274%; route: 3.659, 82.801%; tC2Q: 0.306, 6.925%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.897, 100.000%

Path12

Path Summary:

Slack	5.260
Data Arrival Time	7.339
Data Required Time	12.599
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_8_s2
Launch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.920	2.920	tNET	RR	1	R34C110[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/CLK
3.226	0.306	tC2Q	RR	17	R34C110[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/Q
4.591	1.365	tNET	RR	1	R33C91[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/n487_s0/I0
5.045	0.454	tINS	RR	122	R33C91[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/n487_s0/F
7.339	2.294	tNET	RR	1	R48C93[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_8_s2/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.897	2.897	tNET	RR	1	R48C93[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_8_s2/CLK
12.599	-0.298	tSu		1	R48C93[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_8_s2

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.920, 100.000%
Arrival Data Path Delay	cell: 0.454, 10.274%; route: 3.659, 82.801%; tC2Q: 0.306, 6.925%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.897, 100.000%

Path13

Path Summary:

Slack	5.260
Data Arrival Time	7.339
Data Required Time	12.599
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/descrambler_1_s0
Launch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.920	2.920	tNET	RR	1	R34C110[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/CLK
3.226	0.306	tC2Q	RR	17	R34C110[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/Q
4.591	1.365	tNET	RR	1	R33C91[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/n487_s0/I0
5.045	0.454	tINS	RR	122	R33C91[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/n487_s0/F
7.339	2.294	tNET	RR	1	R48C93[3][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/descrambler_1_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.897	2.897	tNET	RR	1	R48C93[3][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/descrambler_1_s0/CLK
12.599	-0.298	tSu		1	R48C93[3][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/descrambler_1_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.920, 100.000%
Arrival Data Path Delay	cell: 0.454, 10.274%; route: 3.659, 82.801%; tC2Q: 0.306, 6.925%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.897, 100.000%

Path14

Path Summary:

Slack	5.260
Data Arrival Time	7.339
Data Required Time	12.599
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/descrambler_2_s0
Launch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.920	2.920	tNET	RR	1	R34C110[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/CLK
3.226	0.306	tC2Q	RR	17	R34C110[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/Q
4.591	1.365	tNET	RR	1	R33C91[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/n487_s0/I0
5.045	0.454	tINS	RR	122	R33C91[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/n487_s0/F
7.339	2.294	tNET	RR	1	R48C93[3][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/descrambler_2_s0/SET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.897	2.897	tNET	RR	1	R48C93[3][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/descrambler_2_s0/CLK
12.599	-0.298	tSu		1	R48C93[3][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/descrambler_2_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.920, 100.000%
Arrival Data Path Delay	cell: 0.454, 10.274%; route: 3.659, 82.801%; tC2Q: 0.306, 6.925%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.897, 100.000%

Path15

Path Summary:

Slack	5.260
Data Arrival Time	7.339
Data Required Time	12.599
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/descrambler_3_s0
Launch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.920	2.920	tNET	RR	1	R34C110[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/CLK
3.226	0.306	tC2Q	RR	17	R34C110[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/Q
4.591	1.365	tNET	RR	1	R33C91[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/n487_s0/I0
5.045	0.454	tINS	RR	122	R33C91[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/n487_s0/F
7.339	2.294	tNET	RR	1	R48C93[2][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/descrambler_3_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.897	2.897	tNET	RR	1	R48C93[2][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/descrambler_3_s0/CLK
12.599	-0.298	tSu		1	R48C93[2][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/descrambler_3_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.920, 100.000%
Arrival Data Path Delay	cell: 0.454, 10.274%; route: 3.659, 82.801%; tC2Q: 0.306, 6.925%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.897, 100.000%

Path16

Path Summary:

Slack	5.267
Data Arrival Time	7.339
Data Required Time	12.606
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_0_s2
Launch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.920	2.920	tNET	RR	1	R34C110[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/CLK
3.226	0.306	tC2Q	RR	17	R34C110[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/Q
4.591	1.365	tNET	RR	1	R33C91[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/n487_s0/I0
5.045	0.454	tINS	RR	122	R33C91[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/n487_s0/F
7.339	2.294	tNET	RR	1	R48C92[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_0_s2/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.904	2.904	tNET	RR	1	R48C92[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_0_s2/CLK
12.606	-0.298	tSu		1	R48C92[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_0_s2

Path Statistics:

Clock Skew	-0.016
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.920, 100.000%
Arrival Data Path Delay	cell: 0.454, 10.274%; route: 3.659, 82.801%; tC2Q: 0.306, 6.925%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.904, 100.000%

Path17

Path Summary:

Slack	5.267
Data Arrival Time	7.339
Data Required Time	12.606
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_2_s2
Launch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.920	2.920	tNET	RR	1	R34C110[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/CLK
3.226	0.306	tC2Q	RR	17	R34C110[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/Q
4.591	1.365	tNET	RR	1	R33C91[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/n487_s0/I0
5.045	0.454	tINS	RR	122	R33C91[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/n487_s0/F
7.339	2.294	tNET	RR	1	R48C92[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_2_s2/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.904	2.904	tNET	RR	1	R48C92[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_2_s2/CLK
12.606	-0.298	tSu		1	R48C92[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_2_s2

Path Statistics:

Clock Skew	-0.016
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.920, 100.000%
Arrival Data Path Delay	cell: 0.454, 10.274%; route: 3.659, 82.801%; tC2Q: 0.306, 6.925%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.904, 100.000%

Path18

Path Summary:

Slack	5.267
Data Arrival Time	7.339
Data Required Time	12.606
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_9_s2
Launch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.920	2.920	tNET	RR	1	R34C110[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/CLK
3.226	0.306	tC2Q	RR	17	R34C110[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/Q
4.591	1.365	tNET	RR	1	R33C91[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/n487_s0/I0
5.045	0.454	tINS	RR	122	R33C91[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/n487_s0/F
7.339	2.294	tNET	RR	1	R48C92[1][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_9_s2/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.904	2.904	tNET	RR	1	R48C92[1][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_9_s2/CLK
12.606	-0.298	tSu		1	R48C92[1][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_9_s2

Path Statistics:

Clock Skew	-0.016
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.920, 100.000%
Arrival Data Path Delay	cell: 0.454, 10.274%; route: 3.659, 82.801%; tC2Q: 0.306, 6.925%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.904, 100.000%

Path19

Path Summary:

Slack	5.267
Data Arrival Time	7.339
Data Required Time	12.606
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_21_s2
Launch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.920	2.920	tNET	RR	1	R34C110[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/CLK
3.226	0.306	tC2Q	RR	17	R34C110[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/Q
4.591	1.365	tNET	RR	1	R33C91[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/n487_s0/I0
5.045	0.454	tINS	RR	122	R33C91[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/n487_s0/F
7.339	2.294	tNET	RR	1	R48C92[2][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_21_s2/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.904	2.904	tNET	RR	1	R48C92[2][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_21_s2/CLK
12.606	-0.298	tSu		1	R48C92[2][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_21_s2

Path Statistics:

Clock Skew	-0.016
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.920, 100.000%
Arrival Data Path Delay	cell: 0.454, 10.274%; route: 3.659, 82.801%; tC2Q: 0.306, 6.925%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.904, 100.000%

Path20

Path Summary:

Slack	5.267
Data Arrival Time	7.339
Data Required Time	12.606
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_22_s2
Launch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.920	2.920	tNET	RR	1	R34C110[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/CLK
3.226	0.306	tC2Q	RR	17	R34C110[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/Q
4.591	1.365	tNET	RR	1	R33C91[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/n487_s0/I0
5.045	0.454	tINS	RR	122	R33C91[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/n487_s0/F
7.339	2.294	tNET	RR	1	R48C92[3][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_22_s2/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.904	2.904	tNET	RR	1	R48C92[3][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_22_s2/CLK
12.606	-0.298	tSu		1	R48C92[3][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_22_s2

Path Statistics:

Clock Skew	-0.016
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.920, 100.000%
Arrival Data Path Delay	cell: 0.454, 10.274%; route: 3.659, 82.801%; tC2Q: 0.306, 6.925%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.904, 100.000%

Path21

Path Summary:

Slack	5.267
Data Arrival Time	7.339
Data Required Time	12.606
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_39_s2
Launch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.920	2.920	tNET	RR	1	R34C110[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/CLK
3.226	0.306	tC2Q	RR	17	R34C110[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/Q
4.591	1.365	tNET	RR	1	R33C91[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/n487_s0/I0
5.045	0.454	tINS	RR	122	R33C91[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/n487_s0/F
7.339	2.294	tNET	RR	1	R48C92[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_39_s2/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.904	2.904	tNET	RR	1	R48C92[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_39_s2/CLK
12.606	-0.298	tSu		1	R48C92[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_39_s2

Path Statistics:

Clock Skew	-0.016
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.920, 100.000%
Arrival Data Path Delay	cell: 0.454, 10.274%; route: 3.659, 82.801%; tC2Q: 0.306, 6.925%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.904, 100.000%

Path22

Path Summary:

Slack	5.267
Data Arrival Time	7.339
Data Required Time	12.606
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_41_s2
Launch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.920	2.920	tNET	RR	1	R34C110[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/CLK
3.226	0.306	tC2Q	RR	17	R34C110[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/Q
4.591	1.365	tNET	RR	1	R33C91[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/n487_s0/I0
5.045	0.454	tINS	RR	122	R33C91[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/n487_s0/F
7.339	2.294	tNET	RR	1	R48C92[0][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_41_s2/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.904	2.904	tNET	RR	1	R48C92[0][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_41_s2/CLK
12.606	-0.298	tSu		1	R48C92[0][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_41_s2

Path Statistics:

Clock Skew	-0.016
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.920, 100.000%
Arrival Data Path Delay	cell: 0.454, 10.274%; route: 3.659, 82.801%; tC2Q: 0.306, 6.925%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.904, 100.000%

Path23

Path Summary:

Slack	5.273
Data Arrival Time	7.339
Data Required Time	12.612
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_5_s2
Launch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.920	2.920	tNET	RR	1	R34C110[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/CLK
3.226	0.306	tC2Q	RR	17	R34C110[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/Q
4.591	1.365	tNET	RR	1	R33C91[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/n487_s0/I0
5.045	0.454	tINS	RR	122	R33C91[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/n487_s0/F
7.339	2.294	tNET	RR	1	R47C93[1][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_5_s2/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.910	2.910	tNET	RR	1	R47C93[1][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_5_s2/CLK
12.612	-0.298	tSu		1	R47C93[1][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_5_s2

Path Statistics:

Clock Skew	-0.010
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.920, 100.000%
Arrival Data Path Delay	cell: 0.454, 10.274%; route: 3.659, 82.801%; tC2Q: 0.306, 6.925%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.910, 100.000%

Path24

Path Summary:

Slack	5.273
Data Arrival Time	7.339
Data Required Time	12.612
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_12_s2
Launch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.920	2.920	tNET	RR	1	R34C110[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/CLK
3.226	0.306	tC2Q	RR	17	R34C110[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/Q
4.591	1.365	tNET	RR	1	R33C91[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/n487_s0/I0
5.045	0.454	tINS	RR	122	R33C91[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/n487_s0/F
7.339	2.294	tNET	RR	1	R47C93[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_12_s2/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.910	2.910	tNET	RR	1	R47C93[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_12_s2/CLK
12.612	-0.298	tSu		1	R47C93[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_12_s2

Path Statistics:

Clock Skew	-0.010
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.920, 100.000%
Arrival Data Path Delay	cell: 0.454, 10.274%; route: 3.659, 82.801%; tC2Q: 0.306, 6.925%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.910, 100.000%

Path25

Path Summary:

Slack	5.273
Data Arrival Time	7.339
Data Required Time	12.612
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_13_s2
Launch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.920	2.920	tNET	RR	1	R34C110[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/CLK
3.226	0.306	tC2Q	RR	17	R34C110[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/Q
4.591	1.365	tNET	RR	1	R33C91[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/n487_s0/I0
5.045	0.454	tINS	RR	122	R33C91[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/n487_s0/F
7.339	2.294	tNET	RR	1	R47C93[0][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_13_s2/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.910	2.910	tNET	RR	1	R47C93[0][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_13_s2/CLK
12.612	-0.298	tSu		1	R47C93[0][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/o_serdes_rx_dat_13_s2

Path Statistics:

Clock Skew	-0.010
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.920, 100.000%
Arrival Data Path Delay	cell: 0.454, 10.274%; route: 3.659, 82.801%; tC2Q: 0.306, 6.925%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.910, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.251
Data Arrival Time	1.704
Data Required Time	1.453
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_50_s0
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s
Launch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.402	1.402	tNET	RR	1	R49C108[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_50_s0/CLK
1.543	0.141	tC2Q	RF	2	R49C108[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_50_s0/Q
1.704	0.161	tNET	FF	1	BSRAM_R46[22]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[14]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.416	1.416	tNET	RR	1	BSRAM_R46[22]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/CLKA
1.453	0.037	tHld		1	BSRAM_R46[22]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s

Path Statistics:

Clock Skew	0.014
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.402, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.161, 53.311%; tC2Q: 0.141, 46.689%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.416, 100.000%

Path2

Path Summary:

Slack	0.251
Data Arrival Time	1.704
Data Required Time	1.453
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_49_s0
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s
Launch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.402	1.402	tNET	RR	1	R49C108[2][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_49_s0/CLK
1.543	0.141	tC2Q	RF	2	R49C108[2][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_49_s0/Q
1.704	0.161	tNET	FF	1	BSRAM_R46[22]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[13]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.416	1.416	tNET	RR	1	BSRAM_R46[22]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/CLKA
1.453	0.037	tHld		1	BSRAM_R46[22]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s

Path Statistics:

Clock Skew	0.014
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.402, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.161, 53.311%; tC2Q: 0.141, 46.689%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.416, 100.000%

Path3

Path Summary:

Slack	0.251
Data Arrival Time	1.704
Data Required Time	1.453
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_48_s0
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s
Launch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.402	1.402	tNET	RR	1	R49C108[1][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_48_s0/CLK
1.543	0.141	tC2Q	RF	2	R49C108[1][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/wdth_conv_1stage_48_s0/Q
1.704	0.161	tNET	FF	1	BSRAM_R46[22]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/DI[12]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.416	1.416	tNET	RR	1	BSRAM_R46[22]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/CLKA
1.453	0.037	tHld		1	BSRAM_R46[22]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s

Path Statistics:

Clock Skew	0.014
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.402, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.161, 53.311%; tC2Q: 0.141, 46.689%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.416, 100.000%

Path4

Path Summary:

Slack	0.275
Data Arrival Time	1.743
Data Required Time	1.468
From	u_frame_check/RX_D_R_59_s3
To	u_frame_check/RX_D_R_59_s3
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.443	1.443	tNET	RR	1	R34C141[1][A]	u_frame_check/RX_D_R_59_s3/CLK
1.584	0.141	tC2Q	RF	2	R34C141[1][A]	u_frame_check/RX_D_R_59_s3/Q
1.590	0.006	tNET	FF	1	R34C141[1][A]	u_frame_check/n442_s2/I2
1.743	0.153	tINS	FF	1	R34C141[1][A]	u_frame_check/n442_s2/F
1.743	0.000	tNET	FF	1	R34C141[1][A]	u_frame_check/RX_D_R_59_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.443	1.443	tNET	RR	1	R34C141[1][A]	u_frame_check/RX_D_R_59_s3/CLK
1.468	0.025	tHld		1	R34C141[1][A]	u_frame_check/RX_D_R_59_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.443, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.443, 100.000%

Path5

Path Summary:

Slack	0.275
Data Arrival Time	1.746
Data Required Time	1.471
From	u_frame_check/RX_D_R_55_s3
To	u_frame_check/RX_D_R_55_s3
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.446	1.446	tNET	RR	1	R33C142[0][A]	u_frame_check/RX_D_R_55_s3/CLK
1.587	0.141	tC2Q	RF	2	R33C142[0][A]	u_frame_check/RX_D_R_55_s3/Q
1.593	0.006	tNET	FF	1	R33C142[0][A]	u_frame_check/n438_s2/I2
1.746	0.153	tINS	FF	1	R33C142[0][A]	u_frame_check/n438_s2/F
1.746	0.000	tNET	FF	1	R33C142[0][A]	u_frame_check/RX_D_R_55_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.446	1.446	tNET	RR	1	R33C142[0][A]	u_frame_check/RX_D_R_55_s3/CLK
1.471	0.025	tHld		1	R33C142[0][A]	u_frame_check/RX_D_R_55_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.446, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.446, 100.000%

Path6

Path Summary:

Slack	0.275
Data Arrival Time	1.738
Data Required Time	1.463
From	u_frame_check/RX_D_R_53_s3
To	u_frame_check/RX_D_R_53_s3
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.438	1.438	tNET	RR	1	R31C142[0][A]	u_frame_check/RX_D_R_53_s3/CLK
1.579	0.141	tC2Q	RF	2	R31C142[0][A]	u_frame_check/RX_D_R_53_s3/Q
1.585	0.006	tNET	FF	1	R31C142[0][A]	u_frame_check/n436_s2/I2
1.738	0.153	tINS	FF	1	R31C142[0][A]	u_frame_check/n436_s2/F
1.738	0.000	tNET	FF	1	R31C142[0][A]	u_frame_check/RX_D_R_53_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.438	1.438	tNET	RR	1	R31C142[0][A]	u_frame_check/RX_D_R_53_s3/CLK
1.463	0.025	tHld		1	R31C142[0][A]	u_frame_check/RX_D_R_53_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.438, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.438, 100.000%

Path7

Path Summary:

Slack	0.275
Data Arrival Time	1.738
Data Required Time	1.463
From	u_frame_check/RX_D_R_51_s3
To	u_frame_check/RX_D_R_51_s3
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.438	1.438	tNET	RR	1	R31C142[1][A]	u_frame_check/RX_D_R_51_s3/CLK
1.579	0.141	tC2Q	RF	2	R31C142[1][A]	u_frame_check/RX_D_R_51_s3/Q
1.585	0.006	tNET	FF	1	R31C142[1][A]	u_frame_check/n434_s2/I2
1.738	0.153	tINS	FF	1	R31C142[1][A]	u_frame_check/n434_s2/F
1.738	0.000	tNET	FF	1	R31C142[1][A]	u_frame_check/RX_D_R_51_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.438	1.438	tNET	RR	1	R31C142[1][A]	u_frame_check/RX_D_R_51_s3/CLK
1.463	0.025	tHld		1	R31C142[1][A]	u_frame_check/RX_D_R_51_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.438, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.438, 100.000%

Path8

Path Summary:

Slack	0.275
Data Arrival Time	1.750
Data Required Time	1.475
From	u_frame_check/RX_D_R_13_s3
To	u_frame_check/RX_D_R_13_s3
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.450	1.450	tNET	RR	1	R36C142[1][A]	u_frame_check/RX_D_R_13_s3/CLK
1.591	0.141	tC2Q	RF	2	R36C142[1][A]	u_frame_check/RX_D_R_13_s3/Q
1.597	0.006	tNET	FF	1	R36C142[1][A]	u_frame_check/n460_s4/I2
1.750	0.153	tINS	FF	1	R36C142[1][A]	u_frame_check/n460_s4/F
1.750	0.000	tNET	FF	1	R36C142[1][A]	u_frame_check/RX_D_R_13_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.450	1.450	tNET	RR	1	R36C142[1][A]	u_frame_check/RX_D_R_13_s3/CLK
1.475	0.025	tHld		1	R36C142[1][A]	u_frame_check/RX_D_R_13_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.450, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.450, 100.000%

Path9

Path Summary:

Slack	0.275
Data Arrival Time	1.738
Data Required Time	1.463
From	u_ufc_axi_to_ll/new_pkt_r_s0
To	u_ufc_axi_to_ll/new_pkt_r_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.438	1.438	tNET	RR	1	R14C131[0][A]	u_ufc_axi_to_ll/new_pkt_r_s0/CLK
1.579	0.141	tC2Q	RF	2	R14C131[0][A]	u_ufc_axi_to_ll/new_pkt_r_s0/Q
1.585	0.006	tNET	FF	1	R14C131[0][A]	u_ufc_axi_to_ll/new_pkt_s2/I1
1.738	0.153	tINS	FF	1	R14C131[0][A]	u_ufc_axi_to_ll/new_pkt_s2/F
1.738	0.000	tNET	FF	1	R14C131[0][A]	u_ufc_axi_to_ll/new_pkt_r_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.438	1.438	tNET	RR	1	R14C131[0][A]	u_ufc_axi_to_ll/new_pkt_r_s0/CLK
1.463	0.025	tHld		1	R14C131[0][A]	u_ufc_axi_to_ll/new_pkt_r_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.438, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.438, 100.000%

Path10

Path Summary:

Slack	0.275
Data Arrival Time	1.761
Data Required Time	1.486
From	u_data_axi_to_ll/u0_axi_register_slice/sel_wr_s2
To	u_data_axi_to_ll/u0_axi_register_slice/sel_wr_s2
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.461	1.461	tNET	RR	1	R42C141[0][A]	u_data_axi_to_ll/u0_axi_register_slice/sel_wr_s2/CLK
1.602	0.141	tC2Q	RF	3	R42C141[0][A]	u_data_axi_to_ll/u0_axi_register_slice/sel_wr_s2/Q
1.608	0.006	tNET	FF	1	R42C141[0][A]	u_data_axi_to_ll/u0_axi_register_slice/n46_s3/I2
1.761	0.153	tINS	FF	1	R42C141[0][A]	u_data_axi_to_ll/u0_axi_register_slice/n46_s3/F
1.761	0.000	tNET	FF	1	R42C141[0][A]	u_data_axi_to_ll/u0_axi_register_slice/sel_wr_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.461	1.461	tNET	RR	1	R42C141[0][A]	u_data_axi_to_ll/u0_axi_register_slice/sel_wr_s2/CLK
1.486	0.025	tHld		1	R42C141[0][A]	u_data_axi_to_ll/u0_axi_register_slice/sel_wr_s2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.461, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.461, 100.000%

Path11

Path Summary:

Slack	0.275
Data Arrival Time	1.772
Data Required Time	1.497
From	u_data_axi_to_ll/new_pkt_r_s0
To	u_data_axi_to_ll/new_pkt_r_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.472	1.472	tNET	RR	1	R38C142[0][A]	u_data_axi_to_ll/new_pkt_r_s0/CLK
1.613	0.141	tC2Q	RF	2	R38C142[0][A]	u_data_axi_to_ll/new_pkt_r_s0/Q
1.619	0.006	tNET	FF	1	R38C142[0][A]	u_data_axi_to_ll/new_pkt_s2/I1
1.772	0.153	tINS	FF	1	R38C142[0][A]	u_data_axi_to_ll/new_pkt_s2/F
1.772	0.000	tNET	FF	1	R38C142[0][A]	u_data_axi_to_ll/new_pkt_r_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.472	1.472	tNET	RR	1	R38C142[0][A]	u_data_axi_to_ll/new_pkt_r_s0/CLK
1.497	0.025	tHld		1	R38C142[0][A]	u_data_axi_to_ll/new_pkt_r_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.472, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.472, 100.000%

Path12

Path Summary:

Slack	0.275
Data Arrival Time	1.734
Data Required Time	1.459
From	u_frame_gen/count_for_fc_en_1_s0
To	u_frame_gen/count_for_fc_en_1_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.434	1.434	tNET	RR	1	R32C124[0][A]	u_frame_gen/count_for_fc_en_1_s0/CLK
1.575	0.141	tC2Q	RF	4	R32C124[0][A]	u_frame_gen/count_for_fc_en_1_s0/Q
1.581	0.006	tNET	FF	1	R32C124[0][A]	u_frame_gen/n341_s1/I1
1.734	0.153	tINS	FF	1	R32C124[0][A]	u_frame_gen/n341_s1/F
1.734	0.000	tNET	FF	1	R32C124[0][A]	u_frame_gen/count_for_fc_en_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.434	1.434	tNET	RR	1	R32C124[0][A]	u_frame_gen/count_for_fc_en_1_s0/CLK
1.459	0.025	tHld		1	R32C124[0][A]	u_frame_gen/count_for_fc_en_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.434, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.434, 100.000%

Path13

Path Summary:

Slack	0.275
Data Arrival Time	1.750
Data Required Time	1.475
From	u_frame_gen/data_cycle_r_s0
To	u_frame_gen/data_cycle_r_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.450	1.450	tNET	RR	1	R36C126[0][A]	u_frame_gen/data_cycle_r_s0/CLK
1.591	0.141	tC2Q	RF	2	R36C126[0][A]	u_frame_gen/data_cycle_r_s0/Q
1.597	0.006	tNET	FF	1	R36C126[0][A]	u_frame_gen/next_data_cycle_c_s0/I0
1.750	0.153	tINS	FF	1	R36C126[0][A]	u_frame_gen/next_data_cycle_c_s0/F
1.750	0.000	tNET	FF	1	R36C126[0][A]	u_frame_gen/data_cycle_r_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.450	1.450	tNET	RR	1	R36C126[0][A]	u_frame_gen/data_cycle_r_s0/CLK
1.475	0.025	tHld		1	R36C126[0][A]	u_frame_gen/data_cycle_r_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.450, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.450, 100.000%

Path14

Path Summary:

Slack	0.275
Data Arrival Time	1.742
Data Required Time	1.467
From	u_frame_gen/ifg_size_r_7_s0
To	u_frame_gen/ifg_size_r_7_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.442	1.442	tNET	RR	1	R33C127[0][A]	u_frame_gen/ifg_size_r_7_s0/CLK
1.583	0.141	tC2Q	RF	5	R33C127[0][A]	u_frame_gen/ifg_size_r_7_s0/Q
1.589	0.006	tNET	FF	1	R33C127[0][A]	u_frame_gen/n167_s2/I0
1.742	0.153	tINS	FF	1	R33C127[0][A]	u_frame_gen/n167_s2/F
1.742	0.000	tNET	FF	1	R33C127[0][A]	u_frame_gen/ifg_size_r_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.442	1.442	tNET	RR	1	R33C127[0][A]	u_frame_gen/ifg_size_r_7_s0/CLK
1.467	0.025	tHld		1	R33C127[0][A]	u_frame_gen/ifg_size_r_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.442, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.442, 100.000%

Path15

Path Summary:

Slack	0.275
Data Arrival Time	1.734
Data Required Time	1.459
From	u_ufc_ll_to_axi/u_axi_register_slice/sel_rd_s2
To	u_ufc_ll_to_axi/u_axi_register_slice/sel_rd_s2
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.434	1.434	tNET	RR	1	R31C115[0][A]	u_ufc_ll_to_axi/u_axi_register_slice/sel_rd_s2/CLK
1.575	0.141	tC2Q	RF	17	R31C115[0][A]	u_ufc_ll_to_axi/u_axi_register_slice/sel_rd_s2/Q
1.581	0.006	tNET	FF	1	R31C115[0][A]	u_ufc_ll_to_axi/u_axi_register_slice/n32_s3/I2
1.734	0.153	tINS	FF	1	R31C115[0][A]	u_ufc_ll_to_axi/u_axi_register_slice/n32_s3/F
1.734	0.000	tNET	FF	1	R31C115[0][A]	u_ufc_ll_to_axi/u_axi_register_slice/sel_rd_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.434	1.434	tNET	RR	1	R31C115[0][A]	u_ufc_ll_to_axi/u_axi_register_slice/sel_rd_s2/CLK
1.459	0.025	tHld		1	R31C115[0][A]	u_ufc_ll_to_axi/u_axi_register_slice/sel_rd_s2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.434, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.434, 100.000%

Path16

Path Summary:

Slack	0.275
Data Arrival Time	1.746
Data Required Time	1.471
From	u_ufc_ll_to_axi/u_axi_register_slice/sel_wr_s1
To	u_ufc_ll_to_axi/u_axi_register_slice/sel_wr_s1
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.446	1.446	tNET	RR	1	R33C118[0][A]	u_ufc_ll_to_axi/u_axi_register_slice/sel_wr_s1/CLK
1.587	0.141	tC2Q	RF	3	R33C118[0][A]	u_ufc_ll_to_axi/u_axi_register_slice/sel_wr_s1/Q
1.593	0.006	tNET	FF	1	R33C118[0][A]	u_ufc_ll_to_axi/u_axi_register_slice/n46_s2/I0
1.746	0.153	tINS	FF	1	R33C118[0][A]	u_ufc_ll_to_axi/u_axi_register_slice/n46_s2/F
1.746	0.000	tNET	FF	1	R33C118[0][A]	u_ufc_ll_to_axi/u_axi_register_slice/sel_wr_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.446	1.446	tNET	RR	1	R33C118[0][A]	u_ufc_ll_to_axi/u_axi_register_slice/sel_wr_s1/CLK
1.471	0.025	tHld		1	R33C118[0][A]	u_ufc_ll_to_axi/u_axi_register_slice/sel_wr_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.446, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.446, 100.000%

Path17

Path Summary:

Slack	0.275
Data Arrival Time	1.742
Data Required Time	1.467
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/gen_roralink_lane[0].u0_duplex_mode/u0_sym_dec/rx_na_idles_cntr_0_s1
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/gen_roralink_lane[0].u0_duplex_mode/u0_sym_dec/rx_na_idles_cntr_0_s1
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.442	1.442	tNET	RR	1	R50C122[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/gen_roralink_lane[0].u0_duplex_mode/u0_sym_dec/rx_na_idles_cntr_0_s1/CLK
1.583	0.141	tC2Q	RF	3	R50C122[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/gen_roralink_lane[0].u0_duplex_mode/u0_sym_dec/rx_na_idles_cntr_0_s1/Q
1.589	0.006	tNET	FF	1	R50C122[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/gen_roralink_lane[0].u0_duplex_mode/u0_sym_dec/n321_s3/I2
1.742	0.153	tINS	FF	1	R50C122[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/gen_roralink_lane[0].u0_duplex_mode/u0_sym_dec/n321_s3/F
1.742	0.000	tNET	FF	1	R50C122[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/gen_roralink_lane[0].u0_duplex_mode/u0_sym_dec/rx_na_idles_cntr_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.442	1.442	tNET	RR	1	R50C122[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/gen_roralink_lane[0].u0_duplex_mode/u0_sym_dec/rx_na_idles_cntr_0_s1/CLK
1.467	0.025	tHld		1	R50C122[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/gen_roralink_lane[0].u0_duplex_mode/u0_sym_dec/rx_na_idles_cntr_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.442, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.442, 100.000%

Path18

Path Summary:

Slack	0.275
Data Arrival Time	1.739
Data Required Time	1.464
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/gen_roralink_lane[0].u0_duplex_mode/u0_duplex_init_sm/counter1_r_1_s0
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/gen_roralink_lane[0].u0_duplex_mode/u0_duplex_init_sm/counter1_r_1_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.439	1.439	tNET	RR	1	R52C120[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/gen_roralink_lane[0].u0_duplex_mode/u0_duplex_init_sm/counter1_r_1_s0/CLK
1.580	0.141	tC2Q	RF	2	R52C120[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/gen_roralink_lane[0].u0_duplex_mode/u0_duplex_init_sm/counter1_r_1_s0/Q
1.586	0.006	tNET	FF	1	R52C120[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/gen_roralink_lane[0].u0_duplex_mode/u0_duplex_init_sm/n109_s0/I2
1.739	0.153	tINS	FF	1	R52C120[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/gen_roralink_lane[0].u0_duplex_mode/u0_duplex_init_sm/n109_s0/F
1.739	0.000	tNET	FF	1	R52C120[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/gen_roralink_lane[0].u0_duplex_mode/u0_duplex_init_sm/counter1_r_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.439	1.439	tNET	RR	1	R52C120[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/gen_roralink_lane[0].u0_duplex_mode/u0_duplex_init_sm/counter1_r_1_s0/CLK
1.464	0.025	tHld		1	R52C120[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/gen_roralink_lane[0].u0_duplex_mode/u0_duplex_init_sm/counter1_r_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.439, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.439, 100.000%

Path19

Path Summary:

Slack	0.275
Data Arrival Time	1.730
Data Required Time	1.455
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_standard_cc/count_16d_flop_r_s9
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_standard_cc/count_16d_flop_r_s9
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.430	1.430	tNET	RR	1	R48C121[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_standard_cc/count_16d_flop_r_s9/CLK
1.571	0.141	tC2Q	RF	2	R48C121[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_standard_cc/count_16d_flop_r_s9/Q
1.577	0.006	tNET	FF	1	R48C121[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_standard_cc/n65_s3/I1
1.730	0.153	tINS	FF	1	R48C121[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_standard_cc/n65_s3/F
1.730	0.000	tNET	FF	1	R48C121[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_standard_cc/count_16d_flop_r_s9/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.430	1.430	tNET	RR	1	R48C121[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_standard_cc/count_16d_flop_r_s9/CLK
1.455	0.025	tHld		1	R48C121[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_standard_cc/count_16d_flop_r_s9

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.430, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.430, 100.000%

Path20

Path Summary:

Slack	0.275
Data Arrival Time	1.759
Data Required Time	1.484
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rem_out_2_s1
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rem_out_2_s1
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.459	1.459	tNET	RR	1	R25C129[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rem_out_2_s1/CLK
1.600	0.141	tC2Q	RF	2	R25C129[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rem_out_2_s1/Q
1.606	0.006	tNET	FF	1	R25C129[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/n107_s6/I1
1.759	0.153	tINS	FF	1	R25C129[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/n107_s6/F
1.759	0.000	tNET	FF	1	R25C129[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rem_out_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.459	1.459	tNET	RR	1	R25C129[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rem_out_2_s1/CLK
1.484	0.025	tHld		1	R25C129[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rem_out_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.459, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.459, 100.000%

Path21

Path Summary:

Slack	0.275
Data Arrival Time	1.738
Data Required Time	1.463
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_tx_ll/u_duplex_tx_ll_control_sm/flg_for_ufc_header_r_s2
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_tx_ll/u_duplex_tx_ll_control_sm/flg_for_ufc_header_r_s2
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.438	1.438	tNET	RR	1	R50C115[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_tx_ll/u_duplex_tx_ll_control_sm/flg_for_ufc_header_r_s2/CLK
1.579	0.141	tC2Q	RF	2	R50C115[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_tx_ll/u_duplex_tx_ll_control_sm/flg_for_ufc_header_r_s2/Q
1.585	0.006	tNET	FF	1	R50C115[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_tx_ll/u_duplex_tx_ll_control_sm/n621_s3/I1
1.738	0.153	tINS	FF	1	R50C115[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_tx_ll/u_duplex_tx_ll_control_sm/n621_s3/F
1.738	0.000	tNET	FF	1	R50C115[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_tx_ll/u_duplex_tx_ll_control_sm/flg_for_ufc_header_r_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.438	1.438	tNET	RR	1	R50C115[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_tx_ll/u_duplex_tx_ll_control_sm/flg_for_ufc_header_r_s2/CLK
1.463	0.025	tHld		1	R50C115[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_tx_ll/u_duplex_tx_ll_control_sm/flg_for_ufc_header_r_s2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.438, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.438, 100.000%

Path22

Path Summary:

Slack	0.275
Data Arrival Time	1.734
Data Required Time	1.459
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_axi_to_ll_data/new_pkt_r_s0
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_axi_to_ll_data/new_pkt_r_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.434	1.434	tNET	RR	1	R30C118[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_axi_to_ll_data/new_pkt_r_s0/CLK
1.575	0.141	tC2Q	RF	5	R30C118[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_axi_to_ll_data/new_pkt_r_s0/Q
1.581	0.006	tNET	FF	1	R30C118[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_axi_to_ll_data/new_pkt_s2/I0
1.734	0.153	tINS	FF	1	R30C118[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_axi_to_ll_data/new_pkt_s2/F
1.734	0.000	tNET	FF	1	R30C118[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_axi_to_ll_data/new_pkt_r_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.434	1.434	tNET	RR	1	R30C118[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_axi_to_ll_data/new_pkt_r_s0/CLK
1.459	0.025	tHld		1	R30C118[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_axi_to_ll_data/new_pkt_r_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.434, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.434, 100.000%

Path23

Path Summary:

Slack	0.275
Data Arrival Time	1.726
Data Required Time	1.451
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_global_logic/u_duplex_ch_bond_code_gen/free_count_r_1_s0
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_global_logic/u_duplex_ch_bond_code_gen/free_count_r_1_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.426	1.426	tNET	RR	1	R48C124[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_global_logic/u_duplex_ch_bond_code_gen/free_count_r_1_s0/CLK
1.567	0.141	tC2Q	RF	3	R48C124[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_global_logic/u_duplex_ch_bond_code_gen/free_count_r_1_s0/Q
1.573	0.006	tNET	FF	1	R48C124[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_global_logic/u_duplex_ch_bond_code_gen/n15_s2/I2
1.726	0.153	tINS	FF	1	R48C124[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_global_logic/u_duplex_ch_bond_code_gen/n15_s2/F
1.726	0.000	tNET	FF	1	R48C124[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_global_logic/u_duplex_ch_bond_code_gen/free_count_r_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.426	1.426	tNET	RR	1	R48C124[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_global_logic/u_duplex_ch_bond_code_gen/free_count_r_1_s0/CLK
1.451	0.025	tHld		1	R48C124[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_global_logic/u_duplex_ch_bond_code_gen/free_count_r_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.426, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.426, 100.000%

Path24

Path Summary:

Slack	0.275
Data Arrival Time	1.734
Data Required Time	1.459
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_global_logic/u_duplex_channel_init_sm/chan_bond_timer_8_s0
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_global_logic/u_duplex_channel_init_sm/chan_bond_timer_8_s0
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.434	1.434	tNET	RR	1	R49C125[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_global_logic/u_duplex_channel_init_sm/chan_bond_timer_8_s0/CLK
1.575	0.141	tC2Q	RF	2	R49C125[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_global_logic/u_duplex_channel_init_sm/chan_bond_timer_8_s0/Q
1.581	0.006	tNET	FF	1	R49C125[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_global_logic/u_duplex_channel_init_sm/n143_s2/I2
1.734	0.153	tINS	FF	1	R49C125[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_global_logic/u_duplex_channel_init_sm/n143_s2/F
1.734	0.000	tNET	FF	1	R49C125[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_global_logic/u_duplex_channel_init_sm/chan_bond_timer_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.434	1.434	tNET	RR	1	R49C125[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_global_logic/u_duplex_channel_init_sm/chan_bond_timer_8_s0/CLK
1.459	0.025	tHld		1	R49C125[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_global_logic/u_duplex_channel_init_sm/chan_bond_timer_8_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.434, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.434, 100.000%

Path25

Path Summary:

Slack	0.275
Data Arrival Time	1.733
Data Required Time	1.458
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/head_err_cnt_0_s0
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/head_err_cnt_0_s0
Launch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.433	1.433	tNET	RR	1	R22C90[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/head_err_cnt_0_s0/CLK
1.574	0.141	tC2Q	RF	3	R22C90[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/head_err_cnt_0_s0/Q
1.580	0.006	tNET	FF	1	R22C90[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/n241_6_3_s0/I0
1.733	0.153	tINS	FF	1	R22C90[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/n241_6_3_s0/F
1.733	0.000	tNET	FF	1	R22C90[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/head_err_cnt_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
1.433	1.433	tNET	RR	1	R22C90[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/head_err_cnt_0_s0/CLK
1.458	0.025	tHld		1	R22C90[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/head_err_cnt_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.433, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.433, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	4.373
Data Arrival Time	8.240
Data Required Time	12.613
From	u1_reset_gen/o_rst1_s1
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_rst_srl_0_s0
Launch Clk	cfg_clk:[R]
Latch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
2.914	2.914	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
3.220	0.306	tC2Q	RR	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
5.813	2.593	tNET	RR	1	R4C121[0][A]	gt_pcs_rx_rst_s1/I0
6.276	0.463	tINS	RR	2	R4C121[0][A]	gt_pcs_rx_rst_s1/F
6.280	0.004	tNET	RR	1	R4C121[0][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_arst_s2/I0
6.511	0.231	tINS	RR	1	R4C121[0][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_arst_s2/F
7.443	0.932	tNET	RR	1	R30C112[0][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_arst_s1/I2
7.786	0.343	tINS	RF	3	R30C112[0][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_arst_s1/F
8.240	0.454	tNET	FF	1	R33C111[1][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_rst_srl_0_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.926	2.926	tNET	RR	1	R33C111[1][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_rst_srl_0_s0/CLK
12.891	-0.035	tUnc
12.613	-0.278	tSu		1	R33C111[1][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_rst_srl_0_s0

Path Statistics:

Clock Skew	0.012
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.914, 100.000%
Arrival Data Path Delay	cell: 1.037, 19.469%; route: 3.984, 74.786%; tC2Q: 0.306, 5.745%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.926, 100.000%

Path2

Path Summary:

Slack	4.373
Data Arrival Time	8.240
Data Required Time	12.613
From	u1_reset_gen/o_rst1_s1
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_rst_srl_1_s0
Launch Clk	cfg_clk:[R]
Latch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
2.914	2.914	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
3.220	0.306	tC2Q	RR	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
5.813	2.593	tNET	RR	1	R4C121[0][A]	gt_pcs_rx_rst_s1/I0
6.276	0.463	tINS	RR	2	R4C121[0][A]	gt_pcs_rx_rst_s1/F
6.280	0.004	tNET	RR	1	R4C121[0][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_arst_s2/I0
6.511	0.231	tINS	RR	1	R4C121[0][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_arst_s2/F
7.443	0.932	tNET	RR	1	R30C112[0][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_arst_s1/I2
7.786	0.343	tINS	RF	3	R30C112[0][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_arst_s1/F
8.240	0.454	tNET	FF	1	R33C111[2][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_rst_srl_1_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.926	2.926	tNET	RR	1	R33C111[2][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_rst_srl_1_s0/CLK
12.891	-0.035	tUnc
12.613	-0.278	tSu		1	R33C111[2][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_rst_srl_1_s0

Path Statistics:

Clock Skew	0.012
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.914, 100.000%
Arrival Data Path Delay	cell: 1.037, 19.469%; route: 3.984, 74.786%; tC2Q: 0.306, 5.745%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.926, 100.000%

Path3

Path Summary:

Slack	4.373
Data Arrival Time	8.240
Data Required Time	12.613
From	u1_reset_gen/o_rst1_s1
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_rst_srl_2_s0
Launch Clk	cfg_clk:[R]
Latch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
2.914	2.914	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
3.220	0.306	tC2Q	RR	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
5.813	2.593	tNET	RR	1	R4C121[0][A]	gt_pcs_rx_rst_s1/I0
6.276	0.463	tINS	RR	2	R4C121[0][A]	gt_pcs_rx_rst_s1/F
6.280	0.004	tNET	RR	1	R4C121[0][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_arst_s2/I0
6.511	0.231	tINS	RR	1	R4C121[0][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_arst_s2/F
7.443	0.932	tNET	RR	1	R30C112[0][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_arst_s1/I2
7.786	0.343	tINS	RF	3	R30C112[0][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_arst_s1/F
8.240	0.454	tNET	FF	1	R33C111[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_rst_srl_2_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.926	2.926	tNET	RR	1	R33C111[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_rst_srl_2_s0/CLK
12.891	-0.035	tUnc
12.613	-0.278	tSu		1	R33C111[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/rx_rst_srl_2_s0

Path Statistics:

Clock Skew	0.012
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.914, 100.000%
Arrival Data Path Delay	cell: 1.037, 19.469%; route: 3.984, 74.786%; tC2Q: 0.306, 5.745%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.926, 100.000%

Path4

Path Summary:

Slack	6.976
Data Arrival Time	15.653
Data Required Time	22.629
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/o_serdes_rx_blocksync_s2
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_srl_2_s0
Launch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.948	2.949	tNET	RR	1	R21C92[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/o_serdes_rx_blocksync_s2/CLK
13.254	0.306	tC2Q	RR	73	R21C92[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/o_serdes_rx_blocksync_s2/Q
15.163	1.909	tNET	RR	1	R44C102[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_async_s1/I2
15.370	0.207	tINS	RF	7	R44C102[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_async_s1/F
15.653	0.283	tNET	FF	1	R44C100[2][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_srl_2_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cfg_clk
20.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
22.942	2.942	tNET	RR	1	R44C100[2][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_srl_2_s0/CLK
22.907	-0.035	tUnc
22.629	-0.278	tSu		1	R44C100[2][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_srl_2_s0

Path Statistics:

Clock Skew	-0.006
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.949, 100.000%
Arrival Data Path Delay	cell: 0.207, 7.652%; route: 2.192, 81.035%; tC2Q: 0.306, 11.312%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.942, 100.000%

Path5

Path Summary:

Slack	6.976
Data Arrival Time	15.653
Data Required Time	22.629
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/o_serdes_rx_blocksync_s2
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_srl_0_s0
Launch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.948	2.949	tNET	RR	1	R21C92[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/o_serdes_rx_blocksync_s2/CLK
13.254	0.306	tC2Q	RR	73	R21C92[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/o_serdes_rx_blocksync_s2/Q
15.163	1.909	tNET	RR	1	R44C102[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_async_s1/I2
15.370	0.207	tINS	RF	7	R44C102[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_async_s1/F
15.653	0.283	tNET	FF	1	R44C100[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_srl_0_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cfg_clk
20.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
22.942	2.942	tNET	RR	1	R44C100[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_srl_0_s0/CLK
22.907	-0.035	tUnc
22.629	-0.278	tSu		1	R44C100[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_srl_0_s0

Path Statistics:

Clock Skew	-0.006
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.949, 100.000%
Arrival Data Path Delay	cell: 0.207, 7.652%; route: 2.192, 81.035%; tC2Q: 0.306, 11.312%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.942, 100.000%

Path6

Path Summary:

Slack	6.976
Data Arrival Time	15.653
Data Required Time	22.629
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/o_serdes_rx_blocksync_s2
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_srl_1_s0
Launch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.948	2.949	tNET	RR	1	R21C92[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/o_serdes_rx_blocksync_s2/CLK
13.254	0.306	tC2Q	RR	73	R21C92[0][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/o_serdes_rx_blocksync_s2/Q
15.163	1.909	tNET	RR	1	R44C102[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_async_s1/I2
15.370	0.207	tINS	RF	7	R44C102[2][B]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_async_s1/F
15.653	0.283	tNET	FF	1	R44C100[3][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_srl_1_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cfg_clk
20.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
22.942	2.942	tNET	RR	1	R44C100[3][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_srl_1_s0/CLK
22.907	-0.035	tUnc
22.629	-0.278	tSu		1	R44C100[3][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/hpcnt_reset_srl_1_s0

Path Statistics:

Clock Skew	-0.006
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.949, 100.000%
Arrival Data Path Delay	cell: 0.207, 7.652%; route: 2.192, 81.035%; tC2Q: 0.306, 11.312%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.942, 100.000%

Path7

Path Summary:

Slack	7.773
Data Arrival Time	4.919
Data Required Time	12.691
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/fsm_st_curr_1_s0
Launch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.920	2.920	tNET	RR	1	R34C110[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/CLK
3.214	0.294	tC2Q	RF	17	R34C110[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/Q
4.919	1.705	tNET	FF	1	R18C91[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/fsm_st_curr_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.969	2.970	tNET	RR	1	R18C91[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/fsm_st_curr_1_s0/CLK
12.691	-0.278	tSu		1	R18C91[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/fsm_st_curr_1_s0

Path Statistics:

Clock Skew	0.049
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.920, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.705, 85.293%; tC2Q: 0.294, 14.707%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.970, 100.000%

Path8

Path Summary:

Slack	7.910
Data Arrival Time	4.735
Data Required Time	12.645
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/fsm_st_curr_0_s0
Launch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.920	2.920	tNET	RR	1	R34C110[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/CLK
3.214	0.294	tC2Q	RF	17	R34C110[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/Q
4.735	1.521	tNET	FF	1	R18C92[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/fsm_st_curr_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.923	2.923	tNET	RR	1	R18C92[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/fsm_st_curr_0_s0/CLK
12.645	-0.278	tSu		1	R18C92[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/fsm_st_curr_0_s0

Path Statistics:

Clock Skew	0.003
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.920, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.521, 83.802%; tC2Q: 0.294, 16.198%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.923, 100.000%

Path9

Path Summary:

Slack	8.108
Data Arrival Time	4.560
Data Required Time	12.668
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/fsm_st_curr_2_s0
Launch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]
Latch Clk	u_SerDes_Top/q1_lane1_fabric_rx_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.920	2.920	tNET	RR	1	R34C110[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/CLK
3.214	0.294	tC2Q	RF	17	R34C110[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/rst_o_s0/Q
4.560	1.346	tNET	FF	1	R22C92[3][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/fsm_st_curr_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000	0.000	tCL	RR	1773	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
12.946	2.947	tNET	RR	1	R22C92[3][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/fsm_st_curr_2_s0/CLK
12.668	-0.278	tSu		1	R22C92[3][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/fsm_st_curr_2_s0

Path Statistics:

Clock Skew	0.026
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.920, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.346, 82.073%; tC2Q: 0.294, 17.927%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.947, 100.000%

Path10

Path Summary:

Slack	15.664
Data Arrival Time	6.997
Data Required Time	22.661
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wp_rd_g2b_ptr_3_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
2.914	2.914	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
3.208	0.294	tC2Q	RF	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
6.997	3.789	tNET	FF	1	R4C114[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wp_rd_g2b_ptr_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cfg_clk
20.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
22.939	2.939	tNET	RR	1	R4C114[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wp_rd_g2b_ptr_3_s0/CLK
22.661	-0.278	tSu		1	R4C114[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wp_rd_g2b_ptr_3_s0

Path Statistics:

Clock Skew	0.025
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.914, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.789, 92.799%; tC2Q: 0.294, 7.201%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.939, 100.000%

Path11

Path Summary:

Slack	15.667
Data Arrival Time	6.997
Data Required Time	22.663
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wp_rd_gray_ptr_3_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
2.914	2.914	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
3.208	0.294	tC2Q	RF	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
6.997	3.789	tNET	FF	1	R3C114[0][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wp_rd_gray_ptr_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cfg_clk
20.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
22.941	2.941	tNET	RR	1	R3C114[0][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wp_rd_gray_ptr_3_s0/CLK
22.663	-0.278	tSu		1	R3C114[0][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wp_rd_gray_ptr_3_s0

Path Statistics:

Clock Skew	0.027
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.914, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.789, 92.799%; tC2Q: 0.294, 7.201%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.941, 100.000%

Path12

Path Summary:

Slack	15.667
Data Arrival Time	6.997
Data Required Time	22.663
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wp_rd_gray_ptr1_3_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
2.914	2.914	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
3.208	0.294	tC2Q	RF	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
6.997	3.789	tNET	FF	1	R3C114[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wp_rd_gray_ptr1_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cfg_clk
20.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
22.941	2.941	tNET	RR	1	R3C114[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wp_rd_gray_ptr1_3_s0/CLK
22.663	-0.278	tSu		1	R3C114[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wp_rd_gray_ptr1_3_s0

Path Statistics:

Clock Skew	0.027
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.914, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.789, 92.799%; tC2Q: 0.294, 7.201%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.941, 100.000%

Path13

Path Summary:

Slack	15.828
Data Arrival Time	6.829
Data Required Time	22.657
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wp_rd_g2b_ptr_2_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
2.914	2.914	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
3.208	0.294	tC2Q	RF	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
6.829	3.621	tNET	FF	1	R6C114[0][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wp_rd_g2b_ptr_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cfg_clk
20.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
22.935	2.935	tNET	RR	1	R6C114[0][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wp_rd_g2b_ptr_2_s0/CLK
22.657	-0.278	tSu		1	R6C114[0][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wp_rd_g2b_ptr_2_s0

Path Statistics:

Clock Skew	0.021
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.914, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.621, 92.490%; tC2Q: 0.294, 7.510%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.935, 100.000%

Path14

Path Summary:

Slack	15.995
Data Arrival Time	6.660
Data Required Time	22.655
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wp_rd_g2b_ptr_1_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
2.914	2.914	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
3.208	0.294	tC2Q	RF	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
6.661	3.453	tNET	FF	1	R7C114[1][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wp_rd_g2b_ptr_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cfg_clk
20.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
22.933	2.933	tNET	RR	1	R7C114[1][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wp_rd_g2b_ptr_1_s0/CLK
22.655	-0.278	tSu		1	R7C114[1][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wp_rd_g2b_ptr_1_s0

Path Statistics:

Clock Skew	0.019
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.914, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.453, 92.153%; tC2Q: 0.294, 7.847%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.933, 100.000%

Path15

Path Summary:

Slack	16.158
Data Arrival Time	6.486
Data Required Time	22.644
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wp_rd_g2b_ptr_0_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
2.914	2.914	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
3.208	0.294	tC2Q	RF	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
6.485	3.278	tNET	FF	1	R9C114[1][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wp_rd_g2b_ptr_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cfg_clk
20.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
22.922	2.922	tNET	RR	1	R9C114[1][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wp_rd_g2b_ptr_0_s0/CLK
22.644	-0.278	tSu		1	R9C114[1][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wp_rd_g2b_ptr_0_s0

Path Statistics:

Clock Skew	0.008
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.914, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.278, 91.769%; tC2Q: 0.294, 8.231%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.922, 100.000%

Path16

Path Summary:

Slack	16.158
Data Arrival Time	6.486
Data Required Time	22.644
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wp_rd_gray_ptr1_0_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
2.914	2.914	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
3.208	0.294	tC2Q	RF	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
6.485	3.278	tNET	FF	1	R9C114[1][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wp_rd_gray_ptr1_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cfg_clk
20.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
22.922	2.922	tNET	RR	1	R9C114[1][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wp_rd_gray_ptr1_0_s0/CLK
22.644	-0.278	tSu		1	R9C114[1][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/wp_rd_gray_ptr1_0_s0

Path Statistics:

Clock Skew	0.008
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.914, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.278, 91.769%; tC2Q: 0.294, 8.231%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.922, 100.000%

Path17

Path Summary:

Slack	16.236
Data Arrival Time	6.403
Data Required Time	22.639
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/rd_gray_ptr_2_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
2.914	2.914	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
3.208	0.294	tC2Q	RF	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
6.404	3.196	tNET	FF	1	R11C115[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/rd_gray_ptr_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cfg_clk
20.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
22.917	2.918	tNET	RR	1	R11C115[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/rd_gray_ptr_2_s0/CLK
22.639	-0.278	tSu		1	R11C115[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/rd_gray_ptr_2_s0

Path Statistics:

Clock Skew	0.004
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.914, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.196, 91.575%; tC2Q: 0.294, 8.425%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.918, 100.000%

Path18

Path Summary:

Slack	16.404
Data Arrival Time	6.236
Data Required Time	22.639
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/rd1_ptr_1_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
2.914	2.914	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
3.208	0.294	tC2Q	RF	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
6.236	3.028	tNET	FF	1	R11C113[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/rd1_ptr_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cfg_clk
20.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
22.917	2.918	tNET	RR	1	R11C113[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/rd1_ptr_1_s0/CLK
22.639	-0.278	tSu		1	R11C113[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/rd1_ptr_1_s0

Path Statistics:

Clock Skew	0.004
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.914, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.028, 91.149%; tC2Q: 0.294, 8.851%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.918, 100.000%

Path19

Path Summary:

Slack	16.411
Data Arrival Time	6.236
Data Required Time	22.647
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/rd1_ptr_0_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
2.914	2.914	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
3.208	0.294	tC2Q	RF	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
6.236	3.028	tNET	FF	1	R11C112[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/rd1_ptr_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cfg_clk
20.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
22.925	2.925	tNET	RR	1	R11C112[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/rd1_ptr_0_s0/CLK
22.647	-0.278	tSu		1	R11C112[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/rd1_ptr_0_s0

Path Statistics:

Clock Skew	0.011
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.914, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 3.028, 91.149%; tC2Q: 0.294, 8.851%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.925, 100.000%

Path20

Path Summary:

Slack	16.515
Data Arrival Time	6.128
Data Required Time	22.644
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tx_data_reg_1_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
2.914	2.914	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
3.208	0.294	tC2Q	RF	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
6.128	2.921	tNET	FF	1	R9C122[3][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tx_data_reg_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cfg_clk
20.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
22.922	2.922	tNET	RR	1	R9C122[3][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tx_data_reg_1_s0/CLK
22.644	-0.278	tSu		1	R9C122[3][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tx_data_reg_1_s0

Path Statistics:

Clock Skew	0.008
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.914, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.921, 90.854%; tC2Q: 0.294, 9.146%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.922, 100.000%

Path21

Path Summary:

Slack	16.515
Data Arrival Time	6.128
Data Required Time	22.644
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tx_data_reg_4_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
2.914	2.914	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
3.208	0.294	tC2Q	RF	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
6.128	2.921	tNET	FF	1	R9C122[1][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tx_data_reg_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cfg_clk
20.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
22.922	2.922	tNET	RR	1	R9C122[1][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tx_data_reg_4_s0/CLK
22.644	-0.278	tSu		1	R9C122[1][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/tx_data_reg_4_s0

Path Statistics:

Clock Skew	0.008
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.914, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.921, 90.854%; tC2Q: 0.294, 9.146%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.922, 100.000%

Path22

Path Summary:

Slack	16.515
Data Arrival Time	6.128
Data Required Time	22.644
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
2.914	2.914	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
3.208	0.294	tC2Q	RF	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
6.128	2.921	tNET	FF	1	R9C122[0][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cfg_clk
20.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
22.922	2.922	tNET	RR	1	R9C122[0][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s0/CLK
22.644	-0.278	tSu		1	R9C122[0][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s0

Path Statistics:

Clock Skew	0.008
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.914, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.921, 90.854%; tC2Q: 0.294, 9.146%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.922, 100.000%

Path23

Path Summary:

Slack	16.586
Data Arrival Time	6.053
Data Required Time	22.639
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/rp_wr_g2b_ptr_1_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
2.914	2.914	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
3.208	0.294	tC2Q	RF	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
6.054	2.846	tNET	FF	1	R11C111[0][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/rp_wr_g2b_ptr_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cfg_clk
20.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
22.917	2.918	tNET	RR	1	R11C111[0][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/rp_wr_g2b_ptr_1_s0/CLK
22.639	-0.278	tSu		1	R11C111[0][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/rp_wr_g2b_ptr_1_s0

Path Statistics:

Clock Skew	0.004
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.914, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.846, 90.636%; tC2Q: 0.294, 9.364%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.918, 100.000%

Path24

Path Summary:

Slack	16.586
Data Arrival Time	6.053
Data Required Time	22.639
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/rp_wr_g2b_ptr_2_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
2.914	2.914	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
3.208	0.294	tC2Q	RF	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
6.054	2.846	tNET	FF	1	R11C111[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/rp_wr_g2b_ptr_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cfg_clk
20.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
22.917	2.918	tNET	RR	1	R11C111[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/rp_wr_g2b_ptr_2_s0/CLK
22.639	-0.278	tSu		1	R11C111[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/rp_wr_g2b_ptr_2_s0

Path Statistics:

Clock Skew	0.004
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.914, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.846, 90.636%; tC2Q: 0.294, 9.364%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.918, 100.000%

Path25

Path Summary:

Slack	16.586
Data Arrival Time	6.053
Data Required Time	22.639
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/rp_wr_g2b_ptr_3_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
2.914	2.914	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
3.208	0.294	tC2Q	RF	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
6.054	2.846	tNET	FF	1	R11C111[1][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/rp_wr_g2b_ptr_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cfg_clk
20.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
22.917	2.918	tNET	RR	1	R11C111[1][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/rp_wr_g2b_ptr_3_s0/CLK
22.639	-0.278	tSu		1	R11C111[1][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/rp_wr_g2b_ptr_3_s0

Path Statistics:

Clock Skew	0.004
Setup Relationship	20.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.914, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.846, 90.636%; tC2Q: 0.294, 9.364%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.918, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.321
Data Arrival Time	1.711
Data Required Time	1.390
From	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_reset_cbcc/cbcc_reset_cbstg2_rd_clk_s0
To	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/master.master/alignment_done_r_s1
Launch Clk	sys_clk:[R]
Latch Clk	sys_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.430	1.430	tNET	RR	1	R48C105[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_reset_cbcc/cbcc_reset_cbstg2_rd_clk_s0/CLK
1.574	0.144	tC2Q	RR	16	R48C105[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_reset_cbcc/cbcc_reset_cbstg2_rd_clk_s0/Q
1.711	0.137	tNET	RR	1	R47C106[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/master.master/alignment_done_r_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					sys_clk
0.000	0.000	tCL	RR	4522	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK
1.443	1.443	tNET	RR	1	R47C106[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/master.master/alignment_done_r_s1/CLK
1.390	-0.053	tHld		1	R47C106[1][A]	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/master.master/alignment_done_r_s1

Path Statistics:

Clock Skew	0.013
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.430, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.137, 48.754%; tC2Q: 0.144, 51.246%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.443, 100.000%

Path2

Path Summary:

Slack	0.397
Data Arrival Time	1.754
Data Required Time	1.357
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/addr_param_3_s1
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.406	1.406	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
1.550	0.144	tC2Q	RR	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
1.754	0.204	tNET	RR	1	R14C104[1][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/addr_param_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.410	1.410	tNET	RR	1	R14C104[1][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/addr_param_3_s1/CLK
1.357	-0.053	tHld		1	R14C104[1][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/addr_param_3_s1

Path Statistics:

Clock Skew	0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.406, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.204, 58.621%; tC2Q: 0.144, 41.379%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.410, 100.000%

Path3

Path Summary:

Slack	0.397
Data Arrival Time	1.754
Data Required Time	1.357
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/addr_param_7_s1
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.406	1.406	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
1.550	0.144	tC2Q	RR	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
1.754	0.204	tNET	RR	1	R14C104[0][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/addr_param_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.410	1.410	tNET	RR	1	R14C104[0][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/addr_param_7_s1/CLK
1.357	-0.053	tHld		1	R14C104[0][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/addr_param_7_s1

Path Statistics:

Clock Skew	0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.406, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.204, 58.621%; tC2Q: 0.144, 41.379%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.410, 100.000%

Path4

Path Summary:

Slack	0.397
Data Arrival Time	1.754
Data Required Time	1.357
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/addr_param_11_s1
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.406	1.406	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
1.550	0.144	tC2Q	RR	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
1.754	0.204	tNET	RR	1	R14C104[1][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/addr_param_11_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.410	1.410	tNET	RR	1	R14C104[1][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/addr_param_11_s1/CLK
1.357	-0.053	tHld		1	R14C104[1][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/addr_param_11_s1

Path Statistics:

Clock Skew	0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.406, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.204, 58.621%; tC2Q: 0.144, 41.379%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.410, 100.000%

Path5

Path Summary:

Slack	0.397
Data Arrival Time	1.754
Data Required Time	1.357
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/addr_param_15_s1
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.406	1.406	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
1.550	0.144	tC2Q	RR	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
1.754	0.204	tNET	RR	1	R14C104[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/addr_param_15_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.410	1.410	tNET	RR	1	R14C104[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/addr_param_15_s1/CLK
1.357	-0.053	tHld		1	R14C104[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/addr_param_15_s1

Path Statistics:

Clock Skew	0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.406, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.204, 58.621%; tC2Q: 0.144, 41.379%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.410, 100.000%

Path6

Path Summary:

Slack	0.397
Data Arrival Time	1.754
Data Required Time	1.357
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/rx_fifo_wdata_35_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.406	1.406	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
1.550	0.144	tC2Q	RR	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
1.754	0.204	tNET	RR	1	R14C104[2][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/rx_fifo_wdata_35_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.410	1.410	tNET	RR	1	R14C104[2][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/rx_fifo_wdata_35_s0/CLK
1.357	-0.053	tHld		1	R14C104[2][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/rx_fifo_wdata_35_s0

Path Statistics:

Clock Skew	0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.406, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.204, 58.621%; tC2Q: 0.144, 41.379%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.410, 100.000%

Path7

Path Summary:

Slack	0.397
Data Arrival Time	1.754
Data Required Time	1.357
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/rx_fifo_wdata_43_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.406	1.406	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
1.550	0.144	tC2Q	RR	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
1.754	0.204	tNET	RR	1	R14C104[2][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/rx_fifo_wdata_43_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.410	1.410	tNET	RR	1	R14C104[2][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/rx_fifo_wdata_43_s0/CLK
1.357	-0.053	tHld		1	R14C104[2][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/rx_fifo_wdata_43_s0

Path Statistics:

Clock Skew	0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.406, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.204, 58.621%; tC2Q: 0.144, 41.379%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.410, 100.000%

Path8

Path Summary:

Slack	0.397
Data Arrival Time	1.754
Data Required Time	1.357
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/rx_fifo_wdata_47_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.406	1.406	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
1.550	0.144	tC2Q	RR	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
1.754	0.204	tNET	RR	1	R14C104[3][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/rx_fifo_wdata_47_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.410	1.410	tNET	RR	1	R14C104[3][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/rx_fifo_wdata_47_s0/CLK
1.357	-0.053	tHld		1	R14C104[3][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/rx_fifo_wdata_47_s0

Path Statistics:

Clock Skew	0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.406, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.204, 58.621%; tC2Q: 0.144, 41.379%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.410, 100.000%

Path9

Path Summary:

Slack	0.401
Data Arrival Time	1.754
Data Required Time	1.353
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/fsm_st_curr_0_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.406	1.406	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
1.550	0.144	tC2Q	RR	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
1.754	0.204	tNET	RR	1	R14C105[1][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/fsm_st_curr_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.406	1.406	tNET	RR	1	R14C105[1][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/fsm_st_curr_0_s0/CLK
1.353	-0.053	tHld		1	R14C105[1][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/fsm_st_curr_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.406, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.204, 58.621%; tC2Q: 0.144, 41.379%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.406, 100.000%

Path10

Path Summary:

Slack	0.401
Data Arrival Time	1.754
Data Required Time	1.353
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/fsm_st_curr_1_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.406	1.406	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
1.550	0.144	tC2Q	RR	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
1.754	0.204	tNET	RR	1	R14C105[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/fsm_st_curr_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.406	1.406	tNET	RR	1	R14C105[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/fsm_st_curr_1_s0/CLK
1.353	-0.053	tHld		1	R14C105[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/fsm_st_curr_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.406, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.204, 58.621%; tC2Q: 0.144, 41.379%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.406, 100.000%

Path11

Path Summary:

Slack	0.401
Data Arrival Time	1.754
Data Required Time	1.353
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/fsm_st_curr_2_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.406	1.406	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
1.550	0.144	tC2Q	RR	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
1.754	0.204	tNET	RR	1	R14C105[0][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/fsm_st_curr_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.406	1.406	tNET	RR	1	R14C105[0][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/fsm_st_curr_2_s0/CLK
1.353	-0.053	tHld		1	R14C105[0][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/fsm_st_curr_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.406, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.204, 58.621%; tC2Q: 0.144, 41.379%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.406, 100.000%

Path12

Path Summary:

Slack	0.409
Data Arrival Time	1.758
Data Required Time	1.349
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_4_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.406	1.406	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
1.550	0.144	tC2Q	RR	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
1.758	0.208	tNET	RR	1	R13C107[1][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.402	1.402	tNET	RR	1	R13C107[1][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_4_s0/CLK
1.349	-0.053	tHld		1	R13C107[1][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_4_s0

Path Statistics:

Clock Skew	-0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.406, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.208, 59.091%; tC2Q: 0.144, 40.909%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.402, 100.000%

Path13

Path Summary:

Slack	0.409
Data Arrival Time	1.758
Data Required Time	1.349
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_6_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.406	1.406	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
1.550	0.144	tC2Q	RR	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
1.758	0.208	tNET	RR	1	R13C107[2][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_6_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.402	1.402	tNET	RR	1	R13C107[2][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_6_s0/CLK
1.349	-0.053	tHld		1	R13C107[2][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_6_s0

Path Statistics:

Clock Skew	-0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.406, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.208, 59.091%; tC2Q: 0.144, 40.909%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.402, 100.000%

Path14

Path Summary:

Slack	0.409
Data Arrival Time	1.758
Data Required Time	1.349
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_7_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.406	1.406	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
1.550	0.144	tC2Q	RR	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
1.758	0.208	tNET	RR	1	R13C107[2][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_7_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.402	1.402	tNET	RR	1	R13C107[2][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_7_s0/CLK
1.349	-0.053	tHld		1	R13C107[2][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_7_s0

Path Statistics:

Clock Skew	-0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.406, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.208, 59.091%; tC2Q: 0.144, 40.909%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.402, 100.000%

Path15

Path Summary:

Slack	0.409
Data Arrival Time	1.758
Data Required Time	1.349
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_11_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.406	1.406	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
1.550	0.144	tC2Q	RR	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
1.758	0.208	tNET	RR	1	R13C107[1][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_11_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.402	1.402	tNET	RR	1	R13C107[1][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_11_s0/CLK
1.349	-0.053	tHld		1	R13C107[1][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_11_s0

Path Statistics:

Clock Skew	-0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.406, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.208, 59.091%; tC2Q: 0.144, 40.909%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.402, 100.000%

Path16

Path Summary:

Slack	0.411
Data Arrival Time	1.752
Data Required Time	1.341
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/data_param_9_s1
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.406	1.406	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
1.550	0.144	tC2Q	RR	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
1.752	0.202	tNET	RR	1	R12C106[2][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/data_param_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.394	1.394	tNET	RR	1	R12C106[2][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/data_param_9_s1/CLK
1.341	-0.053	tHld		1	R12C106[2][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/data_param_9_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.406, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.202, 58.382%; tC2Q: 0.144, 41.618%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.394, 100.000%

Path17

Path Summary:

Slack	0.411
Data Arrival Time	1.752
Data Required Time	1.341
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/data_param_13_s1
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.406	1.406	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
1.550	0.144	tC2Q	RR	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
1.752	0.202	tNET	RR	1	R12C106[2][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/data_param_13_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.394	1.394	tNET	RR	1	R12C106[2][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/data_param_13_s1/CLK
1.341	-0.053	tHld		1	R12C106[2][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/data_param_13_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.406, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.202, 58.382%; tC2Q: 0.144, 41.618%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.394, 100.000%

Path18

Path Summary:

Slack	0.411
Data Arrival Time	1.752
Data Required Time	1.341
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/data_param_17_s1
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.406	1.406	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
1.550	0.144	tC2Q	RR	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
1.752	0.202	tNET	RR	1	R12C106[1][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/data_param_17_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.394	1.394	tNET	RR	1	R12C106[1][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/data_param_17_s1/CLK
1.341	-0.053	tHld		1	R12C106[1][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/data_param_17_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.406, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.202, 58.382%; tC2Q: 0.144, 41.618%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.394, 100.000%

Path19

Path Summary:

Slack	0.411
Data Arrival Time	1.752
Data Required Time	1.341
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/data_param_21_s1
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.406	1.406	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
1.550	0.144	tC2Q	RR	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
1.752	0.202	tNET	RR	1	R12C106[1][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/data_param_21_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.394	1.394	tNET	RR	1	R12C106[1][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/data_param_21_s1/CLK
1.341	-0.053	tHld		1	R12C106[1][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/data_param_21_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.406, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.202, 58.382%; tC2Q: 0.144, 41.618%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.394, 100.000%

Path20

Path Summary:

Slack	0.411
Data Arrival Time	1.752
Data Required Time	1.341
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/data_param_25_s1
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.406	1.406	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
1.550	0.144	tC2Q	RR	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
1.752	0.202	tNET	RR	1	R12C106[0][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/data_param_25_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.394	1.394	tNET	RR	1	R12C106[0][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/data_param_25_s1/CLK
1.341	-0.053	tHld		1	R12C106[0][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/data_param_25_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.406, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.202, 58.382%; tC2Q: 0.144, 41.618%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.394, 100.000%

Path21

Path Summary:

Slack	0.411
Data Arrival Time	1.752
Data Required Time	1.341
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/data_param_29_s1
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.406	1.406	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
1.550	0.144	tC2Q	RR	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
1.752	0.202	tNET	RR	1	R12C106[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/data_param_29_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.394	1.394	tNET	RR	1	R12C106[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/data_param_29_s1/CLK
1.341	-0.053	tHld		1	R12C106[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/data_param_29_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.406, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.202, 58.382%; tC2Q: 0.144, 41.618%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.394, 100.000%

Path22

Path Summary:

Slack	0.413
Data Arrival Time	1.758
Data Required Time	1.345
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_1_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.406	1.406	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
1.550	0.144	tC2Q	RR	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
1.758	0.208	tNET	RR	1	R12C107[1][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.398	1.398	tNET	RR	1	R12C107[1][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_1_s0/CLK
1.345	-0.053	tHld		1	R12C107[1][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_1_s0

Path Statistics:

Clock Skew	-0.008
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.406, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.208, 59.091%; tC2Q: 0.144, 40.909%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.398, 100.000%

Path23

Path Summary:

Slack	0.413
Data Arrival Time	1.758
Data Required Time	1.345
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_5_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.406	1.406	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
1.550	0.144	tC2Q	RR	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
1.758	0.208	tNET	RR	1	R12C107[2][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.398	1.398	tNET	RR	1	R12C107[2][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_5_s0/CLK
1.345	-0.053	tHld		1	R12C107[2][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_5_s0

Path Statistics:

Clock Skew	-0.008
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.406, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.208, 59.091%; tC2Q: 0.144, 40.909%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.398, 100.000%

Path24

Path Summary:

Slack	0.413
Data Arrival Time	1.758
Data Required Time	1.345
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_8_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.406	1.406	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
1.550	0.144	tC2Q	RR	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
1.758	0.208	tNET	RR	1	R12C107[2][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_8_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.398	1.398	tNET	RR	1	R12C107[2][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_8_s0/CLK
1.345	-0.053	tHld		1	R12C107[2][B]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_8_s0

Path Statistics:

Clock Skew	-0.008
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.406, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.208, 59.091%; tC2Q: 0.144, 40.909%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.398, 100.000%

Path25

Path Summary:

Slack	0.413
Data Arrival Time	1.758
Data Required Time	1.345
From	u1_reset_gen/o_rst1_s1
To	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_12_s0
Launch Clk	cfg_clk:[R]
Latch Clk	cfg_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.406	1.406	tNET	RR	1	R14C107[0][A]	u1_reset_gen/o_rst1_s1/CLK
1.550	0.144	tC2Q	RR	444	R14C107[0][A]	u1_reset_gen/o_rst1_s1/Q
1.758	0.208	tNET	RR	1	R12C107[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_12_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cfg_clk
0.000	0.000	tCL	RR	2032	PLL_R[3]	u_Gowin_PLL/PLL_inst/CLKOUT0
1.398	1.398	tNET	RR	1	R12C107[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_12_s0/CLK
1.345	-0.053	tHld		1	R12C107[0][A]	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/divclk_cnt_12_s0

Path Statistics:

Clock Skew	-0.008
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.406, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.208, 59.091%; tC2Q: 0.144, 40.909%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.398, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	2.886
Actual Width:	3.748
Required Width:	0.862
Type:	Low Pulse Width
Clock:	u_SerDes_Top/q1_lane1_fabric_rx_clk
Objects:	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			u_SerDes_Top/q1_lane1_fabric_rx_clk
5.000	0.000	tCL	FF	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.668	2.668	tNET	FF	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000	0.000	tCL	RR	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
11.416	1.416	tNET	RR	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/CLKA

MPW2

MPW Summary:

Slack:	2.890
Actual Width:	3.752
Required Width:	0.862
Type:	Low Pulse Width
Clock:	u_SerDes_Top/q1_lane1_fabric_rx_clk
Objects:	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			u_SerDes_Top/q1_lane1_fabric_rx_clk
5.000	0.000	tCL	FF	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.660	2.660	tNET	FF	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000	0.000	tCL	RR	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
11.412	1.412	tNET	RR	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/CLKA

MPW3

MPW Summary:

Slack:	2.890
Actual Width:	3.752
Required Width:	0.862
Type:	Low Pulse Width
Clock:	u_SerDes_Top/q1_lane1_fabric_rx_clk
Objects:	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/gowin_add_SDPX9B_mem_data_mem_data_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			u_SerDes_Top/q1_lane1_fabric_rx_clk
5.000	0.000	tCL	FF	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.660	2.660	tNET	FF	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/gowin_add_SDPX9B_mem_data_mem_data_0_1_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000	0.000	tCL	RR	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
11.412	1.412	tNET	RR	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/gowin_add_SDPX9B_mem_data_mem_data_0_1_s/CLKA

MPW4

MPW Summary:

Slack:	2.893
Actual Width:	3.755
Required Width:	0.862
Type:	Low Pulse Width
Clock:	u_SerDes_Top/q1_lane1_fabric_rx_clk
Objects:	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/gowin_add_SDPX9B_mem_data_mem_data_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			u_SerDes_Top/q1_lane1_fabric_rx_clk
5.000	0.000	tCL	FF	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.653	2.653	tNET	FF	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/gowin_add_SDPX9B_mem_data_mem_data_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000	0.000	tCL	RR	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
11.408	1.408	tNET	RR	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/gowin_add_SDPX9B_mem_data_mem_data_0_0_s/CLKA

MPW5

MPW Summary:

Slack:	2.894
Actual Width:	3.756
Required Width:	0.862
Type:	High Pulse Width
Clock:	u_SerDes_Top/q1_lane1_fabric_rx_clk
Objects:	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.931	2.931	tNET	RR	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			u_SerDes_Top/q1_lane1_fabric_rx_clk
5.000	0.000	tCL	FF	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
6.687	1.687	tNET	FF	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_1_s/CLKA

MPW6

MPW Summary:

Slack:	2.897
Actual Width:	3.759
Required Width:	0.862
Type:	High Pulse Width
Clock:	u_SerDes_Top/q1_lane1_fabric_rx_clk
Objects:	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.923	2.923	tNET	RR	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			u_SerDes_Top/q1_lane1_fabric_rx_clk
5.000	0.000	tCL	FF	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
6.683	1.683	tNET	FF	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/mem_data_mem_data_0_0_s/CLKA

MPW7

MPW Summary:

Slack:	2.897
Actual Width:	3.759
Required Width:	0.862
Type:	High Pulse Width
Clock:	u_SerDes_Top/q1_lane1_fabric_rx_clk
Objects:	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/gowin_add_SDPX9B_mem_data_mem_data_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.923	2.923	tNET	RR	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/gowin_add_SDPX9B_mem_data_mem_data_0_1_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			u_SerDes_Top/q1_lane1_fabric_rx_clk
5.000	0.000	tCL	FF	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
6.683	1.683	tNET	FF	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/gowin_add_SDPX9B_mem_data_mem_data_0_1_s/CLKA

MPW8

MPW Summary:

Slack:	2.901
Actual Width:	3.763
Required Width:	0.862
Type:	High Pulse Width
Clock:	u_SerDes_Top/q1_lane1_fabric_rx_clk
Objects:	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/gowin_add_SDPX9B_mem_data_mem_data_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			u_SerDes_Top/q1_lane1_fabric_rx_clk
0.000	0.000	tCL	RR	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
2.916	2.916	tNET	RR	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/gowin_add_SDPX9B_mem_data_mem_data_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			u_SerDes_Top/q1_lane1_fabric_rx_clk
5.000	0.000	tCL	FF	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
6.679	1.679	tNET	FF	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/gowin_add_SDPX9B_mem_data_mem_data_0_0_s/CLKA

MPW9

MPW Summary:

Slack:	3.508
Actual Width:	3.708
Required Width:	0.200
Type:	Low Pulse Width
Clock:	u_SerDes_Top/q1_lane1_fabric_rx_clk
Objects:	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/serdes_rx_data_59_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			u_SerDes_Top/q1_lane1_fabric_rx_clk
5.000	0.000	tCL	FF	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.732	2.732	tNET	FF	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/serdes_rx_data_59_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000	0.000	tCL	RR	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
11.441	1.441	tNET	RR	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/serdes_rx_data_59_s0/CLK

MPW10

MPW Summary:

Slack:	3.508
Actual Width:	3.708
Required Width:	0.200
Type:	Low Pulse Width
Clock:	u_SerDes_Top/q1_lane1_fabric_rx_clk
Objects:	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/serdes_rx_data_12_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			u_SerDes_Top/q1_lane1_fabric_rx_clk
5.000	0.000	tCL	FF	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
7.732	2.732	tNET	FF	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/serdes_rx_data_12_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			u_SerDes_Top/q1_lane1_fabric_rx_clk
10.000	0.000	tCL	RR	u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK
11.441	1.441	tNET	RR	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/serdes_rx_data_12_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
4522	sys_clk	9.333	3.164
2032	cfg_clk	4.373	2.990
1773	u_SerDes_Top/q1_lane1_fabric_rx_clk	4.637	2.997
444	cfg_rst	4.373	4.554
196	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/rd_ptr[2]	14.943	3.094
194	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/tx_crc_gen_inst[0].tx_crc_gen/p_0_in__0	9.628	2.842
194	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/p_0_in__0	9.333	2.886
192	u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/rd_ptr[2]	14.803	3.070
186	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/tx_reset_comb	16.771	1.694
149	u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/rx_src_rdy_n_i	14.879	2.133

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R2C2	100.00%
R2C3	100.00%
R2C4	100.00%
R2C5	100.00%
R2C66	100.00%
R2C68	100.00%
R2C69	100.00%
R3C17	100.00%
R7C64	100.00%
R7C65	100.00%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name osc_clk_i -period 20 -waveform {0 10} [get_ports {osc_clk_i}]
TC_CLOCK	Actived	create_clock -name cfg_clk -period 20 -waveform {0 10} [get_nets {cfg_clk}]
TC_CLOCK	Actived	create_clock -name sys_clk -period 20.48 -waveform {0 10.24} [get_nets {sys_clk}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {cfg_clk}] -to [get_clocks {sys_clk}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {sys_clk}] -to [get_clocks {cfg_clk}]