Power Messages

Report Title	Power Analysis Report
Design File	F:\138k_serdes\20251230\Gowin_RoraLink_64B66B_RefDesign\project\impl\gwsynthesis\serial_64b66b.vg
Physical Constraints File	F:\138k_serdes\20251230\Gowin_RoraLink_64B66B_RefDesign\project\src\top.cst
Timing Constraints File	F:\138k_serdes\20251230\Gowin_RoraLink_64B66B_RefDesign\project\src\top.sdc
Tool Version	V1.9.12.01 (64-bit)
Part Number	GW5AST-LV138FPG676AC2/I1
Device	GW5AST-138
Device Version	B
Created Time	Tue Dec 30 15:37:04 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Configure Information:

Grade	Commercial
Process	Typical
Ambient Temperature	25.000
Use Custom Theta JA	false
Heat Sink	None
Air Flow	LFM_0
Use Custom Theta SA	false
Board Thermal Model	None
Use Custom Theta JB	false
Related Vcd File
Related Saif File
Filter Glitches	false
Default IO Toggle Rate	0.125
Default Remain Toggle Rate	0.125

Power Summary

Power Information:

Total Power (mW)	167.758
Quiescent Power (mW)	126.023
Dynamic Power (mW)	41.736

Thermal Information:

Junction Temperature	27.050
Theta JA	12.222
Max Allowed Ambient Temperature	82.950

Supply Information:

Voltage Source	Voltage	Dynamic Current(mA)	Quiescent Current(mA)	Power(mW)
VCC	0.900	45.577	100.025	131.042
VCCX	1.800	0.139	9.000	16.450
VCCIO33	3.300	0.141	3.818	13.066
VCCLDO	1.200	0.000	6.000	7.200

Power Details

Power By Block Type:

Block Type	Total Power(mW)	Static Power(mW)	Average Toggle Rate(millions of transitions/sec)
Logic	14.937	NA	14.319
IO	15.383	14.541	4.754
BSRAM	16.298	NA	NA
PLL	9.648	NA	NA

Power By Hierarchy:

Hierarchy Entity	Total Power(mW)	Block Dynamic Power(mW)
top	40.884	40.884(40.809)
top/u1_reset_gen/	0.017	0.017(0.000)
top/u2_reset_gen/	0.017	0.017(0.000)
top/u_Gowin_PLL/	9.648	9.648(0.000)
top/u_SerDes_Top/	30.219	30.219(30.219)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/	30.219	30.219(30.218)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/	30.218	30.218(30.144)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u0_reset_gen/	0.011	0.011(0.000)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u1_reset_gen/	0.011	0.011(0.000)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u2_reset_gen/	0.011	0.011(0.000)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u3_reset_gen/	0.011	0.011(0.000)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u4_reset_gen/	0.022	0.022(0.000)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/	12.418	12.418(12.416)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/gen_roralink_lane[0].u0_duplex_mode/	0.066	0.066(0.066)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/gen_roralink_lane[0].u0_duplex_mode/u0_duplex_init_sm/	0.005	0.005(0.000)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/gen_roralink_lane[0].u0_duplex_mode/u0_err_detect/	0.001	0.001(0.000)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/gen_roralink_lane[0].u0_duplex_mode/u0_sym_dec/	0.034	0.034(0.000)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/gen_roralink_lane[0].u0_duplex_mode/u0_sym_gen/	0.026	0.026(0.000)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_axi_to_ll_data/	0.001	0.001(0.000)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_axi_to_ll_ufc/	0.000	0.000(0.000)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_axi_to_ll_userk/	0.000	0.000(0.000)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_global_logic/	0.013	0.013(0.013)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_global_logic/u_duplex_ch_bond_code_gen/	0.002	0.002(0.000)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_global_logic/u_duplex_channel_err_detect/	0.000	0.000(0.000)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_global_logic/u_duplex_channel_init_sm/	0.010	0.010(0.000)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_rx_ll/	0.081	0.081(0.081)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_rx_ll/u_rx_ll_datapath/	0.061	0.061(0.000)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_rx_ll/u_rx_stream_ufc_datapath/	0.014	0.014(0.000)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_rx_ll/u_rx_stream_userk_datapath/	0.006	0.006(0.000)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_tx_ll/	0.062	0.062(0.062)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_tx_ll/u_duplex_tx_ll_control_sm/	0.024	0.024(0.000)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_duplex_tx_ll/u_duplex_tx_ll_datapath/	0.038	0.038(0.000)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_ll_to_axi_data/	0.002	0.002(0.000)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_ll_to_axi_ufc/	0.002	0.002(0.000)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_ll_to_axi_userk/	0.000	0.000(0.000)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/	6.385	6.385(6.289)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_rxcrc/rx_crc_gen_inst[0].rx_crc_gen/	6.289	6.289(0.000)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_standard_cc/	0.011	0.011(0.000)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/	5.793	5.793(5.722)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_mac_top/u_txcrc/tx_crc_gen_inst[0].tx_crc_gen/	5.722	5.722(0.000)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/	17.663	17.663(17.650)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/	16.591	16.591(16.468)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/master.master/	0.004	0.004(0.000)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/	16.464	16.464(16.298)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_ctc_cb/u_gen_async_fifo/u_async_data_buffer/	16.298	16.298(0.000)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_descrambler/	0.047	0.047(0.000)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_gearbox/	0.569	0.569(0.000)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_rx_headsync/	0.122	0.122(0.000)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_tx_gearbox/	0.269	0.269(0.000)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/gen_gearbox_and_block_sync[0].u_gtr12_tx_scrambler/	0.034	0.034(0.000)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_logic_cbcc/	0.001	0.001(0.000)
top/u_SerDes_Top/RoraLink_64B66B_Top_inst/u_RoraLink_64B66B_Core/u_RoraLink_64b66b_phy_top/u_gtr12_common_reset_cbcc/	0.017	0.017(0.000)
top/u_apb2local/	0.006	0.006(0.000)
top/u_data_axi_to_ll/	0.056	0.056(0.051)
top/u_data_axi_to_ll/u0_axi_register_slice/	0.026	0.026(0.000)
top/u_data_axi_to_ll/u1_axi_register_slice/	0.025	0.025(0.000)
top/u_data_ll_to_axi/	0.012	0.012(0.011)
top/u_data_ll_to_axi/u_axi_register_slice/	0.011	0.011(0.000)
top/u_frame_check/	0.216	0.216(0.000)
top/u_frame_gen/	0.035	0.035(0.000)
top/u_local2reg/	0.135	0.135(0.000)
top/u_uart_bus_top/	0.351	0.351(0.351)
top/u_uart_bus_top/uart_bus_core/	0.351	0.351(0.326)
top/u_uart_bus_top/uart_bus_core/u_uart_md/	0.326	0.326(0.326)
top/u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/	0.012	0.012(0.000)
top/u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/	0.154	0.154(0.154)
top/u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/	0.141	0.141(0.111)
top/u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/	0.111	0.111(0.000)
top/u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/	0.013	0.013(0.000)
top/u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/	0.160	0.160(0.160)
top/u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/	0.144	0.144(0.114)
top/u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/	0.114	0.114(0.000)
top/u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/	0.016	0.016(0.000)
top/u_ufc_axi_to_ll/	0.045	0.045(0.041)
top/u_ufc_axi_to_ll/u0_axi_register_slice/	0.026	0.026(0.000)
top/u_ufc_axi_to_ll/u1_axi_register_slice/	0.015	0.015(0.000)
top/u_ufc_ll_to_axi/	0.008	0.008(0.008)
top/u_ufc_ll_to_axi/u_axi_register_slice/	0.008	0.008(0.000)
top/u_userk_axi_to_ll/	0.035	0.035(0.035)
top/u_userk_axi_to_ll/u0_axi_register_slice/	0.023	0.023(0.000)
top/u_userk_axi_to_ll/u1_axi_register_slice/	0.012	0.012(0.000)
top/u_userk_ll_to_axi/	0.009	0.009(0.009)
top/u_userk_ll_to_axi/u_axi_register_slice/	0.009	0.009(0.000)

Power By Clock Domain:

Clock Domain	Clock Frequency(Mhz)	Total Dynamic Power(mW)
cfg_clk	50.000	0.550
u_SerDes_Top/q1_lane1_fabric_rx_clk	100.000	11.911
sys_clk	48.828	18.784
NO CLOCK DOMAIN	0.000	0.000
osc_clk_i	50.000	9.648