Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | F:\138k_serdes\20251230\Gowin_RoraLink_64B66B_RefDesign\project\src\apb2local.v F:\138k_serdes\20251230\Gowin_RoraLink_64B66B_RefDesign\project\src\axi_register_slice.v F:\138k_serdes\20251230\Gowin_RoraLink_64B66B_RefDesign\project\src\axi_to_ll_reg.v F:\138k_serdes\20251230\Gowin_RoraLink_64B66B_RefDesign\project\src\frame_check.v F:\138k_serdes\20251230\Gowin_RoraLink_64B66B_RefDesign\project\src\frame_gen.v F:\138k_serdes\20251230\Gowin_RoraLink_64B66B_RefDesign\project\src\gowin_pll\gowin_pll.v F:\138k_serdes\20251230\Gowin_RoraLink_64B66B_RefDesign\project\src\ll_to_axi_reg.v F:\138k_serdes\20251230\Gowin_RoraLink_64B66B_RefDesign\project\src\local2reg.v F:\138k_serdes\20251230\Gowin_RoraLink_64B66B_RefDesign\project\src\reset_gen.v F:\138k_serdes\20251230\Gowin_RoraLink_64B66B_RefDesign\project\src\serdes\roralink_64b66b\roralink_64b66b.v F:\138k_serdes\20251230\Gowin_RoraLink_64B66B_RefDesign\project\src\serdes\serdes.v F:\138k_serdes\20251230\Gowin_RoraLink_64B66B_RefDesign\project\src\top.v F:\138k_serdes\20251230\Gowin_RoraLink_64B66B_RefDesign\project\src\uart_to_bus\uart_to_bus.v |
| GowinSynthesis Constraints File | F:\138k_serdes\20251230\Gowin_RoraLink_64B66B_RefDesign\project\src\top.gsc |
| Tool Version | V1.9.12.01 (64-bit) |
| Part Number | GW5AST-LV138FPG676AC2/I1 |
| Device | GW5AST-138 |
| Device Version | B |
| Created Time | Tue Dec 30 15:36:24 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | top |
| Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 2001.227MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.734s, Elapsed time = 0h 0m 0.732s, Peak memory usage = 2001.227MB Optimizing Phase 1: CPU time = 0h 0m 0.468s, Elapsed time = 0h 0m 0.459s, Peak memory usage = 2001.227MB Optimizing Phase 2: CPU time = 0h 0m 0.671s, Elapsed time = 0h 0m 0.674s, Peak memory usage = 2001.227MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.405s, Peak memory usage = 2001.227MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 2001.227MB Inferring Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.076s, Peak memory usage = 2001.227MB Inferring Phase 3: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.045s, Peak memory usage = 2001.227MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.562s, Elapsed time = 0h 0m 0.551s, Peak memory usage = 2001.227MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.151s, Peak memory usage = 2001.227MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.062s, Peak memory usage = 2001.227MB Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 2001.227MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.546s, Elapsed time = 0h 0m 0.581s, Peak memory usage = 2001.227MB Generate output files: CPU time = 0h 0m 0.515s, Elapsed time = 0h 0m 0.551s, Peak memory usage = 2001.227MB |
| Total Time and Memory Usage | CPU time = 0h 0m 8s, Elapsed time = 0h 0m 8s, Peak memory usage = 2001.227MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 18 |
| I/O Buf | 17 |
| IBUF | 3 |
| OBUF | 11 |
| TBUF | 3 |
| Register | 8317 |
| DFFSE | 425 |
| DFFRE | 6355 |
| DFFPE | 18 |
| DFFCE | 1519 |
| LUT | 7275 |
| LUT1 | 64 |
| LUT2 | 565 |
| LUT3 | 2926 |
| LUT4 | 3100 |
| LUT5 | 172 |
| LUT6 | 448 |
| ALU | 538 |
| ALU | 538 |
| INV | 83 |
| INV | 83 |
| BSRAM | 2 |
| SDPX9B | 2 |
| CLOCK | 1 |
| PLL | 1 |
| GTR12_QUAD | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 9412(8874 LUT, 538 ALU) / 138240 | 7% |
| Register | 8317 / 139140 | 6% |
| --Register as Latch | 0 / 139140 | 0% |
| --Register as FF | 8317 / 139140 | 6% |
| BSRAM | 2 / 340 | <1% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | osc_clk_i | Base | 20.000 | 50.000 | 0.000 | 10.000 | osc_clk_i_ibuf/I | ||
| 2 | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk | Generated | 20.000 | 50.000 | 0.000 | 10.000 | osc_clk_i_ibuf/I | osc_clk_i | u_Gowin_PLL/PLL_inst/CLKOUT0 |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk | 50.000(MHz) | 132.031(MHz) | 10 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 12.426 |
| Data Arrival Time | 8.112 |
| Data Required Time | 20.538 |
| From | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0 |
| To | u_local2reg/local_rdat_o_5_s0 |
| Launch Clk | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk | |||
| 0.259 | 0.259 | tCL | RR | 2032 | u_Gowin_PLL/PLL_inst/CLKOUT0 |
| 0.589 | 0.330 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0/CLK |
| 0.895 | 0.306 | tC2Q | RR | 3 | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0/Q |
| 1.225 | 0.330 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s2/I0 |
| 1.688 | 0.463 | tINS | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s2/F |
| 2.018 | 0.330 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s0/I0 |
| 2.481 | 0.463 | tINS | RR | 76 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s0/F |
| 2.811 | 0.330 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_addr_o_d_7_s0/I1 |
| 3.265 | 0.454 | tINS | RR | 2 | u_uart_bus_top/uart_bus_core/apb0_addr_o_d_7_s0/F |
| 3.595 | 0.330 | tNET | RR | 1 | u_local2reg/n1765_s51/I0 |
| 4.058 | 0.463 | tINS | RR | 2 | u_local2reg/n1765_s51/F |
| 4.388 | 0.330 | tNET | RR | 1 | u_local2reg/n1765_s49/I3 |
| 4.619 | 0.231 | tINS | RR | 30 | u_local2reg/n1765_s49/F |
| 4.949 | 0.330 | tNET | RR | 1 | u_local2reg/n1771_s47/I1 |
| 5.403 | 0.454 | tINS | RR | 32 | u_local2reg/n1771_s47/F |
| 5.733 | 0.330 | tNET | RR | 1 | u_local2reg/n1791_s39/I0 |
| 6.196 | 0.463 | tINS | RR | 1 | u_local2reg/n1791_s39/F |
| 6.526 | 0.330 | tNET | RR | 1 | u_local2reg/n1791_s36/I0 |
| 6.989 | 0.463 | tINS | RR | 1 | u_local2reg/n1791_s36/F |
| 7.319 | 0.330 | tNET | RR | 1 | u_local2reg/n1791_s35/I0 |
| 7.782 | 0.463 | tINS | RR | 1 | u_local2reg/n1791_s35/F |
| 8.112 | 0.330 | tNET | RR | 1 | u_local2reg/local_rdat_o_5_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk | |||
| 20.259 | 0.259 | tCL | RR | 2032 | u_Gowin_PLL/PLL_inst/CLKOUT0 |
| 20.589 | 0.330 | tNET | RR | 1 | u_local2reg/local_rdat_o_5_s0/CLK |
| 20.538 | -0.051 | tSu | 1 | u_local2reg/local_rdat_o_5_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 10 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.330, 100.000% |
| Arrival Data Path Delay: | cell: 3.917, 52.067%; route: 3.300, 43.865%; tC2Q: 0.306, 4.068% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.330, 100.000% |
Path 2
Path Summary:| Slack | 12.426 |
| Data Arrival Time | 8.112 |
| Data Required Time | 20.538 |
| From | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0 |
| To | u_local2reg/local_rdat_o_7_s0 |
| Launch Clk | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk | |||
| 0.259 | 0.259 | tCL | RR | 2032 | u_Gowin_PLL/PLL_inst/CLKOUT0 |
| 0.589 | 0.330 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0/CLK |
| 0.895 | 0.306 | tC2Q | RR | 3 | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0/Q |
| 1.225 | 0.330 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s2/I0 |
| 1.688 | 0.463 | tINS | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s2/F |
| 2.018 | 0.330 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s0/I0 |
| 2.481 | 0.463 | tINS | RR | 76 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s0/F |
| 2.811 | 0.330 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_addr_o_d_7_s0/I1 |
| 3.265 | 0.454 | tINS | RR | 2 | u_uart_bus_top/uart_bus_core/apb0_addr_o_d_7_s0/F |
| 3.595 | 0.330 | tNET | RR | 1 | u_local2reg/n1765_s51/I0 |
| 4.058 | 0.463 | tINS | RR | 2 | u_local2reg/n1765_s51/F |
| 4.388 | 0.330 | tNET | RR | 1 | u_local2reg/n1765_s49/I3 |
| 4.619 | 0.231 | tINS | RR | 30 | u_local2reg/n1765_s49/F |
| 4.949 | 0.330 | tNET | RR | 1 | u_local2reg/n1771_s47/I1 |
| 5.403 | 0.454 | tINS | RR | 32 | u_local2reg/n1771_s47/F |
| 5.733 | 0.330 | tNET | RR | 1 | u_local2reg/n1789_s39/I0 |
| 6.196 | 0.463 | tINS | RR | 1 | u_local2reg/n1789_s39/F |
| 6.526 | 0.330 | tNET | RR | 1 | u_local2reg/n1789_s36/I0 |
| 6.989 | 0.463 | tINS | RR | 1 | u_local2reg/n1789_s36/F |
| 7.319 | 0.330 | tNET | RR | 1 | u_local2reg/n1789_s35/I0 |
| 7.782 | 0.463 | tINS | RR | 1 | u_local2reg/n1789_s35/F |
| 8.112 | 0.330 | tNET | RR | 1 | u_local2reg/local_rdat_o_7_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk | |||
| 20.259 | 0.259 | tCL | RR | 2032 | u_Gowin_PLL/PLL_inst/CLKOUT0 |
| 20.589 | 0.330 | tNET | RR | 1 | u_local2reg/local_rdat_o_7_s0/CLK |
| 20.538 | -0.051 | tSu | 1 | u_local2reg/local_rdat_o_7_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 10 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.330, 100.000% |
| Arrival Data Path Delay: | cell: 3.917, 52.067%; route: 3.300, 43.865%; tC2Q: 0.306, 4.068% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.330, 100.000% |
Path 3
Path Summary:| Slack | 12.426 |
| Data Arrival Time | 8.112 |
| Data Required Time | 20.538 |
| From | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0 |
| To | u_local2reg/local_rdat_o_9_s0 |
| Launch Clk | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk | |||
| 0.259 | 0.259 | tCL | RR | 2032 | u_Gowin_PLL/PLL_inst/CLKOUT0 |
| 0.589 | 0.330 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0/CLK |
| 0.895 | 0.306 | tC2Q | RR | 3 | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0/Q |
| 1.225 | 0.330 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s2/I0 |
| 1.688 | 0.463 | tINS | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s2/F |
| 2.018 | 0.330 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s0/I0 |
| 2.481 | 0.463 | tINS | RR | 76 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s0/F |
| 2.811 | 0.330 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_addr_o_d_7_s0/I1 |
| 3.265 | 0.454 | tINS | RR | 2 | u_uart_bus_top/uart_bus_core/apb0_addr_o_d_7_s0/F |
| 3.595 | 0.330 | tNET | RR | 1 | u_local2reg/n1765_s51/I0 |
| 4.058 | 0.463 | tINS | RR | 2 | u_local2reg/n1765_s51/F |
| 4.388 | 0.330 | tNET | RR | 1 | u_local2reg/n1765_s49/I3 |
| 4.619 | 0.231 | tINS | RR | 30 | u_local2reg/n1765_s49/F |
| 4.949 | 0.330 | tNET | RR | 1 | u_local2reg/n1767_s47/I1 |
| 5.403 | 0.454 | tINS | RR | 30 | u_local2reg/n1767_s47/F |
| 5.733 | 0.330 | tNET | RR | 1 | u_local2reg/n1787_s39/I0 |
| 6.196 | 0.463 | tINS | RR | 1 | u_local2reg/n1787_s39/F |
| 6.526 | 0.330 | tNET | RR | 1 | u_local2reg/n1787_s36/I0 |
| 6.989 | 0.463 | tINS | RR | 1 | u_local2reg/n1787_s36/F |
| 7.319 | 0.330 | tNET | RR | 1 | u_local2reg/n1787_s35/I0 |
| 7.782 | 0.463 | tINS | RR | 1 | u_local2reg/n1787_s35/F |
| 8.112 | 0.330 | tNET | RR | 1 | u_local2reg/local_rdat_o_9_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk | |||
| 20.259 | 0.259 | tCL | RR | 2032 | u_Gowin_PLL/PLL_inst/CLKOUT0 |
| 20.589 | 0.330 | tNET | RR | 1 | u_local2reg/local_rdat_o_9_s0/CLK |
| 20.538 | -0.051 | tSu | 1 | u_local2reg/local_rdat_o_9_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 10 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.330, 100.000% |
| Arrival Data Path Delay: | cell: 3.917, 52.067%; route: 3.300, 43.865%; tC2Q: 0.306, 4.068% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.330, 100.000% |
Path 4
Path Summary:| Slack | 12.426 |
| Data Arrival Time | 8.112 |
| Data Required Time | 20.538 |
| From | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0 |
| To | u_local2reg/local_rdat_o_10_s0 |
| Launch Clk | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk | |||
| 0.259 | 0.259 | tCL | RR | 2032 | u_Gowin_PLL/PLL_inst/CLKOUT0 |
| 0.589 | 0.330 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0/CLK |
| 0.895 | 0.306 | tC2Q | RR | 3 | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0/Q |
| 1.225 | 0.330 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s2/I0 |
| 1.688 | 0.463 | tINS | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s2/F |
| 2.018 | 0.330 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s0/I0 |
| 2.481 | 0.463 | tINS | RR | 76 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s0/F |
| 2.811 | 0.330 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_addr_o_d_7_s0/I1 |
| 3.265 | 0.454 | tINS | RR | 2 | u_uart_bus_top/uart_bus_core/apb0_addr_o_d_7_s0/F |
| 3.595 | 0.330 | tNET | RR | 1 | u_local2reg/n1765_s51/I0 |
| 4.058 | 0.463 | tINS | RR | 2 | u_local2reg/n1765_s51/F |
| 4.388 | 0.330 | tNET | RR | 1 | u_local2reg/n1765_s49/I3 |
| 4.619 | 0.231 | tINS | RR | 30 | u_local2reg/n1765_s49/F |
| 4.949 | 0.330 | tNET | RR | 1 | u_local2reg/n1766_s48/I1 |
| 5.403 | 0.454 | tINS | RR | 31 | u_local2reg/n1766_s48/F |
| 5.733 | 0.330 | tNET | RR | 1 | u_local2reg/n1786_s39/I0 |
| 6.196 | 0.463 | tINS | RR | 1 | u_local2reg/n1786_s39/F |
| 6.526 | 0.330 | tNET | RR | 1 | u_local2reg/n1786_s36/I0 |
| 6.989 | 0.463 | tINS | RR | 1 | u_local2reg/n1786_s36/F |
| 7.319 | 0.330 | tNET | RR | 1 | u_local2reg/n1786_s35/I0 |
| 7.782 | 0.463 | tINS | RR | 1 | u_local2reg/n1786_s35/F |
| 8.112 | 0.330 | tNET | RR | 1 | u_local2reg/local_rdat_o_10_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk | |||
| 20.259 | 0.259 | tCL | RR | 2032 | u_Gowin_PLL/PLL_inst/CLKOUT0 |
| 20.589 | 0.330 | tNET | RR | 1 | u_local2reg/local_rdat_o_10_s0/CLK |
| 20.538 | -0.051 | tSu | 1 | u_local2reg/local_rdat_o_10_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 10 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.330, 100.000% |
| Arrival Data Path Delay: | cell: 3.917, 52.067%; route: 3.300, 43.865%; tC2Q: 0.306, 4.068% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.330, 100.000% |
Path 5
Path Summary:| Slack | 12.426 |
| Data Arrival Time | 8.112 |
| Data Required Time | 20.538 |
| From | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0 |
| To | u_local2reg/local_rdat_o_12_s0 |
| Launch Clk | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk | |||
| 0.259 | 0.259 | tCL | RR | 2032 | u_Gowin_PLL/PLL_inst/CLKOUT0 |
| 0.589 | 0.330 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0/CLK |
| 0.895 | 0.306 | tC2Q | RR | 3 | u_uart_bus_top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/cpu_addr_0_s0/Q |
| 1.225 | 0.330 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s2/I0 |
| 1.688 | 0.463 | tINS | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s2/F |
| 2.018 | 0.330 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s0/I0 |
| 2.481 | 0.463 | tINS | RR | 76 | u_uart_bus_top/uart_bus_core/apb0_sel_o_d_s0/F |
| 2.811 | 0.330 | tNET | RR | 1 | u_uart_bus_top/uart_bus_core/apb0_addr_o_d_7_s0/I1 |
| 3.265 | 0.454 | tINS | RR | 2 | u_uart_bus_top/uart_bus_core/apb0_addr_o_d_7_s0/F |
| 3.595 | 0.330 | tNET | RR | 1 | u_local2reg/n1765_s51/I0 |
| 4.058 | 0.463 | tINS | RR | 2 | u_local2reg/n1765_s51/F |
| 4.388 | 0.330 | tNET | RR | 1 | u_local2reg/n1765_s49/I3 |
| 4.619 | 0.231 | tINS | RR | 30 | u_local2reg/n1765_s49/F |
| 4.949 | 0.330 | tNET | RR | 1 | u_local2reg/n1769_s48/I1 |
| 5.403 | 0.454 | tINS | RR | 32 | u_local2reg/n1769_s48/F |
| 5.733 | 0.330 | tNET | RR | 1 | u_local2reg/n1784_s39/I0 |
| 6.196 | 0.463 | tINS | RR | 1 | u_local2reg/n1784_s39/F |
| 6.526 | 0.330 | tNET | RR | 1 | u_local2reg/n1784_s36/I0 |
| 6.989 | 0.463 | tINS | RR | 1 | u_local2reg/n1784_s36/F |
| 7.319 | 0.330 | tNET | RR | 1 | u_local2reg/n1784_s35/I0 |
| 7.782 | 0.463 | tINS | RR | 1 | u_local2reg/n1784_s35/F |
| 8.112 | 0.330 | tNET | RR | 1 | u_local2reg/local_rdat_o_12_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | u_Gowin_PLL/PLL_inst/CLKOUT0.default_gen_clk | |||
| 20.259 | 0.259 | tCL | RR | 2032 | u_Gowin_PLL/PLL_inst/CLKOUT0 |
| 20.589 | 0.330 | tNET | RR | 1 | u_local2reg/local_rdat_o_12_s0/CLK |
| 20.538 | -0.051 | tSu | 1 | u_local2reg/local_rdat_o_12_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 10 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.330, 100.000% |
| Arrival Data Path Delay: | cell: 3.917, 52.067%; route: 3.300, 43.865%; tC2Q: 0.306, 4.068% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.330, 100.000% |