﻿______________________________________________________________________
         GOWIN RoraLink 64B66B IP参考设计阅读指南
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目标器件：GW5AST-LV138FPG676AC2/I1
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文件列表
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.
|-- doc
|   `-- readme.txt                          -->  自述文件
|-- tb 
|   `-- tb_top.v                            -->  GOWIN RoraLink 64B66B IP 仿真TestBench文件
|   |-- simlib
|       |-- gw5a
|           `-- prim_sim.v                  -->  GOWIN GW5A系列FPGA仿真库文件
|-- simulation                              -->  Simulation File
|   |-- modelsim_sim                        -->  Simulation File
|       `-- path.f                          -->  GOWIN RoraLink 64B66B IP 仿真Filelist
|       `-- readme.txt                      -->  GOWIN RoraLink 64B66B IP Modelsim仿真自述文件
|       `-- sim.bat                         -->  GOWIN RoraLink 64B66B IP windows bat执行文件
|       `-- sim.do                          -->  GOWIN RoraLink 64B66B IP Modelsim .do文件
|       `-- sim_tcl.tcl                     -->  GOWIN RoraLink 64B66B IP Modelsim .tcl文件
|   |-- vcs_sim                             -->  Simulation File
|       `-- readme.txt                      -->  GOWIN RoraLink 64B66B IP Modelsim仿真自述文件
|       `-- makefile                        -->  GOWIN RoraLink 64B66B IP VCS仿真Makefile文件
|-- project
|   `-- top.gprj              	            -->  参考设计工程文件
|   `-- top.gprj.user                       -->  参考设计工程文件
|   |-- impl                                -->  参考设计工程编译生成文件
|   |-- src                                 -->  参考设计源码
|       `-- top.v                           -->  参考设计工程顶层文件
|       `-- top.cst                         -->  参考设计工程管脚约束文件
|       `-- top.gsc                         -->  参考设计工程综合约束文件
|       `-- top.sdc                         -->  参考设计工程时序约束文件
|       `-- top.gao                         -->  参考设计工程在线调试文件
|       `-- reset_gen.v                     -->  参考设计源码
|       `-- local2reg.v                     -->  参考设计源码
|       `-- ll_to_axi_reg.v                 -->  参考设计源码
|       `-- frame_gen.v                     -->  参考设计源码
|       `-- frame_check.v                   -->  参考设计源码
|       `-- axi_to_ll_reg.v                 -->  参考设计源码
|       `-- axi_register_slice.v            -->  参考设计源码
|       `-- apb2local.v                     -->  参考设计源码
|       |-- serdes         
|           `-- serdes.ipc                  -->  GOWIN SerDes IP 文件
|           `-- serdes.csr                  -->  GOWIN SerDes IP 文件
|           `-- serdes.mod                  -->  GOWIN SerDes IP 文件
|           `-- serdes.v                    -->  GOWIN SerDes IP 文件
|           `-- serdes_temp.v               -->  GOWIN SerDes IP 文件
|           |-- roralink_64b66b         
|           |   `-- roralink_64b66b.v       -->  GOWIN RoraLink 64B66B IP 文件(Encrypted)
|           |   `-- roralink_64b66b.vo      -->  GOWIN RoraLink 64B66B IP 文件
|           |   `-- roralink_64b66b_tmp.v   -->  GOWIN RoraLink 64B66B IP 文件
|           |   |-- temp                                                  
|       |-- uart_to_bus         
|       |   `-- uart_to_bus.ipc             -->  GOWIN Uart to Bus IP 文件                          
|       |   `-- uart_to_bus.vo              -->  GOWIN Uart to Bus IP 文件                          
|       |   `-- uart_to_bus.v               -->  GOWIN Uart to Bus IP 文件                          
|       |   `-- uart_to_bus_tmp.v           -->  GOWIN Uart to Bus IP 文件  
|       |   |-- temp                                                 
|       |-- gowin_pll         
|       |   `-- gowin_pll.ipc               -->  GOWIN PLL IP 文件                          
|       |   `-- gowin_pll.vo                -->  GOWIN PLL IP 文件                          
|       |   `-- gowin_pll.v                 -->  GOWIN PLL IP 文件                          
|       |   `-- gowin_pll_tmp.v             -->  GOWIN PLL IP 文件                                                  
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如何在云源软件里打开工程：
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1. 解压已压缩的设计文件。
2. 启动云源软件并选择“File -> Open”。
3. 在已打开的“Open File”窗口中进入对应工程所在路径，选择工程文件“top.gprj”。
4. 点击“打开”，则工程即可加载。 

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如何在云源软件中运行综合，布局布线及时序分析：
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1. 点击云源软件界面中Process面板中的Process选项卡，双击Synthsize(GowinSynthesis)，这将使设计运行综合。
2. 点击”Project -> Configuration -> Place & Route”以设置生成Post-place文件及SDF文件等。
3. 点击云源软件界面中Process面板中的Process选项卡，双击Place & Route，这将使设计运行映射及布局布线。
4. 当布局布线完成时，用户可以双击Timing Analysis Report得到时序分析结果。

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如何运行工程仿真：
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方法一：
1. 在windows系统下，用鼠标双击./simulation/sim.bat,执行文件。
2. 脚本自动打开modelsim并进行仿真。
3. 在Modelsim软件中查看仿真波形。

方法二：
1. 启动Modelsim并点击change directory至路径“../simulation”。 
2. 在transcript window中执行脚本文件（sim.do）。
3. 在Modelsim软件中查看仿真波形。


________________________________________________________________________
	  GOWIN RoraLink 64B66B IP Design Example Readme
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Object device: GW5AST-LV138FPG676AC2/I1
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File List:
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.
|-- doc
|   `-- readme.txt                          -->  Read Me file (this file)
|-- tb 
|   `-- tb_top.v                            -->  TestBench for GOWIN RoraLink 64B66B Ref design
|   |-- simlib
|       |-- gw5a
|           `-- prim_sim.v                  -->  GOWIN GW5A FPGA simulation library file
|-- simulation                              -->  Simulation File
|   |-- modelsim_sim                        -->  Simulation File
|       `-- path.f                          -->  Filelist for modelsim simulation
|       `-- readme.txt                      -->  Read Me file for modelsim simulation
|       `-- sim.bat                         -->  Windows bat for modelsim simulation
|       `-- sim.do                          -->  File for Simulation run command
|       `-- sim_tcl.tcl                     -->  Tcl for Simulation run command
|   |-- vcs_sim                             -->  Simulation File
|       `-- readme.txt                      -->  Read Me file for modelsim simulation
|       `-- makefile                        -->  File for Simulation run command
|-- project
|   `-- top.gprj              	            -->  Design Example Project File
|   `-- top.gprj.user                       -->  Design Example Project File
|   |-- impl                                -->  Design Example Project File
|   |-- src                                 -->  Design Example Project File
|       `-- top.v                           -->  Design Example Project File
|       `-- top.cst                         -->  Design Example Project File
|       `-- top.gsc                         -->  Design Example Project File
|       `-- top.sdc                         -->  Design Example Project File
|       `-- top.gao                         -->  Design Example Project File
|       |-- serdes         
|           `-- serdes.v                    -->  File for Gowin Project
|           `-- serdes.ipc                  -->  File for Gowin Project
|           `-- serdes.csr                  -->  File for Gowin Project
|           `-- serdes.mod                  -->  File for Gowin Project
|           `-- serdes_temp.v               -->  File for Gowin Project
|           |-- roralink_64b66b         
|           |   `-- roralink_64b66b.v       -->  File for Gowin Project(Encrypted)
|           |   `-- roralink_64b66b.vo      -->  File for Gowin Project
|           |   `-- roralink_64b66b_tmp.v   -->  File for Gowin Project
|           |   |-- temp                                                    
|       |-- uart_to_bus         
|       |   `-- uart_to_bus.ipc             -->  File for Gowin Project                         
|       |   `-- uart_to_bus.vo              -->  File for Gowin Project                          
|       |   `-- uart_to_bus.v               -->  File for Gowin Project                          
|       |   `-- uart_to_bus_tmp.v           -->  File for Gowin Project 
|       |   |-- temp                                                 
|       |-- gowin_pll                       
|       |   `-- gowin_pll.ipc               -->  File for Gowin Project                          
|       |   `-- gowin_pll.vo                -->  File for Gowin Project                          
|       |   `-- gowin_pll.v                 -->  File for Gowin Project                         
|       |   `-- gowin_pll_tmp.v             -->  File for Gowin Project                                                 
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HOW TO OPEN A PROJECT IN GOWIN EDA:
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1. Unzip the compressed design files.
2. Start the GOWIN EDA and select "File -> Open"
3. In the Open File dialog, enter the Project location, select the project "top.gprj".
4. Click "Open". Then the project could be loaded. 

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HOW TO RUN SYNTHESIZE, PLACE&ROUTE AND TIMING ANALYSIS IN GOWIN EDA:
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1. Click the Process tab in the process panel of the GOWIN EDA dashboard. 
   Double click on Synthsize(GowinSynthesis). This will bring the design through synthesis.
2. Click on "Project -> Configuration -> Place & Route" to configurate the generation of the Post-Place File 
   and SDF File,etc.
3. Click the Process tab in the process panel of the GOWIN EDA dashboard. 
   Double click on Place & Route. This will bring the design through mapping, place and route.
4. Once Place & Route is done, user can double click on Timing Analysis Report to get 
   the timing analysis result.

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HOW TO RUN SIMULATION
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Method 1:
1. Run the script(./simulation/sim.bat) in the windows.
2. Check waveform by software Modelsim.

Method 2:
1. Start the Modelsim and change directory to "../simulation". 
2. Run the script(sim.do) in the transcript window.
3. Check waveform by software Modelsim.