Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\TENGETHERNETMAC\data\xgmac_wrapper.v
D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\TENGETHERNETMAC\data\xgmac.v
GowinSynthesis Constraints File ---
Tool Version V1.9.12.02 (64-bit)
Part Number GW5AST-LV138FPG676AC2/I1
Device GW5AST-138
Device Version B
Created Time Wed Mar 4 10:26:31 2026
Legal Announcement Copyright (C)2014-2026 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Ten_Giga_Ethernet_MAC_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.64s, Elapsed time = 0h 0m 0.769s, Peak memory usage = 102.824MB
Running netlist conversion:
    CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.1s, Peak memory usage = 102.824MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.64s, Elapsed time = 0h 0m 0.642s, Peak memory usage = 102.824MB
    Optimizing Phase 1: CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.33s, Peak memory usage = 102.824MB
    Optimizing Phase 2: CPU time = 0h 0m 0.703s, Elapsed time = 0h 0m 0.709s, Peak memory usage = 102.824MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.286s, Peak memory usage = 102.824MB
    Inferring Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.083s, Peak memory usage = 102.824MB
    Inferring Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.083s, Peak memory usage = 102.824MB
    Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.03s, Peak memory usage = 102.824MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.484s, Elapsed time = 0h 0m 0.472s, Peak memory usage = 102.824MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.187s, Peak memory usage = 102.824MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.124s, Peak memory usage = 102.824MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 18s, Elapsed time = 0h 0m 18s, Peak memory usage = 130.793MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.459s, Peak memory usage = 130.793MB
Generate output files:
    CPU time = 0h 0m 0.437s, Elapsed time = 0h 0m 0.448s, Peak memory usage = 132.074MB
Total Time and Memory Usage CPU time = 0h 0m 22s, Elapsed time = 0h 0m 22s, Peak memory usage = 132.074MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 355
I/O Buf 355
    IBUF 162
    OBUF 193
Register 3630
    DFFPE 66
    DFFCE 3564
LUT 3004
    LUT2 547
    LUT3 805
    LUT4 1652
ALU 4
    ALU 4
INV 3
    INV 3

Resource Utilization Summary

Resource Usage Utilization
Logic 3011(3007 LUT, 4 ALU) / 138240 3%
Register 3630 / 139140 3%
  --Register as Latch 0 / 139140 0%
  --Register as FF 3630 / 139140 3%
BSRAM 0 / 340 0%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 xgtx_clk_i Base 10.000 100.000 0.000 5.000 xgtx_clk_i_ibuf/I
2 xgmii_rx_clk_i Base 10.000 100.000 0.000 5.000 xgmii_rx_clk_i_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 xgtx_clk_i 100.000(MHz) 204.399(MHz) 7 TOP
2 xgmii_rx_clk_i 100.000(MHz) 239.309(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 5.108
Data Arrival Time 5.143
Data Required Time 10.251
From xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_flag_5_s0
To xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/frame_lgt_5_s0
Launch Clk xgtx_clk_i[R]
Latch Clk xgtx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 xgtx_clk_i
0.000 0.000 tCL RR 1 xgtx_clk_i_ibuf/I
0.000 0.000 tINS RR 1334 xgtx_clk_i_ibuf/O
0.297 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_flag_5_s0/CLK
0.572 0.275 tC2Q RR 12 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_flag_5_s0/Q
0.869 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/tx_error_propagation_s5/I0
1.286 0.417 tINS RR 2 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/tx_error_propagation_s5/F
1.583 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n157_s4/I0
2.000 0.417 tINS RR 2 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n157_s4/F
2.297 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n156_s3/I0
2.713 0.417 tINS RR 6 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n156_s3/F
3.010 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n154_s7/I1
3.419 0.409 tINS RR 3 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n154_s7/F
3.716 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n153_s3/I0
4.133 0.417 tINS RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n153_s3/F
4.430 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n153_s2/I0
4.846 0.417 tINS RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n153_s2/F
5.143 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/frame_lgt_5_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 xgtx_clk_i
10.000 0.000 tCL RR 1 xgtx_clk_i_ibuf/I
10.000 0.000 tINS RR 1334 xgtx_clk_i_ibuf/O
10.297 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/frame_lgt_5_s0/CLK
10.251 -0.046 tSu 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/frame_lgt_5_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.297, 100.000%
Arrival Data Path Delay: cell: 2.492, 51.421%; route: 2.079, 42.897%; tC2Q: 0.275, 5.682%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.297, 100.000%

Path 2

Path Summary:
Slack 5.108
Data Arrival Time 5.143
Data Required Time 10.251
From xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_flag_5_s0
To xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/frame_lgt_9_s0
Launch Clk xgtx_clk_i[R]
Latch Clk xgtx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 xgtx_clk_i
0.000 0.000 tCL RR 1 xgtx_clk_i_ibuf/I
0.000 0.000 tINS RR 1334 xgtx_clk_i_ibuf/O
0.297 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_flag_5_s0/CLK
0.572 0.275 tC2Q RR 12 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_flag_5_s0/Q
0.869 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/tx_error_propagation_s5/I0
1.286 0.417 tINS RR 2 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/tx_error_propagation_s5/F
1.583 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n157_s4/I0
2.000 0.417 tINS RR 2 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n157_s4/F
2.297 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n156_s3/I0
2.713 0.417 tINS RR 6 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n156_s3/F
3.010 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n155_s4/I0
3.427 0.417 tINS RR 4 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n155_s4/F
3.724 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n149_s3/I0
4.141 0.417 tINS RR 2 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n149_s3/F
4.438 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n149_s2/I1
4.846 0.409 tINS RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n149_s2/F
5.143 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/frame_lgt_9_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 xgtx_clk_i
10.000 0.000 tCL RR 1 xgtx_clk_i_ibuf/I
10.000 0.000 tINS RR 1334 xgtx_clk_i_ibuf/O
10.297 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/frame_lgt_9_s0/CLK
10.251 -0.046 tSu 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/frame_lgt_9_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.297, 100.000%
Arrival Data Path Delay: cell: 2.492, 51.421%; route: 2.079, 42.897%; tC2Q: 0.275, 5.682%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.297, 100.000%

Path 3

Path Summary:
Slack 5.151
Data Arrival Time 5.100
Data Required Time 10.251
From xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_flag_5_s0
To xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/frame_lgt_8_s0
Launch Clk xgtx_clk_i[R]
Latch Clk xgtx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 xgtx_clk_i
0.000 0.000 tCL RR 1 xgtx_clk_i_ibuf/I
0.000 0.000 tINS RR 1334 xgtx_clk_i_ibuf/O
0.297 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_flag_5_s0/CLK
0.572 0.275 tC2Q RR 12 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_flag_5_s0/Q
0.869 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/tx_error_propagation_s5/I0
1.286 0.417 tINS RR 2 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/tx_error_propagation_s5/F
1.583 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n157_s4/I0
2.000 0.417 tINS RR 2 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n157_s4/F
2.297 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n156_s3/I0
2.713 0.417 tINS RR 6 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n156_s3/F
3.010 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n155_s4/I0
3.427 0.417 tINS RR 4 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n155_s4/F
3.724 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n149_s3/I0
4.141 0.417 tINS RR 2 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n149_s3/F
4.438 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n150_s2/I2
4.803 0.365 tINS RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n150_s2/F
5.100 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/frame_lgt_8_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 xgtx_clk_i
10.000 0.000 tCL RR 1 xgtx_clk_i_ibuf/I
10.000 0.000 tINS RR 1334 xgtx_clk_i_ibuf/O
10.297 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/frame_lgt_8_s0/CLK
10.251 -0.046 tSu 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/frame_lgt_8_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.297, 100.000%
Arrival Data Path Delay: cell: 2.449, 50.983%; route: 2.079, 43.283%; tC2Q: 0.275, 5.734%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.297, 100.000%

Path 4

Path Summary:
Slack 5.159
Data Arrival Time 5.092
Data Required Time 10.251
From xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_flag_5_s0
To xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/frame_lgt_7_s0
Launch Clk xgtx_clk_i[R]
Latch Clk xgtx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 xgtx_clk_i
0.000 0.000 tCL RR 1 xgtx_clk_i_ibuf/I
0.000 0.000 tINS RR 1334 xgtx_clk_i_ibuf/O
0.297 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_flag_5_s0/CLK
0.572 0.275 tC2Q RR 12 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_flag_5_s0/Q
0.869 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/tx_error_propagation_s5/I0
1.286 0.417 tINS RR 2 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/tx_error_propagation_s5/F
1.583 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n157_s4/I0
2.000 0.417 tINS RR 2 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n157_s4/F
2.297 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n156_s3/I0
2.713 0.417 tINS RR 6 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n156_s3/F
3.010 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n155_s4/I0
3.427 0.417 tINS RR 4 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n155_s4/F
3.724 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n151_s3/I2
4.090 0.365 tINS RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n151_s3/F
4.387 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n151_s2/I1
4.795 0.409 tINS RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n151_s2/F
5.092 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/frame_lgt_7_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 xgtx_clk_i
10.000 0.000 tCL RR 1 xgtx_clk_i_ibuf/I
10.000 0.000 tINS RR 1334 xgtx_clk_i_ibuf/O
10.297 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/frame_lgt_7_s0/CLK
10.251 -0.046 tSu 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/frame_lgt_7_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.297, 100.000%
Arrival Data Path Delay: cell: 2.441, 50.901%; route: 2.079, 43.356%; tC2Q: 0.275, 5.743%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.297, 100.000%

Path 5

Path Summary:
Slack 5.202
Data Arrival Time 5.049
Data Required Time 10.251
From xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_flag_5_s0
To xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/frame_lgt_15_s0
Launch Clk xgtx_clk_i[R]
Latch Clk xgtx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 xgtx_clk_i
0.000 0.000 tCL RR 1 xgtx_clk_i_ibuf/I
0.000 0.000 tINS RR 1334 xgtx_clk_i_ibuf/O
0.297 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_flag_5_s0/CLK
0.572 0.275 tC2Q RR 12 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_flag_5_s0/Q
0.869 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/tx_error_propagation_s5/I0
1.286 0.417 tINS RR 2 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/tx_error_propagation_s5/F
1.583 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n157_s4/I0
2.000 0.417 tINS RR 2 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n157_s4/F
2.297 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n156_s3/I0
2.713 0.417 tINS RR 6 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n156_s3/F
3.010 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n155_s4/I0
3.427 0.417 tINS RR 4 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n155_s4/F
3.724 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n143_s3/I2
4.090 0.365 tINS RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n143_s3/F
4.387 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n143_s2/I2
4.752 0.365 tINS RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/n143_s2/F
5.049 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/frame_lgt_15_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 10.000 active clock edge time
10.000 0.000 xgtx_clk_i
10.000 0.000 tCL RR 1 xgtx_clk_i_ibuf/I
10.000 0.000 tINS RR 1334 xgtx_clk_i_ibuf/O
10.297 0.297 tNET RR 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/frame_lgt_15_s0/CLK
10.251 -0.046 tSu 1 xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_framer/frame_lgt_15_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.297, 100.000%
Arrival Data Path Delay: cell: 2.398, 50.455%; route: 2.079, 43.750%; tC2Q: 0.275, 5.795%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.297, 100.000%