Timing Messages
| Report Title | Timing Analysis Report |
| Design File | E:\IP_Release\10G_Serial_Ethernet_MAC\1.1\ref_design\Gowin_10G_Ethernet_MAC_RefDesign\fpga_project\impl\gwsynthesis\fpga_project.vg |
| Physical Constraints File | E:\IP_Release\10G_Serial_Ethernet_MAC\1.1\ref_design\Gowin_10G_Ethernet_MAC_RefDesign\fpga_project\src\fpga_project.cst |
| Timing Constraint File | E:\IP_Release\10G_Serial_Ethernet_MAC\1.1\ref_design\Gowin_10G_Ethernet_MAC_RefDesign\fpga_project\src\fpga_project.sdc |
| Tool Version | V1.9.12.02 (64-bit) |
| Part Number | GW5AST-LV138FPG676AC2/I1 |
| Device | GW5AST-138 |
| Device Version | B |
| Created Time | Wed Mar 4 10:28:53 2026 |
| Legal Announcement | Copyright (C)2014-2026 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
| Setup Delay Model | Slow 0.873V 0C C2/I1 |
| Hold Delay Model | Fast 0.927V 85C C2/I1 |
| Numbers of Paths Analyzed | 19117 |
| Numbers of Endpoints Analyzed | 27226 |
| Numbers of Falling Endpoints | 10 |
| Numbers of Setup Violated Endpoints | 0 |
| Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
|---|---|---|---|---|---|---|---|---|---|
| 1 | serdes_tx_clk | Base | 6.173 | 161.996 | 0.000 | 3.087 | u_SerDes_Top/q1_lane1_fabric_tx_clk | ||
| 2 | serdes_rx_clk | Base | 6.173 | 161.996 | 0.000 | 3.087 | u_SerDes_Top/q1_lane1_fabric_rx_clk | ||
| 3 | tck_pad_i | Base | 50.000 | 20.000 | 0.000 | 25.000 | tck_pad_i | ||
| 4 | xgmii_clk | Base | 6.400 | 156.250 | 0.000 | 3.200 | tx_mac_clk |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | serdes_tx_clk | 161.996(MHz) | 204.304(MHz) | 4 | TOP |
| 2 | serdes_rx_clk | 161.996(MHz) | 191.794(MHz) | 6 | TOP |
| 3 | tck_pad_i | 20.000(MHz) | 102.569(MHz) | 6 | TOP |
| 4 | xgmii_clk | 156.250(MHz) | 180.992(MHz) | 5 | TOP |
Total Negative Slack Summary:
| Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
|---|---|---|---|
| serdes_tx_clk | Setup | 0.000 | 0 |
| serdes_tx_clk | Hold | 0.000 | 0 |
| serdes_rx_clk | Setup | 0.000 | 0 |
| serdes_rx_clk | Hold | 0.000 | 0 |
| tck_pad_i | Setup | 0.000 | 0 |
| tck_pad_i | Hold | 0.000 | 0 |
| xgmii_clk | Setup | 0.000 | 0 |
| xgmii_clk | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Setup Paths Table[1]:
Report Command:report_timing -setup -from_clock [get_clocks {serdes_rx_clk}] -to_clock [get_clocks {serdes_rx_clk}] -max_paths 50 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 0.959 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_45_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | 0.012 | 5.156 |
| 2 | 0.977 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_3_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.020 | 5.170 |
| 3 | 1.001 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_22_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.011 | 5.142 |
| 4 | 1.030 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_54_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.017 | 5.114 |
| 5 | 1.080 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_30_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.027 | 5.074 |
| 6 | 1.088 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_4_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.020 | 5.060 |
| 7 | 1.091 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_8_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.013 | 5.049 |
| 8 | 1.096 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/c_state_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_0_s0/CE | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.005 | 4.858 |
| 9 | 1.096 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/c_state_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_1_s0/CE | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.005 | 4.858 |
| 10 | 1.096 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/c_state_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_2_s0/CE | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.005 | 4.858 |
| 11 | 1.096 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/c_state_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_3_s0/CE | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.005 | 4.858 |
| 12 | 1.098 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_32_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.020 | 5.049 |
| 13 | 1.115 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_6_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.008 | 5.020 |
| 14 | 1.124 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_46_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | 0.008 | 4.995 |
| 15 | 1.233 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/c_state_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_2_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.005 | 4.899 |
| 16 | 1.233 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/c_state_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_3_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.005 | 4.899 |
| 17 | 1.243 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_38_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.005 | 4.889 |
| 18 | 1.248 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_16_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.020 | 4.899 |
| 19 | 1.259 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_34_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.020 | 4.888 |
| 20 | 1.273 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_43_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.017 | 4.871 |
| 21 | 1.290 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_14_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.025 | 4.863 |
| 22 | 1.322 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_59_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.021 | 4.826 |
| 23 | 1.322 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_60_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.021 | 4.826 |
| 24 | 1.324 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_2_s1/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_13_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | 0.010 | 4.793 |
| 25 | 1.325 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_10_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.013 | 4.815 |
| 26 | 1.330 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_63_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.021 | 4.818 |
| 27 | 1.366 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d2_14_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.025 | 4.786 |
| 28 | 1.379 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_2_s1/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_30_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | 0.012 | 4.736 |
| 29 | 1.387 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/c_state_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_0_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.005 | 4.745 |
| 30 | 1.387 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/c_state_0_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_1_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.005 | 4.745 |
| 31 | 1.388 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_36_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | 0.007 | 4.731 |
| 32 | 1.397 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_24_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.015 | 4.745 |
| 33 | 1.402 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_42_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.015 | 4.740 |
| 34 | 1.405 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_20_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.011 | 4.733 |
| 35 | 1.408 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_47_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.021 | 4.740 |
| 36 | 1.450 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_2_s1/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_31_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.007 | 4.684 |
| 37 | 1.461 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_44_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.011 | 4.677 |
| 38 | 1.515 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_28_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.015 | 4.627 |
| 39 | 1.525 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_2_s1/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_27_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.007 | 4.609 |
| 40 | 1.540 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_53_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.017 | 4.604 |
| 41 | 1.548 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_11_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.024 | 4.603 |
| 42 | 1.556 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_62_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.007 | 4.577 |
| 43 | 1.561 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_61_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.007 | 4.573 |
| 44 | 1.582 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_36_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | 0.007 | 4.538 |
| 45 | 1.597 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_22_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.032 | 4.562 |
| 46 | 1.597 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_32_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.027 | 4.557 |
| 47 | 1.612 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_12_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.024 | 4.540 |
| 48 | 1.612 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_14_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.024 | 4.540 |
| 49 | 1.630 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_26_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.008 | 4.505 |
| 50 | 1.631 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_26_s0/D | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 6.173 | -0.008 | 4.504 |
Setup Paths Table[2]:
Report Command:report_timing -setup -from_clock [get_clocks {serdes_tx_clk}] -to_clock [get_clocks {serdes_tx_clk}] -max_paths 50 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 1.278 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_s198/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | -0.010 | 4.859 |
| 2 | 1.287 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_init_s/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | -0.004 | 4.844 |
| 3 | 1.509 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_6_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.007 | 4.612 |
| 4 | 1.678 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_53_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | -0.001 | 4.450 |
| 5 | 1.723 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_42_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.001 | 4.403 |
| 6 | 1.757 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_53_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.016 | 4.354 |
| 7 | 1.781 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_28_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | -0.014 | 4.360 |
| 8 | 1.822 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_48_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.000 | 4.305 |
| 9 | 1.826 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_33_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | -0.014 | 4.315 |
| 10 | 1.875 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_36_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | -0.007 | 4.260 |
| 11 | 1.878 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_7_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.000 | 4.249 |
| 12 | 1.897 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_47_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.007 | 4.224 |
| 13 | 1.940 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_12_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | -0.016 | 4.203 |
| 14 | 1.970 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_57_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | -0.014 | 4.171 |
| 15 | 1.983 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_9_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.012 | 4.132 |
| 16 | 2.002 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_4_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.008 | 4.117 |
| 17 | 2.010 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_59_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | -0.016 | 4.133 |
| 18 | 2.024 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_50_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.008 | 4.095 |
| 19 | 2.025 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_2_s0/CE | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | -0.007 | 3.930 |
| 20 | 2.025 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_3_s0/CE | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | -0.007 | 3.930 |
| 21 | 2.025 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_4_s0/CE | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | -0.007 | 3.930 |
| 22 | 2.026 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_43_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.012 | 4.089 |
| 23 | 2.028 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_16_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | -0.001 | 4.100 |
| 24 | 2.046 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_44_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.015 | 4.066 |
| 25 | 2.047 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_34_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | -0.018 | 4.098 |
| 26 | 2.052 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_20_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.007 | 4.068 |
| 27 | 2.064 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_42_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.001 | 4.062 |
| 28 | 2.075 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_61_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | -0.026 | 4.078 |
| 29 | 2.078 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_41_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.005 | 4.044 |
| 30 | 2.087 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_24_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | -0.024 | 4.064 |
| 31 | 2.087 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_37_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.003 | 4.037 |
| 32 | 2.087 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_6_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.007 | 4.033 |
| 33 | 2.099 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_60_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.009 | 4.018 |
| 34 | 2.109 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/fifo_half_latch_s0/CE | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | -0.018 | 3.857 |
| 35 | 2.114 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_54_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.003 | 4.010 |
| 36 | 2.131 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_20_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.007 | 3.990 |
| 37 | 2.131 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_29_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.009 | 3.987 |
| 38 | 2.143 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_44_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.016 | 3.968 |
| 39 | 2.155 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_60_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.008 | 3.964 |
| 40 | 2.158 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_51_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | -0.019 | 3.989 |
| 41 | 2.166 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/din_d0_28_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_36_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.013 | 3.947 |
| 42 | 2.171 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_0_s0/CE | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.000 | 3.778 |
| 43 | 2.171 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_1_s0/CE | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.000 | 3.778 |
| 44 | 2.176 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_26_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | -0.024 | 3.975 |
| 45 | 2.185 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_37_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.003 | 3.939 |
| 46 | 2.191 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_15_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.005 | 3.930 |
| 47 | 2.194 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_14_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.000 | 3.933 |
| 48 | 2.195 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_62_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.005 | 3.927 |
| 49 | 2.209 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_34_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | -0.018 | 3.936 |
| 50 | 2.218 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_52_s0/D | serdes_tx_clk:[R] | serdes_tx_clk:[R] | 6.173 | 0.008 | 3.901 |
Setup Paths Table[3]:
Report Command:report_timing -setup -from_clock [get_clocks {xgmii_clk}] -to_clock [get_clocks {xgmii_clk}] -max_paths 50 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 0.875 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_31_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.009 | 5.489 |
| 2 | 0.875 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_63_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.009 | 5.489 |
| 3 | 0.876 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_44_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.016 | 5.494 |
| 4 | 0.878 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_21_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.025 | 5.501 |
| 5 | 0.892 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_4_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.016 | 5.445 |
| 6 | 0.892 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_26_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.016 | 5.445 |
| 7 | 0.892 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_58_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.016 | 5.445 |
| 8 | 0.894 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_33_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.015 | 5.445 |
| 9 | 0.913 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_12_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.016 | 5.457 |
| 10 | 1.022 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_28_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.001 | 5.330 |
| 11 | 1.022 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_60_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.001 | 5.330 |
| 12 | 1.047 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_1_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.018 | 5.290 |
| 13 | 1.047 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_36_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.018 | 5.290 |
| 14 | 1.047 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxc_align_reg_2_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.018 | 5.290 |
| 15 | 1.054 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_9_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.011 | 5.290 |
| 16 | 1.054 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_41_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.011 | 5.290 |
| 17 | 1.081 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_16_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.036 | 5.309 |
| 18 | 1.084 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxc_align_reg_6_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.018 | 5.253 |
| 19 | 1.133 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_17_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.004 | 5.225 |
| 20 | 1.149 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_19_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.029 | 5.234 |
| 21 | 1.168 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_20_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.008 | 5.178 |
| 22 | 1.168 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_52_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.008 | 5.178 |
| 23 | 1.215 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_23_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.011 | 5.129 |
| 24 | 1.247 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_12_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.000 | 5.107 |
| 25 | 1.274 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_22_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.009 | 5.089 |
| 26 | 1.321 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_23_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.046 | 5.079 |
| 27 | 1.338 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/cal_crc_64bit_20_s1/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/cal_crc_64bit_29_s1/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.003 | 5.019 |
| 28 | 1.361 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_20_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.007 | 5.000 |
| 29 | 1.372 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_55_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.011 | 4.971 |
| 30 | 1.373 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_0_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.009 | 4.971 |
| 31 | 1.373 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_32_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.009 | 4.971 |
| 32 | 1.374 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_11_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.041 | 5.021 |
| 33 | 1.375 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_16_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.008 | 4.971 |
| 34 | 1.375 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_18_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.008 | 4.971 |
| 35 | 1.382 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_8_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.001 | 4.971 |
| 36 | 1.382 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_40_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.001 | 4.971 |
| 37 | 1.382 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_48_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.001 | 4.971 |
| 38 | 1.382 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_50_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.001 | 4.971 |
| 39 | 1.394 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_18_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.009 | 4.968 |
| 40 | 1.524 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_13_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.012 | 4.842 |
| 41 | 1.533 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxc_align_reg_5_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.007 | 4.815 |
| 42 | 1.538 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_25_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.008 | 4.808 |
| 43 | 1.538 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_57_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.008 | 4.808 |
| 44 | 1.548 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_24_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.000 | 4.806 |
| 45 | 1.548 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_56_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.000 | 4.806 |
| 46 | 1.555 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxc_align_reg_1_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.007 | 4.792 |
| 47 | 1.579 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_6_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.013 | 4.788 |
| 48 | 1.591 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_4_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.004 | 4.768 |
| 49 | 1.604 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_2_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.020 | 4.770 |
| 50 | 1.617 | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/Q | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_24_s0/D | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.004 | 4.742 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 0.181 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_11_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[11] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.001 | 0.213 |
| 2 | 0.181 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_10_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[10] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.001 | 0.213 |
| 3 | 0.181 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_17_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/DI[17] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.001 | 0.213 |
| 4 | 0.184 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_80_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPB_mem_mem_0_2_s/DI[0] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.004 | 0.213 |
| 5 | 0.184 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_72_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[8] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.004 | 0.213 |
| 6 | 0.184 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_69_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[5] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.004 | 0.213 |
| 7 | 0.184 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_60_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/gowin_add_SDPX9B_mem_mem_0_1_s/DI[6] | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 0.000 | 0.004 | 0.213 |
| 8 | 0.184 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_20_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/gowin_add_SDPX9B_phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/DI[2] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.004 | 0.213 |
| 9 | 0.185 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPB_mem_mem_0_0_s/DI[3] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.005 | 0.213 |
| 10 | 0.185 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_7_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[7] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.005 | 0.213 |
| 11 | 0.185 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_1_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[1] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.005 | 0.213 |
| 12 | 0.185 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_4_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/DI[4] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.005 | 0.213 |
| 13 | 0.185 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/DI[2] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.005 | 0.213 |
| 14 | 0.188 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_58_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPB_mem_mem_0_1_s/DI[10] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.008 | 0.213 |
| 15 | 0.188 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_79_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[15] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.008 | 0.213 |
| 16 | 0.188 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_78_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[14] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.008 | 0.213 |
| 17 | 0.188 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_31_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/gowin_add_SDPX9B_mem_mem_0_0_s/DI[13] | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 0.000 | 0.008 | 0.213 |
| 18 | 0.188 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_28_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/gowin_add_SDPX9B_mem_mem_0_0_s/DI[10] | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 0.000 | 0.008 | 0.213 |
| 19 | 0.188 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_42_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[10] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.008 | 0.213 |
| 20 | 0.188 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_41_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[9] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.008 | 0.213 |
| 21 | 0.188 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/serdes_pcs_rx_rden_o_s0/Q | u_SerDes_Top/gtr12_quad_inst1/LANE1_RX_IF_FIFO_RDEN | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 0.000 | 0.002 | 0.223 |
| 22 | 0.190 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_82_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPB_mem_mem_0_2_s/DI[2] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.004 | 0.219 |
| 23 | 0.193 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_32_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/gowin_add_SDPX9B_mem_mem_0_0_s/DI[14] | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 0.000 | 0.008 | 0.219 |
| 24 | 0.194 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPB_mem_mem_0_0_s/DI[8] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.009 | 0.219 |
| 25 | 0.206 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_50_s0/Q | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPB_mem_mem_0_1_s/DI[2] | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.019 | 0.220 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 2.250 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe0_4_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.026 | 3.874 |
| 2 | 2.250 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_4_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.026 | 3.874 |
| 3 | 2.250 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr2ram_0_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.026 | 3.874 |
| 4 | 2.250 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr2ram_1_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.026 | 3.874 |
| 5 | 2.250 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr2ram_2_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.026 | 3.874 |
| 6 | 2.256 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr2ram_3_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.019 | 3.874 |
| 7 | 2.287 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_4_s0/PRESET | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.017 | 3.880 |
| 8 | 2.287 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_tmp_4_s0/PRESET | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.017 | 3.880 |
| 9 | 2.287 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d4_4_s0/PRESET | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.017 | 3.880 |
| 10 | 2.287 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d3_4_s0/PRESET | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.017 | 3.880 |
| 11 | 2.287 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d2_4_s0/PRESET | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.017 | 3.880 |
| 12 | 2.288 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_31_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.019 | 3.880 |
| 13 | 2.288 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_tmp_31_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | -0.019 | 3.880 |
| 14 | 2.314 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_pseudo_random_generators/dout_19_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.029 | 3.807 |
| 15 | 2.314 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_pseudo_random_generators/dout_62_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.029 | 3.807 |
| 16 | 2.314 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/phase_fifo_wr_data_47_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.029 | 3.807 |
| 17 | 2.314 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/phase_fifo_wr_data_64_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.029 | 3.807 |
| 18 | 2.314 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/phase_fifo_wr_data_65_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.029 | 3.807 |
| 19 | 2.418 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_4_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.032 | 3.699 |
| 20 | 2.418 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_0_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.032 | 3.699 |
| 21 | 2.418 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_1_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.032 | 3.699 |
| 22 | 2.418 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_2_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.032 | 3.699 |
| 23 | 2.418 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_3_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.032 | 3.699 |
| 24 | 2.425 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_dly1_0_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.026 | 3.699 |
| 25 | 2.425 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_dly1_1_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 6.400 | 0.026 | 3.699 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 0.335 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_wr_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_wr_d1_2_s0/PRESET | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 0.000 | 0.024 | 0.264 |
| 2 | 0.335 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_wr_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_wr_d1_10_s0/CLEAR | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 0.000 | 0.024 | 0.264 |
| 3 | 0.335 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_wr_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_wr_d1_16_s0/CLEAR | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 0.000 | 0.024 | 0.264 |
| 4 | 0.335 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_wr_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_wr_d1_37_s0/CLEAR | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 0.000 | 0.024 | 0.264 |
| 5 | 0.351 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_0_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | -0.005 | 0.308 |
| 6 | 0.351 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_tmp_0_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | -0.005 | 0.308 |
| 7 | 0.351 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d4_0_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | -0.005 | 0.308 |
| 8 | 0.351 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d3_0_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | -0.005 | 0.308 |
| 9 | 0.351 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d2_0_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | -0.005 | 0.308 |
| 10 | 0.361 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_5_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.004 | 0.310 |
| 11 | 0.361 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_tmp_5_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.004 | 0.310 |
| 12 | 0.361 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d4_5_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.004 | 0.310 |
| 13 | 0.361 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d3_5_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.004 | 0.310 |
| 14 | 0.361 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d2_5_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.004 | 0.310 |
| 15 | 0.362 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_rx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/block_payload_d3_21_s0/CLEAR | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 0.000 | -0.004 | 0.318 |
| 16 | 0.362 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_rx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/block_payload_d2_21_s0/CLEAR | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 0.000 | -0.004 | 0.318 |
| 17 | 0.362 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_rx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/block_payload_d2_41_s0/CLEAR | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 0.000 | -0.004 | 0.318 |
| 18 | 0.362 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_rx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/block_payload_d1_14_s0/CLEAR | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 0.000 | -0.004 | 0.318 |
| 19 | 0.362 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_rx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/block_payload_d1_39_s0/CLEAR | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 0.000 | -0.004 | 0.318 |
| 20 | 0.362 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_rx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/block_payload_d1_41_s0/CLEAR | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 0.000 | -0.004 | 0.318 |
| 21 | 0.362 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_rx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/block_payload_d1_52_s0/CLEAR | serdes_rx_clk:[R] | serdes_rx_clk:[R] | 0.000 | -0.004 | 0.318 |
| 22 | 0.364 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d4_44_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.002 | 0.315 |
| 23 | 0.364 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d3_44_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.002 | 0.315 |
| 24 | 0.364 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d3_50_s0/PRESET | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.002 | 0.315 |
| 25 | 0.364 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d2_44_s0/CLEAR | xgmii_clk:[R] | xgmii_clk:[R] | 0.000 | 0.002 | 0.315 |
Minimum Pulse Width Table:
| Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
|---|---|---|---|---|---|---|
| 1 | 0.371 | 1.146 | 0.776 | Low Pulse Width | xgmii_clk | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPB_mem_mem_0_0_s |
| 2 | 0.374 | 1.150 | 0.776 | Low Pulse Width | xgmii_clk | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s |
| 3 | 0.374 | 1.150 | 0.776 | Low Pulse Width | xgmii_clk | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s |
| 4 | 0.374 | 1.150 | 0.776 | Low Pulse Width | xgmii_clk | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
| 5 | 0.377 | 1.153 | 0.776 | Low Pulse Width | xgmii_clk | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_1_s |
| 6 | 0.377 | 1.153 | 0.776 | Low Pulse Width | xgmii_clk | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s |
| 7 | 0.377 | 1.153 | 0.776 | Low Pulse Width | xgmii_clk | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
| 8 | 0.377 | 1.153 | 0.776 | Low Pulse Width | xgmii_clk | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/gowin_add_SDPX9B_phase_fifo_rd_data_phase_fifo_rd_data_0_0_s |
| 9 | 0.377 | 1.153 | 0.776 | Low Pulse Width | xgmii_clk | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/gowin_add_SDPX9B_mem_mem_0_1_s |
| 10 | 0.377 | 1.153 | 0.776 | Low Pulse Width | xgmii_clk | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPB_mem_mem_0_2_s |
Timing Report By Analysis Type:
Setup Analysis Report
Setup Analysis Report[1]:
Report Command:report_timing -setup -from_clock [get_clocks {serdes_rx_clk}] -to_clock [get_clocks {serdes_rx_clk}] -max_paths 50 -max_common_paths 1
Path1
Path Summary:
| Slack | 0.959 |
| Data Arrival Time | 6.846 |
| Data Required Time | 7.805 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_45_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.690 | 1.690 | tNET | RR | 1 | R47C127[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/CLK |
| 1.965 | 0.275 | tC2Q | RR | 54 | R47C127[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q |
| 3.126 | 1.161 | tNET | RR | 1 | R50C120[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3168_s17/I0 |
| 3.543 | 0.417 | tINS | RR | 3 | R50C120[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3168_s17/F |
| 3.971 | 0.428 | tNET | RR | 1 | R49C123[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3137_s15/I0 |
| 4.337 | 0.365 | tINS | RR | 5 | R49C123[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3137_s15/F |
| 5.094 | 0.757 | tNET | RR | 1 | R44C123[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3127_s14/I0 |
| 5.502 | 0.409 | tINS | RR | 5 | R44C123[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3127_s14/F |
| 6.066 | 0.563 | tNET | RR | 1 | R48C121[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3129_s11/I3 |
| 6.479 | 0.413 | tINS | RR | 1 | R48C121[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3129_s11/F |
| 6.480 | 0.002 | tNET | RR | 1 | R48C121[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3129_s10/I2 |
| 6.846 | 0.365 | tINS | RR | 1 | R48C121[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3129_s10/F |
| 6.846 | 0.000 | tNET | RR | 1 | R48C121[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_45_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.851 | 1.678 | tNET | RR | 1 | R48C121[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_45_s0/CLK |
| 7.805 | -0.046 | tSu | 1 | R48C121[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_45_s0 |
Path Statistics:
| Clock Skew | -0.012 |
| Setup Relationship | 6.173 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.690, 100.000% |
| Arrival Data Path Delay | cell: 1.969, 38.192%; route: 2.912, 56.467%; tC2Q: 0.275, 5.341% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.678, 100.000% |
Path2
Path Summary:
| Slack | 0.977 |
| Data Arrival Time | 6.869 |
| Data Required Time | 7.846 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_3_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.699 | 1.699 | tNET | RR | 1 | R44C126[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/CLK |
| 1.974 | 0.275 | tC2Q | RR | 16 | R44C126[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/Q |
| 2.758 | 0.784 | tNET | RR | 1 | R48C123[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3168_s16/I3 |
| 3.152 | 0.394 | tINS | RR | 2 | R48C123[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3168_s16/F |
| 3.709 | 0.557 | tNET | RR | 1 | R48C119[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3168_s12/I1 |
| 4.126 | 0.417 | tINS | RR | 3 | R48C119[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3168_s12/F |
| 4.567 | 0.441 | tNET | RR | 1 | R43C121[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3170_s13/I3 |
| 4.980 | 0.413 | tINS | RR | 2 | R43C121[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3170_s13/F |
| 5.785 | 0.805 | tNET | RR | 1 | R40C124[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3171_s14/I2 |
| 6.193 | 0.409 | tINS | RR | 1 | R40C124[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3171_s14/F |
| 6.452 | 0.259 | tNET | RR | 1 | R42C124[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3171_s13/I1 |
| 6.869 | 0.417 | tINS | RR | 1 | R42C124[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3171_s13/F |
| 6.869 | 0.000 | tNET | RR | 1 | R42C124[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_3_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.892 | 1.719 | tNET | RR | 1 | R42C124[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_3_s0/CLK |
| 7.846 | -0.046 | tSu | 1 | R42C124[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_3_s0 |
Path Statistics:
| Clock Skew | 0.020 |
| Setup Relationship | 6.173 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.699, 100.000% |
| Arrival Data Path Delay | cell: 2.049, 39.634%; route: 2.846, 55.039%; tC2Q: 0.275, 5.326% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.719, 100.000% |
Path3
Path Summary:
| Slack | 1.001 |
| Data Arrival Time | 6.827 |
| Data Required Time | 7.828 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_22_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.685 | 1.685 | tNET | RR | 1 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/CLK |
| 1.950 | 0.265 | tC2Q | RF | 128 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q |
| 4.423 | 2.473 | tNET | FF | 1 | R33C142[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n975_s6/I2 |
| 4.788 | 0.365 | tINS | FR | 2 | R33C142[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n975_s6/F |
| 5.065 | 0.276 | tNET | RR | 1 | R32C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n766_s3/I1 |
| 5.481 | 0.417 | tINS | RR | 4 | R32C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n766_s3/F |
| 6.597 | 1.116 | tNET | RR | 1 | R29C136[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n547_s2/I1 |
| 6.827 | 0.229 | tINS | RF | 1 | R29C136[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n547_s2/F |
| 6.827 | 0.000 | tNET | FF | 1 | R29C136[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_22_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.869 | 1.696 | tNET | RR | 1 | R29C136[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_22_s0/CLK |
| 7.828 | -0.041 | tSu | 1 | R29C136[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_22_s0 |
Path Statistics:
| Clock Skew | 0.011 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.685, 100.000% |
| Arrival Data Path Delay | cell: 1.012, 19.674%; route: 3.865, 75.179%; tC2Q: 0.265, 5.146% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.696, 100.000% |
Path4
Path Summary:
| Slack | 1.030 |
| Data Arrival Time | 6.804 |
| Data Required Time | 7.834 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_54_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.690 | 1.690 | tNET | RR | 1 | R47C127[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/CLK |
| 1.965 | 0.275 | tC2Q | RR | 54 | R47C127[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q |
| 3.126 | 1.161 | tNET | RR | 1 | R50C120[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3168_s17/I0 |
| 3.543 | 0.417 | tINS | RR | 3 | R50C120[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3168_s17/F |
| 3.971 | 0.428 | tNET | RR | 1 | R49C123[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3137_s15/I0 |
| 4.337 | 0.365 | tINS | RR | 5 | R49C123[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3137_s15/F |
| 4.836 | 0.499 | tNET | RR | 1 | R43C125[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3119_s14/I0 |
| 5.249 | 0.413 | tINS | RR | 5 | R43C125[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3119_s14/F |
| 5.676 | 0.427 | tNET | RR | 1 | R45C123[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3120_s11/I3 |
| 6.084 | 0.409 | tINS | RR | 1 | R45C123[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3120_s11/F |
| 6.387 | 0.302 | tNET | RR | 1 | R45C120[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3120_s10/I2 |
| 6.804 | 0.417 | tINS | RR | 1 | R45C120[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3120_s10/F |
| 6.804 | 0.000 | tNET | RR | 1 | R45C120[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_54_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.880 | 1.707 | tNET | RR | 1 | R45C120[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_54_s0/CLK |
| 7.834 | -0.046 | tSu | 1 | R45C120[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_54_s0 |
Path Statistics:
| Clock Skew | 0.017 |
| Setup Relationship | 6.173 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.690, 100.000% |
| Arrival Data Path Delay | cell: 2.020, 39.511%; route: 2.818, 55.104%; tC2Q: 0.275, 5.385% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.707, 100.000% |
Path5
Path Summary:
| Slack | 1.080 |
| Data Arrival Time | 6.759 |
| Data Required Time | 7.839 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_30_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.685 | 1.685 | tNET | RR | 1 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/CLK |
| 1.950 | 0.265 | tC2Q | RF | 128 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q |
| 4.423 | 2.473 | tNET | FF | 1 | R33C142[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n975_s6/I2 |
| 4.788 | 0.365 | tINS | FR | 2 | R33C142[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n975_s6/F |
| 5.065 | 0.276 | tNET | RR | 1 | R32C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n766_s3/I1 |
| 5.481 | 0.417 | tINS | RR | 4 | R32C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n766_s3/F |
| 6.394 | 0.913 | tNET | RR | 1 | R26C136[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n539_s2/I0 |
| 6.759 | 0.365 | tINS | RR | 1 | R26C136[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n539_s2/F |
| 6.759 | 0.000 | tNET | RR | 1 | R26C136[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_30_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.885 | 1.712 | tNET | RR | 1 | R26C136[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_30_s0/CLK |
| 7.839 | -0.046 | tSu | 1 | R26C136[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_30_s0 |
Path Statistics:
| Clock Skew | 0.027 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.685, 100.000% |
| Arrival Data Path Delay | cell: 1.147, 22.614%; route: 3.662, 72.171%; tC2Q: 0.265, 5.215% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.712, 100.000% |
Path6
Path Summary:
| Slack | 1.088 |
| Data Arrival Time | 6.758 |
| Data Required Time | 7.846 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_4_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.699 | 1.699 | tNET | RR | 1 | R44C126[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/CLK |
| 1.974 | 0.275 | tC2Q | RR | 16 | R44C126[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/S_d5_s0/Q |
| 2.758 | 0.784 | tNET | RR | 1 | R48C123[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3168_s16/I3 |
| 3.152 | 0.394 | tINS | RR | 2 | R48C123[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3168_s16/F |
| 3.709 | 0.557 | tNET | RR | 1 | R48C119[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3168_s12/I1 |
| 4.126 | 0.417 | tINS | RR | 3 | R48C119[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3168_s12/F |
| 4.567 | 0.441 | tNET | RR | 1 | R43C121[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3170_s13/I3 |
| 4.980 | 0.413 | tINS | RR | 2 | R43C121[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3170_s13/F |
| 5.677 | 0.697 | tNET | RR | 1 | R40C124[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3170_s11/I2 |
| 6.091 | 0.413 | tINS | RR | 1 | R40C124[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3170_s11/F |
| 6.350 | 0.259 | tNET | RR | 1 | R42C124[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3170_s9/I1 |
| 6.758 | 0.409 | tINS | RR | 1 | R42C124[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3170_s9/F |
| 6.758 | 0.000 | tNET | RR | 1 | R42C124[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_4_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.892 | 1.719 | tNET | RR | 1 | R42C124[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_4_s0/CLK |
| 7.846 | -0.046 | tSu | 1 | R42C124[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_4_s0 |
Path Statistics:
| Clock Skew | 0.020 |
| Setup Relationship | 6.173 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.699, 100.000% |
| Arrival Data Path Delay | cell: 2.046, 40.430%; route: 2.739, 54.127%; tC2Q: 0.275, 5.443% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.719, 100.000% |
Path7
Path Summary:
| Slack | 1.091 |
| Data Arrival Time | 6.734 |
| Data Required Time | 7.826 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_8_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.685 | 1.685 | tNET | RR | 1 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/CLK |
| 1.950 | 0.265 | tC2Q | RF | 128 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q |
| 4.423 | 2.473 | tNET | FF | 1 | R33C142[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n975_s6/I2 |
| 4.788 | 0.365 | tINS | FR | 2 | R33C142[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n975_s6/F |
| 4.942 | 0.154 | tNET | RR | 1 | R33C140[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n975_s4/I0 |
| 5.351 | 0.409 | tINS | RR | 5 | R33C140[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n975_s4/F |
| 6.369 | 1.018 | tNET | RR | 1 | R26C138[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n764_s3/I1 |
| 6.734 | 0.365 | tINS | RR | 1 | R26C138[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n764_s3/F |
| 6.734 | 0.000 | tNET | RR | 1 | R26C138[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_8_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.872 | 1.699 | tNET | RR | 1 | R26C138[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_8_s0/CLK |
| 7.826 | -0.046 | tSu | 1 | R26C138[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_8_s0 |
Path Statistics:
| Clock Skew | 0.013 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.685, 100.000% |
| Arrival Data Path Delay | cell: 1.139, 22.567%; route: 3.645, 72.193%; tC2Q: 0.265, 5.241% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.699, 100.000% |
Path8
Path Summary:
| Slack | 1.096 |
| Data Arrival Time | 6.570 |
| Data Required Time | 7.666 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/c_state_0_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_0_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.712 | 1.712 | tNET | RR | 1 | R26C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/c_state_0_s0/CLK |
| 1.987 | 0.275 | tC2Q | RR | 80 | R26C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/c_state_0_s0/Q |
| 2.283 | 0.295 | tNET | RR | 1 | R25C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/locked_s79/I1 |
| 2.691 | 0.409 | tINS | RR | 2885 | R25C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/locked_s79/F |
| 5.897 | 3.206 | tNET | RR | 1 | R25C123[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_3_s4/I3 |
| 6.126 | 0.229 | tINS | RF | 5 | R25C123[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_3_s4/F |
| 6.250 | 0.123 | tNET | FF | 1 | R25C124[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_3_s5/I0 |
| 6.459 | 0.210 | tINS | FR | 4 | R25C124[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_3_s5/F |
| 6.570 | 0.111 | tNET | RR | 1 | R25C124[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_0_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.890 | 1.717 | tNET | RR | 1 | R25C124[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_0_s0/CLK |
| 7.666 | -0.224 | tSu | 1 | R25C124[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_0_s0 |
Path Statistics:
| Clock Skew | 0.005 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.712, 100.000% |
| Arrival Data Path Delay | cell: 0.848, 17.452%; route: 3.735, 76.879%; tC2Q: 0.275, 5.669% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.717, 100.000% |
Path9
Path Summary:
| Slack | 1.096 |
| Data Arrival Time | 6.570 |
| Data Required Time | 7.666 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/c_state_0_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_1_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.712 | 1.712 | tNET | RR | 1 | R26C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/c_state_0_s0/CLK |
| 1.987 | 0.275 | tC2Q | RR | 80 | R26C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/c_state_0_s0/Q |
| 2.283 | 0.295 | tNET | RR | 1 | R25C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/locked_s79/I1 |
| 2.691 | 0.409 | tINS | RR | 2885 | R25C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/locked_s79/F |
| 5.897 | 3.206 | tNET | RR | 1 | R25C123[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_3_s4/I3 |
| 6.126 | 0.229 | tINS | RF | 5 | R25C123[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_3_s4/F |
| 6.250 | 0.123 | tNET | FF | 1 | R25C124[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_3_s5/I0 |
| 6.459 | 0.210 | tINS | FR | 4 | R25C124[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_3_s5/F |
| 6.570 | 0.111 | tNET | RR | 1 | R25C124[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_1_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.890 | 1.717 | tNET | RR | 1 | R25C124[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_1_s0/CLK |
| 7.666 | -0.224 | tSu | 1 | R25C124[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_1_s0 |
Path Statistics:
| Clock Skew | 0.005 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.712, 100.000% |
| Arrival Data Path Delay | cell: 0.848, 17.452%; route: 3.735, 76.879%; tC2Q: 0.275, 5.669% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.717, 100.000% |
Path10
Path Summary:
| Slack | 1.096 |
| Data Arrival Time | 6.570 |
| Data Required Time | 7.666 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/c_state_0_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_2_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.712 | 1.712 | tNET | RR | 1 | R26C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/c_state_0_s0/CLK |
| 1.987 | 0.275 | tC2Q | RR | 80 | R26C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/c_state_0_s0/Q |
| 2.283 | 0.295 | tNET | RR | 1 | R25C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/locked_s79/I1 |
| 2.691 | 0.409 | tINS | RR | 2885 | R25C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/locked_s79/F |
| 5.897 | 3.206 | tNET | RR | 1 | R25C123[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_3_s4/I3 |
| 6.126 | 0.229 | tINS | RF | 5 | R25C123[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_3_s4/F |
| 6.250 | 0.123 | tNET | FF | 1 | R25C124[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_3_s5/I0 |
| 6.459 | 0.210 | tINS | FR | 4 | R25C124[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_3_s5/F |
| 6.570 | 0.111 | tNET | RR | 1 | R25C124[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_2_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.890 | 1.717 | tNET | RR | 1 | R25C124[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_2_s0/CLK |
| 7.666 | -0.224 | tSu | 1 | R25C124[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_2_s0 |
Path Statistics:
| Clock Skew | 0.005 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.712, 100.000% |
| Arrival Data Path Delay | cell: 0.848, 17.452%; route: 3.735, 76.879%; tC2Q: 0.275, 5.669% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.717, 100.000% |
Path11
Path Summary:
| Slack | 1.096 |
| Data Arrival Time | 6.570 |
| Data Required Time | 7.666 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/c_state_0_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_3_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.712 | 1.712 | tNET | RR | 1 | R26C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/c_state_0_s0/CLK |
| 1.987 | 0.275 | tC2Q | RR | 80 | R26C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/c_state_0_s0/Q |
| 2.283 | 0.295 | tNET | RR | 1 | R25C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/locked_s79/I1 |
| 2.691 | 0.409 | tINS | RR | 2885 | R25C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/locked_s79/F |
| 5.897 | 3.206 | tNET | RR | 1 | R25C123[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_3_s4/I3 |
| 6.126 | 0.229 | tINS | RF | 5 | R25C123[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_3_s4/F |
| 6.250 | 0.123 | tNET | FF | 1 | R25C124[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_3_s5/I0 |
| 6.459 | 0.210 | tINS | FR | 4 | R25C124[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_3_s5/F |
| 6.570 | 0.111 | tNET | RR | 1 | R25C124[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_3_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.890 | 1.717 | tNET | RR | 1 | R25C124[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_3_s0/CLK |
| 7.666 | -0.224 | tSu | 1 | R25C124[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_3_s0 |
Path Statistics:
| Clock Skew | 0.005 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.712, 100.000% |
| Arrival Data Path Delay | cell: 0.848, 17.452%; route: 3.735, 76.879%; tC2Q: 0.275, 5.669% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.717, 100.000% |
Path12
Path Summary:
| Slack | 1.098 |
| Data Arrival Time | 6.734 |
| Data Required Time | 7.832 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_32_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.685 | 1.685 | tNET | RR | 1 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/CLK |
| 1.950 | 0.265 | tC2Q | RF | 128 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q |
| 4.423 | 2.473 | tNET | FF | 1 | R33C142[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n975_s6/I2 |
| 4.788 | 0.365 | tINS | FR | 2 | R33C142[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n975_s6/F |
| 4.942 | 0.154 | tNET | RR | 1 | R33C140[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n975_s4/I0 |
| 5.351 | 0.409 | tINS | RR | 5 | R33C140[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n975_s4/F |
| 6.326 | 0.975 | tNET | RR | 1 | R26C137[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n537_s2/I0 |
| 6.734 | 0.409 | tINS | RR | 1 | R26C137[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n537_s2/F |
| 6.734 | 0.000 | tNET | RR | 1 | R26C137[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_32_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.878 | 1.705 | tNET | RR | 1 | R26C137[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_32_s0/CLK |
| 7.832 | -0.046 | tSu | 1 | R26C137[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_32_s0 |
Path Statistics:
| Clock Skew | 0.020 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.685, 100.000% |
| Arrival Data Path Delay | cell: 1.183, 23.422%; route: 3.602, 71.337%; tC2Q: 0.265, 5.241% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.705, 100.000% |
Path13
Path Summary:
| Slack | 1.115 |
| Data Arrival Time | 6.705 |
| Data Required Time | 7.820 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_6_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.685 | 1.685 | tNET | RR | 1 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/CLK |
| 1.950 | 0.265 | tC2Q | RF | 128 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q |
| 4.423 | 2.473 | tNET | FF | 1 | R33C142[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n975_s6/I2 |
| 4.788 | 0.365 | tINS | FR | 2 | R33C142[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n975_s6/F |
| 5.065 | 0.276 | tNET | RR | 1 | R32C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n766_s3/I1 |
| 5.481 | 0.417 | tINS | RR | 4 | R32C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n766_s3/F |
| 6.297 | 0.815 | tNET | RR | 1 | R32C136[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n766_s4/I1 |
| 6.705 | 0.409 | tINS | RR | 1 | R32C136[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n766_s4/F |
| 6.705 | 0.000 | tNET | RR | 1 | R32C136[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_6_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.866 | 1.693 | tNET | RR | 1 | R32C136[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_6_s0/CLK |
| 7.820 | -0.046 | tSu | 1 | R32C136[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_6_s0 |
Path Statistics:
| Clock Skew | 0.008 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.685, 100.000% |
| Arrival Data Path Delay | cell: 1.191, 23.718%; route: 3.565, 71.011%; tC2Q: 0.265, 5.271% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.693, 100.000% |
Path14
Path Summary:
| Slack | 1.124 |
| Data Arrival Time | 6.685 |
| Data Required Time | 7.809 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_46_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.690 | 1.690 | tNET | RR | 1 | R47C127[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/CLK |
| 1.965 | 0.275 | tC2Q | RR | 54 | R47C127[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q |
| 3.126 | 1.161 | tNET | RR | 1 | R50C120[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3168_s17/I0 |
| 3.543 | 0.417 | tINS | RR | 3 | R50C120[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3168_s17/F |
| 3.971 | 0.428 | tNET | RR | 1 | R49C123[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3137_s15/I0 |
| 4.337 | 0.365 | tINS | RR | 5 | R49C123[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3137_s15/F |
| 5.094 | 0.757 | tNET | RR | 1 | R44C123[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3127_s14/I0 |
| 5.502 | 0.409 | tINS | RR | 5 | R44C123[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3127_s14/F |
| 5.958 | 0.456 | tNET | RR | 1 | R48C121[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3128_s11/I3 |
| 6.353 | 0.394 | tINS | RR | 1 | R48C121[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3128_s11/F |
| 6.477 | 0.124 | tNET | RR | 1 | R49C121[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3128_s10/I2 |
| 6.685 | 0.208 | tINS | RR | 1 | R49C121[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3128_s10/F |
| 6.685 | 0.000 | tNET | RR | 1 | R49C121[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_46_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.855 | 1.682 | tNET | RR | 1 | R49C121[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_46_s0/CLK |
| 7.809 | -0.046 | tSu | 1 | R49C121[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_46_s0 |
Path Statistics:
| Clock Skew | -0.008 |
| Setup Relationship | 6.173 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.690, 100.000% |
| Arrival Data Path Delay | cell: 1.793, 35.892%; route: 2.927, 58.595%; tC2Q: 0.275, 5.514% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.682, 100.000% |
Path15
Path Summary:
| Slack | 1.233 |
| Data Arrival Time | 6.611 |
| Data Required Time | 7.844 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/c_state_0_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_2_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.712 | 1.712 | tNET | RR | 1 | R26C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/c_state_0_s0/CLK |
| 1.987 | 0.275 | tC2Q | RR | 80 | R26C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/c_state_0_s0/Q |
| 2.283 | 0.295 | tNET | RR | 1 | R25C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/locked_s79/I1 |
| 2.691 | 0.409 | tINS | RR | 2885 | R25C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/locked_s79/F |
| 5.897 | 3.206 | tNET | RR | 1 | R25C123[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_3_s4/I3 |
| 6.126 | 0.229 | tINS | RF | 5 | R25C123[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_3_s4/F |
| 6.246 | 0.120 | tNET | FF | 1 | R25C124[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/n460_s2/I3 |
| 6.611 | 0.365 | tINS | FR | 1 | R25C124[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/n460_s2/F |
| 6.611 | 0.000 | tNET | RR | 1 | R25C124[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_2_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.890 | 1.717 | tNET | RR | 1 | R25C124[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_2_s0/CLK |
| 7.844 | -0.046 | tSu | 1 | R25C124[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_2_s0 |
Path Statistics:
| Clock Skew | 0.005 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.712, 100.000% |
| Arrival Data Path Delay | cell: 1.003, 20.482%; route: 3.620, 73.897%; tC2Q: 0.275, 5.621% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.717, 100.000% |
Path16
Path Summary:
| Slack | 1.233 |
| Data Arrival Time | 6.611 |
| Data Required Time | 7.844 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/c_state_0_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_3_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.712 | 1.712 | tNET | RR | 1 | R26C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/c_state_0_s0/CLK |
| 1.987 | 0.275 | tC2Q | RR | 80 | R26C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/c_state_0_s0/Q |
| 2.283 | 0.295 | tNET | RR | 1 | R25C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/locked_s79/I1 |
| 2.691 | 0.409 | tINS | RR | 2885 | R25C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/locked_s79/F |
| 5.897 | 3.206 | tNET | RR | 1 | R25C123[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_3_s4/I3 |
| 6.126 | 0.229 | tINS | RF | 5 | R25C123[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_3_s4/F |
| 6.246 | 0.120 | tNET | FF | 1 | R25C124[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/n459_s2/I2 |
| 6.611 | 0.365 | tINS | FR | 1 | R25C124[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/n459_s2/F |
| 6.611 | 0.000 | tNET | RR | 1 | R25C124[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_3_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.890 | 1.717 | tNET | RR | 1 | R25C124[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_3_s0/CLK |
| 7.844 | -0.046 | tSu | 1 | R25C124[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_3_s0 |
Path Statistics:
| Clock Skew | 0.005 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.712, 100.000% |
| Arrival Data Path Delay | cell: 1.003, 20.482%; route: 3.620, 73.897%; tC2Q: 0.275, 5.621% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.717, 100.000% |
Path17
Path Summary:
| Slack | 1.243 |
| Data Arrival Time | 6.574 |
| Data Required Time | 7.817 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_38_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.685 | 1.685 | tNET | RR | 1 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/CLK |
| 1.950 | 0.265 | tC2Q | RF | 128 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q |
| 4.272 | 2.322 | tNET | FF | 1 | R33C141[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n975_s8/I2 |
| 4.637 | 0.365 | tINS | FR | 2 | R33C141[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n975_s8/F |
| 4.763 | 0.126 | tNET | RR | 1 | R33C140[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n969_s3/I1 |
| 5.172 | 0.409 | tINS | RR | 5 | R33C140[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n969_s3/F |
| 6.165 | 0.994 | tNET | RR | 1 | R29C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n531_s2/I0 |
| 6.574 | 0.409 | tINS | RR | 1 | R29C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n531_s2/F |
| 6.574 | 0.000 | tNET | RR | 1 | R29C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_38_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.863 | 1.690 | tNET | RR | 1 | R29C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_38_s0/CLK |
| 7.817 | -0.046 | tSu | 1 | R29C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_38_s0 |
Path Statistics:
| Clock Skew | 0.005 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.685, 100.000% |
| Arrival Data Path Delay | cell: 1.183, 24.190%; route: 3.442, 70.398%; tC2Q: 0.265, 5.412% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.690, 100.000% |
Path18
Path Summary:
| Slack | 1.248 |
| Data Arrival Time | 6.584 |
| Data Required Time | 7.832 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_16_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.685 | 1.685 | tNET | RR | 1 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/CLK |
| 1.950 | 0.265 | tC2Q | RF | 128 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q |
| 4.423 | 2.473 | tNET | FF | 1 | R33C142[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n975_s6/I2 |
| 4.788 | 0.365 | tINS | FR | 2 | R33C142[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n975_s6/F |
| 4.942 | 0.154 | tNET | RR | 1 | R33C140[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n975_s4/I0 |
| 5.351 | 0.409 | tINS | RR | 5 | R33C140[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n975_s4/F |
| 6.219 | 0.868 | tNET | RR | 1 | R26C137[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n756_s2/I0 |
| 6.584 | 0.365 | tINS | RR | 1 | R26C137[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n756_s2/F |
| 6.584 | 0.000 | tNET | RR | 1 | R26C137[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_16_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.878 | 1.705 | tNET | RR | 1 | R26C137[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_16_s0/CLK |
| 7.832 | -0.046 | tSu | 1 | R26C137[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_16_s0 |
Path Statistics:
| Clock Skew | 0.020 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.685, 100.000% |
| Arrival Data Path Delay | cell: 1.139, 23.259%; route: 3.495, 71.339%; tC2Q: 0.265, 5.401% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.705, 100.000% |
Path19
Path Summary:
| Slack | 1.259 |
| Data Arrival Time | 6.573 |
| Data Required Time | 7.832 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_34_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.685 | 1.685 | tNET | RR | 1 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/CLK |
| 1.950 | 0.265 | tC2Q | RF | 128 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q |
| 4.272 | 2.322 | tNET | FF | 1 | R33C141[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1145_s4/I2 |
| 4.637 | 0.365 | tINS | FR | 2 | R33C141[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1145_s4/F |
| 5.064 | 0.427 | tNET | RR | 1 | R30C140[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1145_s3/I1 |
| 5.274 | 0.210 | tINS | RR | 4 | R30C140[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1145_s3/F |
| 6.165 | 0.891 | tNET | RR | 1 | R26C141[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1145_s5/I1 |
| 6.573 | 0.409 | tINS | RR | 1 | R26C141[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1145_s5/F |
| 6.573 | 0.000 | tNET | RR | 1 | R26C141[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_34_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.878 | 1.705 | tNET | RR | 1 | R26C141[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_34_s0/CLK |
| 7.832 | -0.046 | tSu | 1 | R26C141[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_34_s0 |
Path Statistics:
| Clock Skew | 0.020 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.685, 100.000% |
| Arrival Data Path Delay | cell: 0.984, 20.125%; route: 3.640, 74.461%; tC2Q: 0.265, 5.413% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.705, 100.000% |
Path20
Path Summary:
| Slack | 1.273 |
| Data Arrival Time | 6.561 |
| Data Required Time | 7.834 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_43_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.690 | 1.690 | tNET | RR | 1 | R47C127[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/CLK |
| 1.965 | 0.275 | tC2Q | RR | 54 | R47C127[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q |
| 3.126 | 1.161 | tNET | RR | 1 | R50C120[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3168_s17/I0 |
| 3.543 | 0.417 | tINS | RR | 3 | R50C120[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3168_s17/F |
| 3.971 | 0.428 | tNET | RR | 1 | R49C123[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3137_s15/I0 |
| 4.337 | 0.365 | tINS | RR | 5 | R49C123[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3137_s15/F |
| 5.094 | 0.757 | tNET | RR | 1 | R44C123[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3127_s14/I0 |
| 5.502 | 0.409 | tINS | RR | 5 | R44C123[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3127_s14/F |
| 5.780 | 0.278 | tNET | RR | 1 | R45C124[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3131_s11/I3 |
| 6.146 | 0.365 | tINS | RR | 1 | R45C124[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3131_s11/F |
| 6.147 | 0.002 | tNET | RR | 1 | R45C124[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3131_s10/I2 |
| 6.561 | 0.413 | tINS | RR | 1 | R45C124[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3131_s10/F |
| 6.561 | 0.000 | tNET | RR | 1 | R45C124[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_43_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.880 | 1.707 | tNET | RR | 1 | R45C124[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_43_s0/CLK |
| 7.834 | -0.046 | tSu | 1 | R45C124[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_43_s0 |
Path Statistics:
| Clock Skew | 0.017 |
| Setup Relationship | 6.173 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.690, 100.000% |
| Arrival Data Path Delay | cell: 1.969, 40.429%; route: 2.626, 53.917%; tC2Q: 0.275, 5.654% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.707, 100.000% |
Path21
Path Summary:
| Slack | 1.290 |
| Data Arrival Time | 6.548 |
| Data Required Time | 7.838 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_14_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.685 | 1.685 | tNET | RR | 1 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/CLK |
| 1.950 | 0.265 | tC2Q | RF | 128 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q |
| 4.423 | 2.473 | tNET | FF | 1 | R33C142[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n975_s6/I2 |
| 4.788 | 0.365 | tINS | FR | 2 | R33C142[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n975_s6/F |
| 5.065 | 0.276 | tNET | RR | 1 | R32C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n766_s3/I1 |
| 5.481 | 0.417 | tINS | RR | 4 | R32C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n766_s3/F |
| 6.183 | 0.701 | tNET | RR | 1 | R25C137[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n758_s3/I0 |
| 6.548 | 0.365 | tINS | RR | 1 | R25C137[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n758_s3/F |
| 6.548 | 0.000 | tNET | RR | 1 | R25C137[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_14_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.883 | 1.710 | tNET | RR | 1 | R25C137[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_14_s0/CLK |
| 7.838 | -0.046 | tSu | 1 | R25C137[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_14_s0 |
Path Statistics:
| Clock Skew | 0.025 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.685, 100.000% |
| Arrival Data Path Delay | cell: 1.147, 23.598%; route: 3.451, 70.961%; tC2Q: 0.265, 5.441% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.710, 100.000% |
Path22
Path Summary:
| Slack | 1.322 |
| Data Arrival Time | 6.516 |
| Data Required Time | 7.838 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_59_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.690 | 1.690 | tNET | RR | 1 | R47C127[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/CLK |
| 1.965 | 0.275 | tC2Q | RR | 54 | R47C127[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q |
| 3.126 | 1.161 | tNET | RR | 1 | R50C120[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3168_s17/I0 |
| 3.543 | 0.417 | tINS | RR | 3 | R50C120[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3168_s17/F |
| 3.971 | 0.428 | tNET | RR | 1 | R49C123[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3137_s15/I0 |
| 4.337 | 0.365 | tINS | RR | 5 | R49C123[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3137_s15/F |
| 4.899 | 0.562 | tNET | RR | 1 | R47C125[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s15/I1 |
| 5.316 | 0.417 | tINS | RR | 1 | R47C125[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s15/F |
| 5.318 | 0.002 | tNET | RR | 1 | R47C125[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s16/I3 |
| 5.726 | 0.409 | tINS | RR | 5 | R47C125[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s16/F |
| 6.099 | 0.373 | tNET | RR | 1 | R43C125[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3115_s10/I2 |
| 6.516 | 0.417 | tINS | RR | 1 | R43C125[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3115_s10/F |
| 6.516 | 0.000 | tNET | RR | 1 | R43C125[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_59_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.883 | 1.710 | tNET | RR | 1 | R43C125[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_59_s0/CLK |
| 7.838 | -0.046 | tSu | 1 | R43C125[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_59_s0 |
Path Statistics:
| Clock Skew | 0.021 |
| Setup Relationship | 6.173 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.690, 100.000% |
| Arrival Data Path Delay | cell: 2.024, 41.943%; route: 2.526, 52.350%; tC2Q: 0.275, 5.707% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.710, 100.000% |
Path23
Path Summary:
| Slack | 1.322 |
| Data Arrival Time | 6.516 |
| Data Required Time | 7.838 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_60_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.690 | 1.690 | tNET | RR | 1 | R47C127[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/CLK |
| 1.965 | 0.275 | tC2Q | RR | 54 | R47C127[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q |
| 3.126 | 1.161 | tNET | RR | 1 | R50C120[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3168_s17/I0 |
| 3.543 | 0.417 | tINS | RR | 3 | R50C120[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3168_s17/F |
| 3.971 | 0.428 | tNET | RR | 1 | R49C123[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3137_s15/I0 |
| 4.337 | 0.365 | tINS | RR | 5 | R49C123[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3137_s15/F |
| 4.899 | 0.562 | tNET | RR | 1 | R47C125[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s15/I1 |
| 5.316 | 0.417 | tINS | RR | 1 | R47C125[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s15/F |
| 5.318 | 0.002 | tNET | RR | 1 | R47C125[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s16/I3 |
| 5.726 | 0.409 | tINS | RR | 5 | R47C125[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s16/F |
| 6.099 | 0.373 | tNET | RR | 1 | R43C125[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3114_s10/I2 |
| 6.516 | 0.417 | tINS | RR | 1 | R43C125[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3114_s10/F |
| 6.516 | 0.000 | tNET | RR | 1 | R43C125[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_60_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.883 | 1.710 | tNET | RR | 1 | R43C125[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_60_s0/CLK |
| 7.838 | -0.046 | tSu | 1 | R43C125[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_60_s0 |
Path Statistics:
| Clock Skew | 0.021 |
| Setup Relationship | 6.173 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.690, 100.000% |
| Arrival Data Path Delay | cell: 2.024, 41.943%; route: 2.526, 52.350%; tC2Q: 0.275, 5.707% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.710, 100.000% |
Path24
Path Summary:
| Slack | 1.324 |
| Data Arrival Time | 6.483 |
| Data Required Time | 7.807 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_2_s1 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_13_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.690 | 1.690 | tNET | RR | 1 | R47C127[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_2_s1/CLK |
| 1.954 | 0.265 | tC2Q | RF | 30 | R47C127[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_2_s1/Q |
| 3.291 | 1.337 | tNET | FF | 1 | R42C120[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3150_s16/I1 |
| 3.656 | 0.365 | tINS | FR | 13 | R42C120[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3150_s16/F |
| 4.325 | 0.669 | tNET | RR | 1 | R50C122[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3159_s13/I3 |
| 4.719 | 0.394 | tINS | RR | 5 | R50C122[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3159_s13/F |
| 5.339 | 0.620 | tNET | RR | 1 | R41C123[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3161_s12/I3 |
| 5.547 | 0.208 | tINS | RR | 1 | R41C123[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3161_s12/F |
| 6.066 | 0.519 | tNET | RR | 1 | R50C122[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3161_s10/I2 |
| 6.483 | 0.417 | tINS | RR | 1 | R50C122[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3161_s10/F |
| 6.483 | 0.000 | tNET | RR | 1 | R50C122[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_13_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.853 | 1.680 | tNET | RR | 1 | R50C122[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_13_s0/CLK |
| 7.807 | -0.046 | tSu | 1 | R50C122[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_13_s0 |
Path Statistics:
| Clock Skew | -0.010 |
| Setup Relationship | 6.173 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.690, 100.000% |
| Arrival Data Path Delay | cell: 1.384, 28.877%; route: 3.145, 65.603%; tC2Q: 0.265, 5.520% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.680, 100.000% |
Path25
Path Summary:
| Slack | 1.325 |
| Data Arrival Time | 6.500 |
| Data Required Time | 7.826 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_10_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.685 | 1.685 | tNET | RR | 1 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/CLK |
| 1.950 | 0.265 | tC2Q | RF | 128 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q |
| 4.423 | 2.473 | tNET | FF | 1 | R33C142[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n975_s7/I2 |
| 4.752 | 0.329 | tINS | FR | 2 | R33C142[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n975_s7/F |
| 4.905 | 0.154 | tNET | RR | 1 | R33C140[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n973_s3/I0 |
| 5.300 | 0.394 | tINS | RR | 5 | R33C140[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n973_s3/F |
| 6.084 | 0.784 | tNET | RR | 1 | R26C138[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n762_s3/I1 |
| 6.500 | 0.417 | tINS | RR | 1 | R26C138[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n762_s3/F |
| 6.500 | 0.000 | tNET | RR | 1 | R26C138[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_10_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.872 | 1.699 | tNET | RR | 1 | R26C138[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_10_s0/CLK |
| 7.826 | -0.046 | tSu | 1 | R26C138[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_10_s0 |
Path Statistics:
| Clock Skew | 0.013 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.685, 100.000% |
| Arrival Data Path Delay | cell: 1.139, 23.664%; route: 3.411, 70.841%; tC2Q: 0.265, 5.495% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.699, 100.000% |
Path26
Path Summary:
| Slack | 1.330 |
| Data Arrival Time | 6.507 |
| Data Required Time | 7.838 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_63_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.690 | 1.690 | tNET | RR | 1 | R47C127[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/CLK |
| 1.965 | 0.275 | tC2Q | RR | 54 | R47C127[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q |
| 3.126 | 1.161 | tNET | RR | 1 | R50C120[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3168_s17/I0 |
| 3.543 | 0.417 | tINS | RR | 3 | R50C120[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3168_s17/F |
| 3.971 | 0.428 | tNET | RR | 1 | R49C123[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3137_s15/I0 |
| 4.337 | 0.365 | tINS | RR | 5 | R49C123[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3137_s15/F |
| 4.899 | 0.562 | tNET | RR | 1 | R47C125[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s15/I1 |
| 5.316 | 0.417 | tINS | RR | 1 | R47C125[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s15/F |
| 5.318 | 0.002 | tNET | RR | 1 | R47C125[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s16/I3 |
| 5.726 | 0.409 | tINS | RR | 5 | R47C125[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s16/F |
| 6.099 | 0.373 | tNET | RR | 1 | R43C125[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s10/I2 |
| 6.507 | 0.409 | tINS | RR | 1 | R43C125[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s10/F |
| 6.507 | 0.000 | tNET | RR | 1 | R43C125[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_63_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.883 | 1.710 | tNET | RR | 1 | R43C125[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_63_s0/CLK |
| 7.838 | -0.046 | tSu | 1 | R43C125[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_63_s0 |
Path Statistics:
| Clock Skew | 0.021 |
| Setup Relationship | 6.173 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.690, 100.000% |
| Arrival Data Path Delay | cell: 2.016, 41.846%; route: 2.526, 52.438%; tC2Q: 0.275, 5.716% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.710, 100.000% |
Path27
Path Summary:
| Slack | 1.366 |
| Data Arrival Time | 6.471 |
| Data Required Time | 7.838 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d2_14_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.685 | 1.685 | tNET | RR | 1 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/CLK |
| 1.950 | 0.265 | tC2Q | RF | 128 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q |
| 4.097 | 2.147 | tNET | FF | 1 | R33C139[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n971_s6/I2 |
| 4.463 | 0.365 | tINS | FR | 2 | R33C139[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n971_s6/F |
| 4.466 | 0.004 | tNET | RR | 1 | R33C139[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n969_s4/I0 |
| 4.875 | 0.409 | tINS | RR | 6 | R33C139[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n969_s4/F |
| 6.106 | 1.231 | tNET | RR | 1 | R25C137[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n961_s3/I0 |
| 6.471 | 0.365 | tINS | RR | 1 | R25C137[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n961_s3/F |
| 6.471 | 0.000 | tNET | RR | 1 | R25C137[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d2_14_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.883 | 1.710 | tNET | RR | 1 | R25C137[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d2_14_s0/CLK |
| 7.838 | -0.046 | tSu | 1 | R25C137[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d2_14_s0 |
Path Statistics:
| Clock Skew | 0.025 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.685, 100.000% |
| Arrival Data Path Delay | cell: 1.139, 23.806%; route: 3.382, 70.666%; tC2Q: 0.265, 5.528% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.710, 100.000% |
Path28
Path Summary:
| Slack | 1.379 |
| Data Arrival Time | 6.426 |
| Data Required Time | 7.805 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_2_s1 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_30_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.690 | 1.690 | tNET | RR | 1 | R47C127[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_2_s1/CLK |
| 1.954 | 0.265 | tC2Q | RF | 30 | R47C127[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_2_s1/Q |
| 3.291 | 1.337 | tNET | FF | 1 | R42C120[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3150_s16/I1 |
| 3.656 | 0.365 | tINS | FR | 13 | R42C120[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3150_s16/F |
| 4.473 | 0.817 | tNET | RR | 1 | R48C125[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s16/I2 |
| 4.802 | 0.329 | tINS | RR | 5 | R48C125[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s16/F |
| 5.334 | 0.532 | tNET | RR | 1 | R48C120[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3144_s11/I2 |
| 5.742 | 0.409 | tINS | RR | 1 | R48C120[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3144_s11/F |
| 6.017 | 0.275 | tNET | RR | 1 | R48C123[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3144_s10/I2 |
| 6.426 | 0.409 | tINS | RR | 1 | R48C123[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3144_s10/F |
| 6.426 | 0.000 | tNET | RR | 1 | R48C123[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_30_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.851 | 1.678 | tNET | RR | 1 | R48C123[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_30_s0/CLK |
| 7.805 | -0.046 | tSu | 1 | R48C123[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_30_s0 |
Path Statistics:
| Clock Skew | -0.012 |
| Setup Relationship | 6.173 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.690, 100.000% |
| Arrival Data Path Delay | cell: 1.511, 31.908%; route: 2.960, 62.505%; tC2Q: 0.265, 5.587% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.678, 100.000% |
Path29
Path Summary:
| Slack | 1.387 |
| Data Arrival Time | 6.457 |
| Data Required Time | 7.844 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/c_state_0_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_0_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.712 | 1.712 | tNET | RR | 1 | R26C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/c_state_0_s0/CLK |
| 1.987 | 0.275 | tC2Q | RR | 80 | R26C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/c_state_0_s0/Q |
| 2.283 | 0.295 | tNET | RR | 1 | R25C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/locked_s79/I1 |
| 2.691 | 0.409 | tINS | RR | 2885 | R25C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/locked_s79/F |
| 5.897 | 3.206 | tNET | RR | 1 | R25C123[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_3_s4/I3 |
| 6.126 | 0.229 | tINS | RF | 5 | R25C123[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_3_s4/F |
| 6.250 | 0.123 | tNET | FF | 1 | R25C124[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/n462_s2/I1 |
| 6.457 | 0.208 | tINS | FR | 1 | R25C124[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/n462_s2/F |
| 6.457 | 0.000 | tNET | RR | 1 | R25C124[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_0_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.890 | 1.717 | tNET | RR | 1 | R25C124[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_0_s0/CLK |
| 7.844 | -0.046 | tSu | 1 | R25C124[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_0_s0 |
Path Statistics:
| Clock Skew | 0.005 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.712, 100.000% |
| Arrival Data Path Delay | cell: 0.846, 17.828%; route: 3.624, 76.369%; tC2Q: 0.275, 5.803% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.717, 100.000% |
Path30
Path Summary:
| Slack | 1.387 |
| Data Arrival Time | 6.457 |
| Data Required Time | 7.844 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/c_state_0_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_1_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.712 | 1.712 | tNET | RR | 1 | R26C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/c_state_0_s0/CLK |
| 1.987 | 0.275 | tC2Q | RR | 80 | R26C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/c_state_0_s0/Q |
| 2.283 | 0.295 | tNET | RR | 1 | R25C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/locked_s79/I1 |
| 2.691 | 0.409 | tINS | RR | 2885 | R25C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/locked_s79/F |
| 5.897 | 3.206 | tNET | RR | 1 | R25C123[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_3_s4/I3 |
| 6.126 | 0.229 | tINS | RF | 5 | R25C123[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_3_s4/F |
| 6.250 | 0.123 | tNET | FF | 1 | R25C124[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/n461_s2/I2 |
| 6.457 | 0.208 | tINS | FR | 1 | R25C124[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/n461_s2/F |
| 6.457 | 0.000 | tNET | RR | 1 | R25C124[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_1_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.890 | 1.717 | tNET | RR | 1 | R25C124[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_1_s0/CLK |
| 7.844 | -0.046 | tSu | 1 | R25C124[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_sync_header_lock/err_cnt_1_s0 |
Path Statistics:
| Clock Skew | 0.005 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.712, 100.000% |
| Arrival Data Path Delay | cell: 0.846, 17.828%; route: 3.624, 76.369%; tC2Q: 0.275, 5.803% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.717, 100.000% |
Path31
Path Summary:
| Slack | 1.388 |
| Data Arrival Time | 6.417 |
| Data Required Time | 7.805 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_36_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.685 | 1.685 | tNET | RR | 1 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/CLK |
| 1.950 | 0.265 | tC2Q | RF | 128 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q |
| 4.272 | 2.322 | tNET | FF | 1 | R33C141[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n971_s5/I2 |
| 4.600 | 0.329 | tINS | FR | 2 | R33C141[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n971_s5/F |
| 4.726 | 0.126 | tNET | RR | 1 | R33C140[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n971_s3/I1 |
| 5.143 | 0.417 | tINS | RR | 5 | R33C140[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n971_s3/F |
| 6.008 | 0.865 | tNET | RR | 1 | R30C137[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n533_s2/I0 |
| 6.417 | 0.409 | tINS | RR | 1 | R30C137[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n533_s2/F |
| 6.417 | 0.000 | tNET | RR | 1 | R30C137[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_36_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.851 | 1.678 | tNET | RR | 1 | R30C137[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_36_s0/CLK |
| 7.805 | -0.046 | tSu | 1 | R30C137[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_36_s0 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.685, 100.000% |
| Arrival Data Path Delay | cell: 1.154, 24.387%; route: 3.313, 70.021%; tC2Q: 0.265, 5.593% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.678, 100.000% |
Path32
Path Summary:
| Slack | 1.397 |
| Data Arrival Time | 6.430 |
| Data Required Time | 7.827 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_24_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.685 | 1.685 | tNET | RR | 1 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/CLK |
| 1.950 | 0.265 | tC2Q | RF | 128 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q |
| 4.423 | 2.473 | tNET | FF | 1 | R33C142[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n975_s6/I2 |
| 4.788 | 0.365 | tINS | FR | 2 | R33C142[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n975_s6/F |
| 4.942 | 0.154 | tNET | RR | 1 | R33C140[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n975_s4/I0 |
| 5.351 | 0.409 | tINS | RR | 5 | R33C140[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n975_s4/F |
| 6.065 | 0.714 | tNET | RR | 1 | R27C137[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n545_s2/I1 |
| 6.430 | 0.365 | tINS | RR | 1 | R27C137[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n545_s2/F |
| 6.430 | 0.000 | tNET | RR | 1 | R27C137[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_24_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.873 | 1.700 | tNET | RR | 1 | R27C137[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_24_s0/CLK |
| 7.827 | -0.046 | tSu | 1 | R27C137[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_24_s0 |
Path Statistics:
| Clock Skew | 0.015 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.685, 100.000% |
| Arrival Data Path Delay | cell: 1.139, 24.014%; route: 3.341, 70.410%; tC2Q: 0.265, 5.577% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
Path33
Path Summary:
| Slack | 1.402 |
| Data Arrival Time | 6.426 |
| Data Required Time | 7.827 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_42_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.685 | 1.685 | tNET | RR | 1 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/CLK |
| 1.950 | 0.265 | tC2Q | RF | 128 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q |
| 4.272 | 2.322 | tNET | FF | 1 | R33C141[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1145_s4/I2 |
| 4.637 | 0.365 | tINS | FR | 2 | R33C141[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1145_s4/F |
| 5.064 | 0.427 | tNET | RR | 1 | R30C140[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1145_s3/I1 |
| 5.293 | 0.229 | tINS | RF | 4 | R30C140[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1145_s3/F |
| 6.060 | 0.767 | tNET | FF | 1 | R27C141[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1137_s3/I0 |
| 6.426 | 0.365 | tINS | FR | 1 | R27C141[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1137_s3/F |
| 6.426 | 0.000 | tNET | RR | 1 | R27C141[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_42_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.873 | 1.700 | tNET | RR | 1 | R27C141[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_42_s0/CLK |
| 7.827 | -0.046 | tSu | 1 | R27C141[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_42_s0 |
Path Statistics:
| Clock Skew | 0.015 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.685, 100.000% |
| Arrival Data Path Delay | cell: 0.960, 20.258%; route: 3.515, 74.160%; tC2Q: 0.265, 5.582% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
Path34
Path Summary:
| Slack | 1.405 |
| Data Arrival Time | 6.418 |
| Data Required Time | 7.824 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_20_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.685 | 1.685 | tNET | RR | 1 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/CLK |
| 1.950 | 0.265 | tC2Q | RF | 128 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q |
| 4.272 | 2.322 | tNET | FF | 1 | R33C141[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n971_s5/I2 |
| 4.600 | 0.329 | tINS | FR | 2 | R33C141[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n971_s5/F |
| 4.726 | 0.126 | tNET | RR | 1 | R33C140[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n971_s3/I1 |
| 5.143 | 0.417 | tINS | RR | 5 | R33C140[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n971_s3/F |
| 6.010 | 0.867 | tNET | RR | 1 | R29C136[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n752_s2/I0 |
| 6.418 | 0.409 | tINS | RR | 1 | R29C136[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n752_s2/F |
| 6.418 | 0.000 | tNET | RR | 1 | R29C136[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_20_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.869 | 1.696 | tNET | RR | 1 | R29C136[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_20_s0/CLK |
| 7.824 | -0.046 | tSu | 1 | R29C136[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_20_s0 |
Path Statistics:
| Clock Skew | 0.011 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.685, 100.000% |
| Arrival Data Path Delay | cell: 1.154, 24.377%; route: 3.315, 70.032%; tC2Q: 0.265, 5.590% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.696, 100.000% |
Path35
Path Summary:
| Slack | 1.408 |
| Data Arrival Time | 6.430 |
| Data Required Time | 7.838 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_47_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.690 | 1.690 | tNET | RR | 1 | R47C127[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/CLK |
| 1.965 | 0.275 | tC2Q | RR | 54 | R47C127[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q |
| 3.126 | 1.161 | tNET | RR | 1 | R50C120[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3168_s17/I0 |
| 3.543 | 0.417 | tINS | RR | 3 | R50C120[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3168_s17/F |
| 3.971 | 0.428 | tNET | RR | 1 | R49C123[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3137_s15/I0 |
| 4.337 | 0.365 | tINS | RR | 5 | R49C123[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3137_s15/F |
| 5.094 | 0.757 | tNET | RR | 1 | R44C123[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3127_s14/I0 |
| 5.502 | 0.409 | tINS | RR | 5 | R44C123[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3127_s14/F |
| 5.780 | 0.278 | tNET | RR | 1 | R43C125[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3127_s11/I3 |
| 6.010 | 0.229 | tINS | RF | 1 | R43C125[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3127_s11/F |
| 6.013 | 0.004 | tNET | FF | 1 | R43C125[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3127_s10/I2 |
| 6.430 | 0.417 | tINS | FR | 1 | R43C125[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3127_s10/F |
| 6.430 | 0.000 | tNET | RR | 1 | R43C125[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_47_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.883 | 1.710 | tNET | RR | 1 | R43C125[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_47_s0/CLK |
| 7.838 | -0.046 | tSu | 1 | R43C125[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_47_s0 |
Path Statistics:
| Clock Skew | 0.021 |
| Setup Relationship | 6.173 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.690, 100.000% |
| Arrival Data Path Delay | cell: 1.837, 38.751%; route: 2.628, 55.440%; tC2Q: 0.275, 5.810% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.710, 100.000% |
Path36
Path Summary:
| Slack | 1.450 |
| Data Arrival Time | 6.373 |
| Data Required Time | 7.824 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_2_s1 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_31_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.690 | 1.690 | tNET | RR | 1 | R47C127[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_2_s1/CLK |
| 1.954 | 0.265 | tC2Q | RF | 30 | R47C127[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_2_s1/Q |
| 3.291 | 1.337 | tNET | FF | 1 | R42C120[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3150_s16/I1 |
| 3.656 | 0.365 | tINS | FR | 13 | R42C120[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3150_s16/F |
| 4.473 | 0.817 | tNET | RR | 1 | R48C125[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s16/I2 |
| 4.802 | 0.329 | tINS | RR | 5 | R48C125[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s16/F |
| 5.593 | 0.791 | tNET | RR | 1 | R47C120[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s12/I2 |
| 6.006 | 0.413 | tINS | RR | 1 | R47C120[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s12/F |
| 6.008 | 0.002 | tNET | RR | 1 | R47C120[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s10/I2 |
| 6.373 | 0.365 | tINS | RR | 1 | R47C120[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s10/F |
| 6.373 | 0.000 | tNET | RR | 1 | R47C120[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_31_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.869 | 1.696 | tNET | RR | 1 | R47C120[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_31_s0/CLK |
| 7.824 | -0.046 | tSu | 1 | R47C120[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_31_s0 |
Path Statistics:
| Clock Skew | 0.007 |
| Setup Relationship | 6.173 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.690, 100.000% |
| Arrival Data Path Delay | cell: 1.472, 31.437%; route: 2.947, 62.913%; tC2Q: 0.265, 5.649% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.696, 100.000% |
Path37
Path Summary:
| Slack | 1.461 |
| Data Arrival Time | 6.363 |
| Data Required Time | 7.824 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_44_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.685 | 1.685 | tNET | RR | 1 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/CLK |
| 1.950 | 0.265 | tC2Q | RF | 128 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q |
| 4.097 | 2.147 | tNET | FF | 1 | R33C139[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n971_s6/I2 |
| 4.463 | 0.365 | tINS | FR | 2 | R33C139[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n971_s6/F |
| 4.466 | 0.004 | tNET | RR | 1 | R33C139[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n971_s4/I1 |
| 4.879 | 0.413 | tINS | RR | 6 | R33C139[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n971_s4/F |
| 5.997 | 1.118 | tNET | RR | 1 | R29C140[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n525_s2/I0 |
| 6.363 | 0.365 | tINS | RR | 1 | R29C140[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n525_s2/F |
| 6.363 | 0.000 | tNET | RR | 1 | R29C140[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_44_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.869 | 1.696 | tNET | RR | 1 | R29C140[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_44_s0/CLK |
| 7.824 | -0.046 | tSu | 1 | R29C140[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_44_s0 |
Path Statistics:
| Clock Skew | 0.011 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.685, 100.000% |
| Arrival Data Path Delay | cell: 1.144, 24.456%; route: 3.269, 69.886%; tC2Q: 0.265, 5.657% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.696, 100.000% |
Path38
Path Summary:
| Slack | 1.515 |
| Data Arrival Time | 6.312 |
| Data Required Time | 7.827 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_28_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.685 | 1.685 | tNET | RR | 1 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/CLK |
| 1.950 | 0.265 | tC2Q | RF | 128 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q |
| 4.272 | 2.322 | tNET | FF | 1 | R33C141[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n971_s5/I2 |
| 4.600 | 0.329 | tINS | FR | 2 | R33C141[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n971_s5/F |
| 4.726 | 0.126 | tNET | RR | 1 | R33C140[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n971_s3/I1 |
| 5.143 | 0.417 | tINS | RR | 5 | R33C140[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n971_s3/F |
| 5.947 | 0.804 | tNET | RR | 1 | R27C137[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n541_s2/I1 |
| 6.312 | 0.365 | tINS | RR | 1 | R27C137[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n541_s2/F |
| 6.312 | 0.000 | tNET | RR | 1 | R27C137[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_28_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.873 | 1.700 | tNET | RR | 1 | R27C137[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_28_s0/CLK |
| 7.827 | -0.046 | tSu | 1 | R27C137[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_28_s0 |
Path Statistics:
| Clock Skew | 0.015 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.685, 100.000% |
| Arrival Data Path Delay | cell: 1.111, 24.003%; route: 3.252, 70.278%; tC2Q: 0.265, 5.719% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
Path39
Path Summary:
| Slack | 1.525 |
| Data Arrival Time | 6.299 |
| Data Required Time | 7.824 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_2_s1 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_27_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.690 | 1.690 | tNET | RR | 1 | R47C127[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_2_s1/CLK |
| 1.954 | 0.265 | tC2Q | RF | 30 | R47C127[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_2_s1/Q |
| 3.291 | 1.337 | tNET | FF | 1 | R42C120[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3150_s16/I1 |
| 3.656 | 0.365 | tINS | FR | 13 | R42C120[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3150_s16/F |
| 4.473 | 0.817 | tNET | RR | 1 | R48C125[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s16/I2 |
| 4.802 | 0.329 | tINS | RR | 5 | R48C125[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s16/F |
| 5.486 | 0.684 | tNET | RR | 1 | R47C120[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3147_s11/I2 |
| 5.880 | 0.394 | tINS | RR | 1 | R47C120[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3147_s11/F |
| 5.882 | 0.002 | tNET | RR | 1 | R47C120[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3147_s10/I2 |
| 6.299 | 0.417 | tINS | RR | 1 | R47C120[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3147_s10/F |
| 6.299 | 0.000 | tNET | RR | 1 | R47C120[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_27_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.869 | 1.696 | tNET | RR | 1 | R47C120[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_27_s0/CLK |
| 7.824 | -0.046 | tSu | 1 | R47C120[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_27_s0 |
Path Statistics:
| Clock Skew | 0.007 |
| Setup Relationship | 6.173 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.690, 100.000% |
| Arrival Data Path Delay | cell: 1.505, 32.650%; route: 2.840, 61.609%; tC2Q: 0.265, 5.741% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.696, 100.000% |
Path40
Path Summary:
| Slack | 1.540 |
| Data Arrival Time | 6.294 |
| Data Required Time | 7.834 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_53_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.690 | 1.690 | tNET | RR | 1 | R47C127[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/CLK |
| 1.965 | 0.275 | tC2Q | RR | 54 | R47C127[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q |
| 3.126 | 1.161 | tNET | RR | 1 | R50C120[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3168_s17/I0 |
| 3.543 | 0.417 | tINS | RR | 3 | R50C120[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3168_s17/F |
| 3.971 | 0.428 | tNET | RR | 1 | R49C123[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3137_s15/I0 |
| 4.337 | 0.365 | tINS | RR | 5 | R49C123[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3137_s15/F |
| 4.836 | 0.499 | tNET | RR | 1 | R43C125[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3119_s14/I0 |
| 5.249 | 0.413 | tINS | RR | 5 | R43C125[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3119_s14/F |
| 5.676 | 0.427 | tNET | RR | 1 | R45C124[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3121_s11/I3 |
| 6.084 | 0.409 | tINS | RR | 1 | R45C124[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3121_s11/F |
| 6.086 | 0.002 | tNET | RR | 1 | R45C124[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3121_s10/I2 |
| 6.294 | 0.208 | tINS | RR | 1 | R45C124[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3121_s10/F |
| 6.294 | 0.000 | tNET | RR | 1 | R45C124[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_53_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.880 | 1.707 | tNET | RR | 1 | R45C124[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_53_s0/CLK |
| 7.834 | -0.046 | tSu | 1 | R45C124[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_53_s0 |
Path Statistics:
| Clock Skew | 0.017 |
| Setup Relationship | 6.173 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.690, 100.000% |
| Arrival Data Path Delay | cell: 1.812, 39.347%; route: 2.517, 54.672%; tC2Q: 0.275, 5.981% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.707, 100.000% |
Path41
Path Summary:
| Slack | 1.548 |
| Data Arrival Time | 6.293 |
| Data Required Time | 7.841 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_11_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.690 | 1.690 | tNET | RR | 1 | R47C127[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/CLK |
| 1.965 | 0.275 | tC2Q | RR | 54 | R47C127[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q |
| 3.126 | 1.161 | tNET | RR | 1 | R50C120[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3168_s17/I0 |
| 3.543 | 0.417 | tINS | RR | 3 | R50C120[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3168_s17/F |
| 4.064 | 0.521 | tNET | RR | 1 | R49C125[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s17/I3 |
| 4.473 | 0.409 | tINS | RR | 4 | R49C125[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s17/F |
| 4.899 | 0.427 | tNET | RR | 1 | R50C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3159_s12/I0 |
| 5.308 | 0.409 | tINS | RR | 5 | R50C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3159_s12/F |
| 5.928 | 0.620 | tNET | RR | 1 | R41C123[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3163_s10/I3 |
| 6.293 | 0.365 | tINS | RR | 1 | R41C123[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3163_s10/F |
| 6.293 | 0.000 | tNET | RR | 1 | R41C123[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_11_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.887 | 1.714 | tNET | RR | 1 | R41C123[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_11_s0/CLK |
| 7.841 | -0.046 | tSu | 1 | R41C123[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_11_s0 |
Path Statistics:
| Clock Skew | 0.024 |
| Setup Relationship | 6.173 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.690, 100.000% |
| Arrival Data Path Delay | cell: 1.599, 34.741%; route: 2.729, 59.277%; tC2Q: 0.275, 5.982% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.714, 100.000% |
Path42
Path Summary:
| Slack | 1.556 |
| Data Arrival Time | 6.267 |
| Data Required Time | 7.824 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_62_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.690 | 1.690 | tNET | RR | 1 | R47C127[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/CLK |
| 1.965 | 0.275 | tC2Q | RR | 54 | R47C127[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q |
| 3.126 | 1.161 | tNET | RR | 1 | R50C120[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3168_s17/I0 |
| 3.543 | 0.417 | tINS | RR | 3 | R50C120[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3168_s17/F |
| 3.971 | 0.428 | tNET | RR | 1 | R49C123[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3137_s15/I0 |
| 4.337 | 0.365 | tINS | RR | 5 | R49C123[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3137_s15/F |
| 4.899 | 0.562 | tNET | RR | 1 | R47C125[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s15/I1 |
| 5.316 | 0.417 | tINS | RR | 1 | R47C125[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s15/F |
| 5.318 | 0.002 | tNET | RR | 1 | R47C125[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s16/I3 |
| 5.726 | 0.409 | tINS | RR | 5 | R47C125[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s16/F |
| 5.854 | 0.128 | tNET | RR | 1 | R47C124[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3112_s10/I2 |
| 6.267 | 0.413 | tINS | RR | 1 | R47C124[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3112_s10/F |
| 6.267 | 0.000 | tNET | RR | 1 | R47C124[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_62_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.869 | 1.696 | tNET | RR | 1 | R47C124[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_62_s0/CLK |
| 7.824 | -0.046 | tSu | 1 | R47C124[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_62_s0 |
Path Statistics:
| Clock Skew | 0.007 |
| Setup Relationship | 6.173 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.690, 100.000% |
| Arrival Data Path Delay | cell: 2.020, 44.141%; route: 2.282, 49.843%; tC2Q: 0.275, 6.017% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.696, 100.000% |
Path43
Path Summary:
| Slack | 1.561 |
| Data Arrival Time | 6.263 |
| Data Required Time | 7.824 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_61_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.690 | 1.690 | tNET | RR | 1 | R47C127[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/CLK |
| 1.965 | 0.275 | tC2Q | RR | 54 | R47C127[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q |
| 3.126 | 1.161 | tNET | RR | 1 | R50C120[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3168_s17/I0 |
| 3.543 | 0.417 | tINS | RR | 3 | R50C120[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3168_s17/F |
| 3.971 | 0.428 | tNET | RR | 1 | R49C123[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3137_s15/I0 |
| 4.337 | 0.365 | tINS | RR | 5 | R49C123[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3137_s15/F |
| 4.899 | 0.562 | tNET | RR | 1 | R47C125[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s15/I1 |
| 5.316 | 0.417 | tINS | RR | 1 | R47C125[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s15/F |
| 5.318 | 0.002 | tNET | RR | 1 | R47C125[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s16/I3 |
| 5.726 | 0.409 | tINS | RR | 5 | R47C125[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3111_s16/F |
| 5.854 | 0.128 | tNET | RR | 1 | R47C124[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3113_s10/I2 |
| 6.263 | 0.409 | tINS | RR | 1 | R47C124[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3113_s10/F |
| 6.263 | 0.000 | tNET | RR | 1 | R47C124[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_61_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.869 | 1.696 | tNET | RR | 1 | R47C124[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_61_s0/CLK |
| 7.824 | -0.046 | tSu | 1 | R47C124[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_61_s0 |
Path Statistics:
| Clock Skew | 0.007 |
| Setup Relationship | 6.173 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.690, 100.000% |
| Arrival Data Path Delay | cell: 2.016, 44.086%; route: 2.282, 49.892%; tC2Q: 0.275, 6.022% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.696, 100.000% |
Path44
Path Summary:
| Slack | 1.582 |
| Data Arrival Time | 6.223 |
| Data Required Time | 7.805 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_36_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.685 | 1.685 | tNET | RR | 1 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/CLK |
| 1.950 | 0.265 | tC2Q | RF | 128 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q |
| 4.272 | 2.322 | tNET | FF | 1 | R33C141[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1145_s4/I2 |
| 4.637 | 0.365 | tINS | FR | 2 | R33C141[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1145_s4/F |
| 5.171 | 0.534 | tNET | RR | 1 | R30C140[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1143_s3/I0 |
| 5.580 | 0.409 | tINS | RR | 4 | R30C140[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1143_s3/F |
| 5.858 | 0.278 | tNET | RR | 1 | R30C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1143_s5/I1 |
| 6.223 | 0.365 | tINS | RR | 1 | R30C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1143_s5/F |
| 6.223 | 0.000 | tNET | RR | 1 | R30C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_36_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.851 | 1.678 | tNET | RR | 1 | R30C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_36_s0/CLK |
| 7.805 | -0.046 | tSu | 1 | R30C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_36_s0 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.685, 100.000% |
| Arrival Data Path Delay | cell: 1.139, 25.109%; route: 3.134, 69.060%; tC2Q: 0.265, 5.831% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.678, 100.000% |
Path45
Path Summary:
| Slack | 1.597 |
| Data Arrival Time | 6.247 |
| Data Required Time | 7.844 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_22_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.685 | 1.685 | tNET | RR | 1 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/CLK |
| 1.950 | 0.265 | tC2Q | RF | 128 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q |
| 4.097 | 2.147 | tNET | FF | 1 | R33C139[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n971_s6/I2 |
| 4.463 | 0.365 | tINS | FR | 2 | R33C139[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n971_s6/F |
| 4.466 | 0.004 | tNET | RR | 1 | R33C139[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n969_s4/I0 |
| 4.875 | 0.409 | tINS | RR | 6 | R33C139[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n969_s4/F |
| 5.831 | 0.956 | tNET | RR | 1 | R25C136[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n750_s2/I1 |
| 6.247 | 0.417 | tINS | RR | 1 | R25C136[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n750_s2/F |
| 6.247 | 0.000 | tNET | RR | 1 | R25C136[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_22_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.890 | 1.717 | tNET | RR | 1 | R25C136[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_22_s0/CLK |
| 7.844 | -0.046 | tSu | 1 | R25C136[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_22_s0 |
Path Statistics:
| Clock Skew | 0.032 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.685, 100.000% |
| Arrival Data Path Delay | cell: 1.191, 26.100%; route: 3.107, 68.100%; tC2Q: 0.265, 5.800% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.717, 100.000% |
Path46
Path Summary:
| Slack | 1.597 |
| Data Arrival Time | 6.242 |
| Data Required Time | 7.839 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_32_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.685 | 1.685 | tNET | RR | 1 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/CLK |
| 1.950 | 0.265 | tC2Q | RF | 128 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q |
| 4.091 | 2.141 | tNET | FF | 1 | R32C140[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1147_s4/I2 |
| 4.320 | 0.229 | tINS | FF | 2 | R32C140[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1147_s4/F |
| 4.581 | 0.261 | tNET | FF | 1 | R33C139[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1147_s3/I1 |
| 4.990 | 0.409 | tINS | FR | 5 | R33C139[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1147_s3/F |
| 5.877 | 0.887 | tNET | RR | 1 | R26C136[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1147_s5/I1 |
| 6.242 | 0.365 | tINS | RR | 1 | R26C136[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n1147_s5/F |
| 6.242 | 0.000 | tNET | RR | 1 | R26C136[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_32_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.885 | 1.712 | tNET | RR | 1 | R26C136[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_32_s0/CLK |
| 7.839 | -0.046 | tSu | 1 | R26C136[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d3_32_s0 |
Path Statistics:
| Clock Skew | 0.027 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.685, 100.000% |
| Arrival Data Path Delay | cell: 1.003, 22.023%; route: 3.289, 72.171%; tC2Q: 0.265, 5.807% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.712, 100.000% |
Path47
Path Summary:
| Slack | 1.612 |
| Data Arrival Time | 6.229 |
| Data Required Time | 7.841 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_12_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.690 | 1.690 | tNET | RR | 1 | R47C127[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/CLK |
| 1.965 | 0.275 | tC2Q | RR | 54 | R47C127[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q |
| 3.126 | 1.161 | tNET | RR | 1 | R50C120[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3168_s17/I0 |
| 3.543 | 0.417 | tINS | RR | 3 | R50C120[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3168_s17/F |
| 4.064 | 0.521 | tNET | RR | 1 | R49C125[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s17/I3 |
| 4.473 | 0.409 | tINS | RR | 4 | R49C125[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s17/F |
| 4.899 | 0.427 | tNET | RR | 1 | R50C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3159_s12/I0 |
| 5.308 | 0.409 | tINS | RR | 5 | R50C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3159_s12/F |
| 5.821 | 0.513 | tNET | RR | 1 | R41C123[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3162_s10/I3 |
| 6.229 | 0.409 | tINS | RR | 1 | R41C123[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3162_s10/F |
| 6.229 | 0.000 | tNET | RR | 1 | R41C123[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_12_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.887 | 1.714 | tNET | RR | 1 | R41C123[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_12_s0/CLK |
| 7.841 | -0.046 | tSu | 1 | R41C123[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_12_s0 |
Path Statistics:
| Clock Skew | 0.024 |
| Setup Relationship | 6.173 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.690, 100.000% |
| Arrival Data Path Delay | cell: 1.642, 36.182%; route: 2.622, 57.752%; tC2Q: 0.275, 6.067% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.714, 100.000% |
Path48
Path Summary:
| Slack | 1.612 |
| Data Arrival Time | 6.229 |
| Data Required Time | 7.841 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_14_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.690 | 1.690 | tNET | RR | 1 | R47C127[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/CLK |
| 1.965 | 0.275 | tC2Q | RR | 54 | R47C127[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/c_state_1_s1/Q |
| 3.126 | 1.161 | tNET | RR | 1 | R50C120[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3168_s17/I0 |
| 3.543 | 0.417 | tINS | RR | 3 | R50C120[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3168_s17/F |
| 4.064 | 0.521 | tNET | RR | 1 | R49C125[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s17/I3 |
| 4.473 | 0.409 | tINS | RR | 4 | R49C125[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3143_s17/F |
| 4.899 | 0.427 | tNET | RR | 1 | R50C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3159_s12/I0 |
| 5.308 | 0.409 | tINS | RR | 5 | R50C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3159_s12/F |
| 5.821 | 0.513 | tNET | RR | 1 | R41C123[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3160_s10/I3 |
| 6.229 | 0.409 | tINS | RR | 1 | R41C123[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/n3160_s10/F |
| 6.229 | 0.000 | tNET | RR | 1 | R41C123[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_14_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.887 | 1.714 | tNET | RR | 1 | R41C123[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_14_s0/CLK |
| 7.841 | -0.046 | tSu | 1 | R41C123[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/xgmii_rxd_tmp_14_s0 |
Path Statistics:
| Clock Skew | 0.024 |
| Setup Relationship | 6.173 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.690, 100.000% |
| Arrival Data Path Delay | cell: 1.642, 36.182%; route: 2.622, 57.752%; tC2Q: 0.275, 6.067% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.714, 100.000% |
Path49
Path Summary:
| Slack | 1.630 |
| Data Arrival Time | 6.191 |
| Data Required Time | 7.820 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_26_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.685 | 1.685 | tNET | RR | 1 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/CLK |
| 1.950 | 0.265 | tC2Q | RF | 128 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q |
| 4.091 | 2.141 | tNET | FF | 1 | R33C140[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n975_s9/I2 |
| 4.320 | 0.229 | tINS | FF | 2 | R33C140[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n975_s9/F |
| 4.412 | 0.092 | tNET | FF | 1 | R33C140[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n973_s4/I0 |
| 4.821 | 0.409 | tINS | FR | 6 | R33C140[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n973_s4/F |
| 5.825 | 1.004 | tNET | RR | 1 | R27C138[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n746_s2/I0 |
| 6.191 | 0.365 | tINS | RR | 1 | R27C138[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n746_s2/F |
| 6.191 | 0.000 | tNET | RR | 1 | R27C138[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_26_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.866 | 1.693 | tNET | RR | 1 | R27C138[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_26_s0/CLK |
| 7.820 | -0.046 | tSu | 1 | R27C138[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d1_26_s0 |
Path Statistics:
| Clock Skew | 0.008 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.685, 100.000% |
| Arrival Data Path Delay | cell: 1.003, 22.273%; route: 3.237, 71.854%; tC2Q: 0.265, 5.873% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.693, 100.000% |
Path50
Path Summary:
| Slack | 1.631 |
| Data Arrival Time | 6.190 |
| Data Required Time | 7.820 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_26_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 1.685 | 1.685 | tNET | RR | 1 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/CLK |
| 1.950 | 0.265 | tC2Q | RF | 128 | R34C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt_1_s2/Q |
| 4.423 | 2.473 | tNET | FF | 1 | R33C142[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n975_s7/I2 |
| 4.752 | 0.329 | tINS | FR | 2 | R33C142[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n975_s7/F |
| 4.905 | 0.154 | tNET | RR | 1 | R33C140[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n973_s3/I0 |
| 5.300 | 0.394 | tINS | RR | 5 | R33C140[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n973_s3/F |
| 5.824 | 0.525 | tNET | RR | 1 | R27C138[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n543_s2/I1 |
| 6.190 | 0.365 | tINS | RR | 1 | R27C138[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/n543_s2/F |
| 6.190 | 0.000 | tNET | RR | 1 | R27C138[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_26_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_rx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 7.866 | 1.693 | tNET | RR | 1 | R27C138[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_26_s0/CLK |
| 7.820 | -0.046 | tSu | 1 | R27C138[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/dout_d0_26_s0 |
Path Statistics:
| Clock Skew | 0.008 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.685, 100.000% |
| Arrival Data Path Delay | cell: 1.088, 24.156%; route: 3.152, 69.970%; tC2Q: 0.265, 5.874% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.693, 100.000% |
Setup Analysis Report[2]:
Report Command:report_timing -setup -from_clock [get_clocks {serdes_tx_clk}] -to_clock [get_clocks {serdes_tx_clk}] -max_paths 50 -max_common_paths 1
Path1
Path Summary:
| Slack | 1.278 |
| Data Arrival Time | 6.573 |
| Data Required Time | 7.852 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_s198 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.714 | 1.714 | tNET | RR | 1 | R5C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/CLK |
| 1.989 | 0.275 | tC2Q | RR | 358 | R5C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/Q |
| 5.404 | 3.415 | tNET | RR | 1 | R21C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_init_3_s0/I0 |
| 5.821 | 0.417 | tINS | RR | 1 | R21C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_init_3_s0/F |
| 5.823 | 0.002 | tNET | RR | 1 | R21C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_init_s9/I1 |
| 6.239 | 0.417 | tINS | RR | 2 | R21C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_init_s9/F |
| 6.365 | 0.126 | tNET | RR | 1 | R21C138[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_init_s10/I2 |
| 6.573 | 0.208 | tINS | RR | 1 | R21C138[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_init_s10/F |
| 6.573 | 0.000 | tNET | RR | 1 | R21C138[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_s198/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.897 | 1.724 | tNET | RR | 1 | R21C138[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_s198/CLK |
| 7.852 | -0.046 | tSu | 1 | R21C138[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_s198 |
Path Statistics:
| Clock Skew | 0.010 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.714, 100.000% |
| Arrival Data Path Delay | cell: 1.041, 21.430%; route: 3.542, 72.902%; tC2Q: 0.275, 5.668% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.724, 100.000% |
Path2
Path Summary:
| Slack | 1.287 |
| Data Arrival Time | 6.558 |
| Data Required Time | 7.845 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_init_s |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.714 | 1.714 | tNET | RR | 1 | R5C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/CLK |
| 1.989 | 0.275 | tC2Q | RR | 358 | R5C133[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2_s0/Q |
| 5.404 | 3.415 | tNET | RR | 1 | R21C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_init_3_s0/I0 |
| 5.821 | 0.417 | tINS | RR | 1 | R21C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_init_3_s0/F |
| 5.823 | 0.002 | tNET | RR | 1 | R21C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_init_s9/I1 |
| 6.239 | 0.417 | tINS | RR | 2 | R21C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_init_s9/F |
| 6.558 | 0.319 | tNET | RR | 1 | R21C137[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_init_s/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.891 | 1.718 | tNET | RR | 1 | R21C137[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_init_s/CLK |
| 7.845 | -0.046 | tSu | 1 | R21C137[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_regram/regstore[0]_ER_init_s |
Path Statistics:
| Clock Skew | 0.004 |
| Setup Relationship | 6.173 |
| Logic Level | 3 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.714, 100.000% |
| Arrival Data Path Delay | cell: 0.833, 17.205%; route: 3.735, 77.109%; tC2Q: 0.275, 5.686% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.718, 100.000% |
Path3
Path Summary:
| Slack | 1.509 |
| Data Arrival Time | 6.312 |
| Data Required Time | 7.820 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_6_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.287 | 1.322 | tNET | FF | 1 | R23C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1028_s3/I2 |
| 3.495 | 0.208 | tINS | FR | 2 | R23C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1028_s3/F |
| 3.948 | 0.454 | tNET | RR | 1 | R22C127[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1028_s2/I0 |
| 4.361 | 0.413 | tINS | RR | 3 | R22C127[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1028_s2/F |
| 5.903 | 1.542 | tNET | RR | 1 | R17C127[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n838_s2/I1 |
| 6.312 | 0.409 | tINS | RR | 1 | R17C127[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n838_s2/F |
| 6.312 | 0.000 | tNET | RR | 1 | R17C127[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_6_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.866 | 1.693 | tNET | RR | 1 | R17C127[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_6_s0/CLK |
| 7.820 | -0.046 | tSu | 1 | R17C127[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_6_s0 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 1.030, 22.326%; route: 3.317, 71.936%; tC2Q: 0.265, 5.738% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.693, 100.000% |
Path4
Path Summary:
| Slack | 1.678 |
| Data Arrival Time | 6.151 |
| Data Required Time | 7.829 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_53_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.483 | 1.518 | tNET | FF | 1 | R23C132[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n399_s5/I2 |
| 3.691 | 0.208 | tINS | FR | 2 | R23C132[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n399_s5/F |
| 3.995 | 0.304 | tNET | RR | 1 | R22C131[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n397_s3/I1 |
| 4.412 | 0.417 | tINS | RR | 3 | R22C131[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n397_s3/F |
| 5.785 | 1.373 | tNET | RR | 1 | R18C126[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n397_s1/I1 |
| 6.151 | 0.365 | tINS | RR | 1 | R18C126[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n397_s1/F |
| 6.151 | 0.000 | tNET | RR | 1 | R18C126[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_53_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.874 | 1.701 | tNET | RR | 1 | R18C126[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_53_s0/CLK |
| 7.829 | -0.046 | tSu | 1 | R18C126[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_53_s0 |
Path Statistics:
| Clock Skew | 0.001 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 0.990, 22.245%; route: 3.196, 71.810%; tC2Q: 0.265, 5.945% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.701, 100.000% |
Path5
Path Summary:
| Slack | 1.723 |
| Data Arrival Time | 6.103 |
| Data Required Time | 7.826 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_42_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.658 | 1.693 | tNET | FF | 1 | R21C131[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n788_s4/I2 |
| 3.986 | 0.329 | tINS | FR | 2 | R21C131[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n788_s4/F |
| 4.317 | 0.331 | tNET | RR | 1 | R21C128[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n786_s3/I1 |
| 4.734 | 0.417 | tINS | RR | 5 | R21C128[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n786_s3/F |
| 5.694 | 0.960 | tNET | RR | 1 | R16C122[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n605_s2/I0 |
| 6.103 | 0.409 | tINS | RR | 1 | R16C122[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n605_s2/F |
| 6.103 | 0.000 | tNET | RR | 1 | R16C122[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_42_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.872 | 1.699 | tNET | RR | 1 | R16C122[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_42_s0/CLK |
| 7.826 | -0.046 | tSu | 1 | R16C122[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_42_s0 |
Path Statistics:
| Clock Skew | -0.001 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 1.154, 26.206%; route: 2.984, 67.784%; tC2Q: 0.265, 6.010% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.699, 100.000% |
Path6
Path Summary:
| Slack | 1.757 |
| Data Arrival Time | 6.054 |
| Data Required Time | 7.811 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_53_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.483 | 1.518 | tNET | FF | 1 | R23C131[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n594_s4/I2 |
| 3.691 | 0.208 | tINS | FR | 2 | R23C131[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n594_s4/F |
| 4.210 | 0.519 | tNET | RR | 1 | R21C126[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n594_s3/I0 |
| 4.604 | 0.394 | tINS | RR | 4 | R21C126[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n594_s3/F |
| 5.689 | 1.084 | tNET | RR | 1 | R15C124[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n594_s5/I0 |
| 6.054 | 0.365 | tINS | RR | 1 | R15C124[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n594_s5/F |
| 6.054 | 0.000 | tNET | RR | 1 | R15C124[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_53_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.857 | 1.684 | tNET | RR | 1 | R15C124[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_53_s0/CLK |
| 7.811 | -0.046 | tSu | 1 | R15C124[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_53_s0 |
Path Statistics:
| Clock Skew | -0.016 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 0.967, 22.220%; route: 3.122, 71.703%; tC2Q: 0.265, 6.077% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.684, 100.000% |
Path7
Path Summary:
| Slack | 1.781 |
| Data Arrival Time | 6.061 |
| Data Required Time | 7.841 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_28_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.072 | 1.107 | tNET | FF | 1 | R20C134[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n982_s4/I2 |
| 3.480 | 0.409 | tINS | FR | 2 | R20C134[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n982_s4/F |
| 4.027 | 0.546 | tNET | RR | 1 | R20C129[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n982_s3/I0 |
| 4.435 | 0.409 | tINS | RR | 7 | R20C129[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n982_s3/F |
| 5.695 | 1.260 | tNET | RR | 1 | R23C121[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n619_s2/I0 |
| 6.061 | 0.365 | tINS | RR | 1 | R23C121[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n619_s2/F |
| 6.061 | 0.000 | tNET | RR | 1 | R23C121[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_28_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.887 | 1.714 | tNET | RR | 1 | R23C121[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_28_s0/CLK |
| 7.841 | -0.046 | tSu | 1 | R23C121[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_28_s0 |
Path Statistics:
| Clock Skew | 0.014 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 1.183, 27.121%; route: 2.913, 66.811%; tC2Q: 0.265, 6.068% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.714, 100.000% |
Path8
Path Summary:
| Slack | 1.822 |
| Data Arrival Time | 6.005 |
| Data Required Time | 7.827 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_48_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.658 | 1.693 | tNET | FF | 1 | R21C131[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n788_s4/I2 |
| 3.986 | 0.329 | tINS | FR | 2 | R21C131[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n788_s4/F |
| 4.247 | 0.261 | tNET | RR | 1 | R21C129[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n788_s3/I0 |
| 4.656 | 0.409 | tINS | RR | 5 | R21C129[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n788_s3/F |
| 5.588 | 0.932 | tNET | RR | 1 | R17C126[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n599_s5/I1 |
| 6.005 | 0.417 | tINS | RR | 1 | R17C126[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n599_s5/F |
| 6.005 | 0.000 | tNET | RR | 1 | R17C126[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_48_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.873 | 1.700 | tNET | RR | 1 | R17C126[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_48_s0/CLK |
| 7.827 | -0.046 | tSu | 1 | R17C126[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_48_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 1.154, 26.803%; route: 2.886, 67.050%; tC2Q: 0.265, 6.147% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
Path9
Path Summary:
| Slack | 1.826 |
| Data Arrival Time | 6.016 |
| Data Required Time | 7.841 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_33_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.658 | 1.693 | tNET | FF | 1 | R21C131[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n995_s4/I2 |
| 3.986 | 0.329 | tINS | FR | 2 | R21C131[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n995_s4/F |
| 4.112 | 0.126 | tNET | RR | 1 | R20C131[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n993_s3/I1 |
| 4.477 | 0.365 | tINS | RR | 8 | R20C131[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n993_s3/F |
| 5.808 | 1.330 | tNET | RR | 1 | R23C129[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n811_s2/I0 |
| 6.016 | 0.208 | tINS | RR | 1 | R23C129[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n811_s2/F |
| 6.016 | 0.000 | tNET | RR | 1 | R23C129[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_33_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.887 | 1.714 | tNET | RR | 1 | R23C129[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_33_s0/CLK |
| 7.841 | -0.046 | tSu | 1 | R23C129[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_33_s0 |
Path Statistics:
| Clock Skew | 0.014 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 0.902, 20.897%; route: 3.149, 72.972%; tC2Q: 0.265, 6.131% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.714, 100.000% |
Path10
Path Summary:
| Slack | 1.875 |
| Data Arrival Time | 5.960 |
| Data Required Time | 7.834 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_36_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.072 | 1.107 | tNET | FF | 1 | R20C134[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n982_s4/I2 |
| 3.480 | 0.409 | tINS | FR | 2 | R20C134[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n982_s4/F |
| 4.027 | 0.546 | tNET | RR | 1 | R20C129[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n982_s3/I0 |
| 4.435 | 0.409 | tINS | RR | 7 | R20C129[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n982_s3/F |
| 5.543 | 1.108 | tNET | RR | 1 | R23C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n611_s2/I1 |
| 5.960 | 0.417 | tINS | RR | 1 | R23C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n611_s2/F |
| 5.960 | 0.000 | tNET | RR | 1 | R23C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_36_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.880 | 1.707 | tNET | RR | 1 | R23C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_36_s0/CLK |
| 7.834 | -0.046 | tSu | 1 | R23C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_36_s0 |
Path Statistics:
| Clock Skew | 0.007 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 1.234, 28.967%; route: 2.761, 64.821%; tC2Q: 0.265, 6.212% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.707, 100.000% |
Path11
Path Summary:
| Slack | 1.878 |
| Data Arrival Time | 5.949 |
| Data Required Time | 7.827 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_7_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.658 | 1.693 | tNET | FF | 1 | R21C131[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n995_s4/I2 |
| 3.986 | 0.329 | tINS | FR | 2 | R21C131[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n995_s4/F |
| 4.262 | 0.276 | tNET | RR | 1 | R22C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n995_s3/I0 |
| 4.679 | 0.417 | tINS | RR | 7 | R22C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n995_s3/F |
| 5.621 | 0.941 | tNET | RR | 1 | R17C130[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n443_s2/I1 |
| 5.949 | 0.329 | tINS | RR | 1 | R17C130[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n443_s2/F |
| 5.949 | 0.000 | tNET | RR | 1 | R17C130[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_7_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.873 | 1.700 | tNET | RR | 1 | R17C130[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_7_s0/CLK |
| 7.827 | -0.046 | tSu | 1 | R17C130[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_7_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 1.074, 25.270%; route: 2.911, 68.502%; tC2Q: 0.265, 6.227% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
Path12
Path Summary:
| Slack | 1.897 |
| Data Arrival Time | 5.924 |
| Data Required Time | 7.820 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_47_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.658 | 1.693 | tNET | FF | 1 | R21C131[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n995_s4/I2 |
| 3.986 | 0.329 | tINS | FR | 2 | R21C131[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n995_s4/F |
| 4.262 | 0.276 | tNET | RR | 1 | R22C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n995_s3/I0 |
| 4.679 | 0.417 | tINS | RR | 7 | R22C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n995_s3/F |
| 5.530 | 0.850 | tNET | RR | 1 | R17C125[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n995_s5/I0 |
| 5.924 | 0.394 | tINS | RR | 1 | R17C125[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n995_s5/F |
| 5.924 | 0.000 | tNET | RR | 1 | R17C125[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_47_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.866 | 1.693 | tNET | RR | 1 | R17C125[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_47_s0/CLK |
| 7.820 | -0.046 | tSu | 1 | R17C125[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_47_s0 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 1.139, 26.976%; route: 2.820, 66.759%; tC2Q: 0.265, 6.265% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.693, 100.000% |
Path13
Path Summary:
| Slack | 1.940 |
| Data Arrival Time | 5.903 |
| Data Required Time | 7.843 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_12_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.072 | 1.107 | tNET | FF | 1 | R20C134[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n982_s4/I2 |
| 3.480 | 0.409 | tINS | FR | 2 | R20C134[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n982_s4/F |
| 4.027 | 0.546 | tNET | RR | 1 | R20C129[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n982_s3/I0 |
| 4.435 | 0.409 | tINS | RR | 7 | R20C129[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n982_s3/F |
| 5.695 | 1.260 | tNET | RR | 1 | R22C121[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n438_s2/I0 |
| 5.903 | 0.208 | tINS | RR | 1 | R22C121[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n438_s2/F |
| 5.903 | 0.000 | tNET | RR | 1 | R22C121[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_12_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.889 | 1.716 | tNET | RR | 1 | R22C121[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_12_s0/CLK |
| 7.843 | -0.046 | tSu | 1 | R22C121[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_12_s0 |
Path Statistics:
| Clock Skew | 0.016 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 1.025, 24.390%; route: 2.913, 69.315%; tC2Q: 0.265, 6.296% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.716, 100.000% |
Path14
Path Summary:
| Slack | 1.970 |
| Data Arrival Time | 5.872 |
| Data Required Time | 7.841 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_57_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.658 | 1.693 | tNET | FF | 1 | R21C131[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n995_s4/I2 |
| 3.986 | 0.329 | tINS | FR | 2 | R21C131[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n995_s4/F |
| 4.112 | 0.126 | tNET | RR | 1 | R20C131[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n993_s3/I1 |
| 4.477 | 0.365 | tINS | RR | 8 | R20C131[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n993_s3/F |
| 5.455 | 0.977 | tNET | RR | 1 | R23C125[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n985_s5/I1 |
| 5.872 | 0.417 | tINS | RR | 1 | R23C125[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n985_s5/F |
| 5.872 | 0.000 | tNET | RR | 1 | R23C125[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_57_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.887 | 1.714 | tNET | RR | 1 | R23C125[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_57_s0/CLK |
| 7.841 | -0.046 | tSu | 1 | R23C125[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_57_s0 |
Path Statistics:
| Clock Skew | 0.014 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 1.111, 26.624%; route: 2.796, 67.033%; tC2Q: 0.265, 6.343% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.714, 100.000% |
Path15
Path Summary:
| Slack | 1.983 |
| Data Arrival Time | 5.832 |
| Data Required Time | 7.815 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_9_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.658 | 1.693 | tNET | FF | 1 | R21C131[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n995_s4/I2 |
| 3.986 | 0.329 | tINS | FR | 2 | R21C131[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n995_s4/F |
| 4.112 | 0.126 | tNET | RR | 1 | R20C131[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n993_s3/I1 |
| 4.477 | 0.365 | tINS | RR | 8 | R20C131[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n993_s3/F |
| 5.467 | 0.989 | tNET | RR | 1 | R18C132[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n441_s2/I1 |
| 5.832 | 0.365 | tINS | RR | 1 | R18C132[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n441_s2/F |
| 5.832 | 0.000 | tNET | RR | 1 | R18C132[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_9_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.861 | 1.688 | tNET | RR | 1 | R18C132[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_9_s0/CLK |
| 7.815 | -0.046 | tSu | 1 | R18C132[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_9_s0 |
Path Statistics:
| Clock Skew | -0.012 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 1.059, 25.637%; route: 2.808, 67.959%; tC2Q: 0.265, 6.404% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.688, 100.000% |
Path16
Path Summary:
| Slack | 2.002 |
| Data Arrival Time | 5.817 |
| Data Required Time | 7.819 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_4_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.658 | 1.693 | tNET | FF | 1 | R21C131[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1000_s4/I2 |
| 3.865 | 0.208 | tINS | FR | 2 | R21C131[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1000_s4/F |
| 3.991 | 0.126 | tNET | RR | 1 | R21C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n998_s3/I1 |
| 4.400 | 0.409 | tINS | RR | 7 | R21C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n998_s3/F |
| 5.609 | 1.209 | tNET | RR | 1 | R16C129[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n446_s2/I1 |
| 5.817 | 0.208 | tINS | RR | 1 | R16C129[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n446_s2/F |
| 5.817 | 0.000 | tNET | RR | 1 | R16C129[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_4_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.865 | 1.692 | tNET | RR | 1 | R16C129[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_4_s0/CLK |
| 7.819 | -0.046 | tSu | 1 | R16C129[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_4_s0 |
Path Statistics:
| Clock Skew | -0.008 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 0.824, 20.026%; route: 3.028, 73.546%; tC2Q: 0.265, 6.428% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.692, 100.000% |
Path17
Path Summary:
| Slack | 2.010 |
| Data Arrival Time | 5.833 |
| Data Required Time | 7.843 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_59_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.483 | 1.518 | tNET | FF | 1 | R23C132[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n399_s5/I2 |
| 3.691 | 0.208 | tINS | FR | 2 | R23C132[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n399_s5/F |
| 4.252 | 0.562 | tNET | RR | 1 | R22C130[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n399_s3/I0 |
| 4.661 | 0.409 | tINS | RR | 3 | R22C130[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n399_s3/F |
| 5.467 | 0.806 | tNET | RR | 1 | R22C125[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n588_s3/I0 |
| 5.833 | 0.365 | tINS | RR | 1 | R22C125[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n588_s3/F |
| 5.833 | 0.000 | tNET | RR | 1 | R22C125[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_59_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.889 | 1.716 | tNET | RR | 1 | R22C125[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_59_s0/CLK |
| 7.843 | -0.046 | tSu | 1 | R22C125[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_59_s0 |
Path Statistics:
| Clock Skew | 0.016 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 0.982, 23.759%; route: 2.886, 69.839%; tC2Q: 0.265, 6.402% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.716, 100.000% |
Path18
Path Summary:
| Slack | 2.024 |
| Data Arrival Time | 5.795 |
| Data Required Time | 7.819 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_50_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.658 | 1.693 | tNET | FF | 1 | R21C131[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n788_s4/I2 |
| 3.986 | 0.329 | tINS | FR | 2 | R21C131[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n788_s4/F |
| 4.317 | 0.331 | tNET | RR | 1 | R21C128[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n786_s3/I1 |
| 4.734 | 0.417 | tINS | RR | 5 | R21C128[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n786_s3/F |
| 5.587 | 0.853 | tNET | RR | 1 | R16C125[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n597_s5/I1 |
| 5.795 | 0.208 | tINS | RR | 1 | R16C125[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n597_s5/F |
| 5.795 | 0.000 | tNET | RR | 1 | R16C125[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_50_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.865 | 1.692 | tNET | RR | 1 | R16C125[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_50_s0/CLK |
| 7.819 | -0.046 | tSu | 1 | R16C125[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_50_s0 |
Path Statistics:
| Clock Skew | -0.008 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 0.953, 23.275%; route: 2.877, 70.264%; tC2Q: 0.265, 6.462% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.692, 100.000% |
Path19
Path Summary:
| Slack | 2.025 |
| Data Arrival Time | 5.624 |
| Data Required Time | 7.649 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_2_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.693 | 1.693 | tNET | RR | 1 | R17C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_1_s0/CLK |
| 1.969 | 0.275 | tC2Q | RR | 5 | R17C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_1_s0/Q |
| 2.097 | 0.128 | tNET | RR | 1 | R17C138[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd_g2b/rdaddr_bin_1_s0/I0 |
| 2.510 | 0.413 | tINS | RR | 4 | R17C138[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd_g2b/rdaddr_bin_1_s0/F |
| 2.958 | 0.448 | tNET | RR | 1 | R17C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd_g2b/rdaddr_bin_0_s/I1 |
| 3.286 | 0.329 | tINS | RR | 2 | R17C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd_g2b/rdaddr_bin_0_s/F |
| 3.627 | 0.341 | tNET | RR | 2 | R20C137[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_0_s/I1 |
| 4.020 | 0.392 | tINS | RR | 1 | R20C137[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_0_s/COUT |
| 4.020 | 0.000 | tNET | RR | 2 | R20C137[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_1_s/CIN |
| 4.056 | 0.036 | tINS | RR | 1 | R20C137[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_1_s/COUT |
| 4.056 | 0.000 | tNET | RR | 2 | R20C137[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_2_s/CIN |
| 4.231 | 0.175 | tINS | RR | 1 | R20C137[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_2_s/SUM |
| 4.340 | 0.109 | tNET | RR | 1 | R20C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n82_s1/I2 |
| 4.734 | 0.394 | tINS | RR | 2 | R20C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n82_s1/F |
| 4.738 | 0.004 | tNET | RR | 1 | R20C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n82_s0/I2 |
| 5.103 | 0.365 | tINS | RR | 5 | R20C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n82_s0/F |
| 5.624 | 0.520 | tNET | RR | 1 | R17C138[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_2_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.873 | 1.700 | tNET | RR | 1 | R17C138[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_2_s0/CLK |
| 7.649 | -0.224 | tSu | 1 | R17C138[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_2_s0 |
Path Statistics:
| Clock Skew | 0.007 |
| Setup Relationship | 6.173 |
| Logic Level | 7 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.693, 100.000% |
| Arrival Data Path Delay | cell: 2.105, 53.561%; route: 1.550, 39.432%; tC2Q: 0.275, 7.007% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
Path20
Path Summary:
| Slack | 2.025 |
| Data Arrival Time | 5.624 |
| Data Required Time | 7.649 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_3_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.693 | 1.693 | tNET | RR | 1 | R17C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_1_s0/CLK |
| 1.969 | 0.275 | tC2Q | RR | 5 | R17C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_1_s0/Q |
| 2.097 | 0.128 | tNET | RR | 1 | R17C138[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd_g2b/rdaddr_bin_1_s0/I0 |
| 2.510 | 0.413 | tINS | RR | 4 | R17C138[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd_g2b/rdaddr_bin_1_s0/F |
| 2.958 | 0.448 | tNET | RR | 1 | R17C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd_g2b/rdaddr_bin_0_s/I1 |
| 3.286 | 0.329 | tINS | RR | 2 | R17C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd_g2b/rdaddr_bin_0_s/F |
| 3.627 | 0.341 | tNET | RR | 2 | R20C137[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_0_s/I1 |
| 4.020 | 0.392 | tINS | RR | 1 | R20C137[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_0_s/COUT |
| 4.020 | 0.000 | tNET | RR | 2 | R20C137[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_1_s/CIN |
| 4.056 | 0.036 | tINS | RR | 1 | R20C137[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_1_s/COUT |
| 4.056 | 0.000 | tNET | RR | 2 | R20C137[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_2_s/CIN |
| 4.231 | 0.175 | tINS | RR | 1 | R20C137[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_2_s/SUM |
| 4.340 | 0.109 | tNET | RR | 1 | R20C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n82_s1/I2 |
| 4.734 | 0.394 | tINS | RR | 2 | R20C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n82_s1/F |
| 4.738 | 0.004 | tNET | RR | 1 | R20C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n82_s0/I2 |
| 5.103 | 0.365 | tINS | RR | 5 | R20C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n82_s0/F |
| 5.624 | 0.520 | tNET | RR | 1 | R17C138[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_3_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.873 | 1.700 | tNET | RR | 1 | R17C138[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_3_s0/CLK |
| 7.649 | -0.224 | tSu | 1 | R17C138[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_3_s0 |
Path Statistics:
| Clock Skew | 0.007 |
| Setup Relationship | 6.173 |
| Logic Level | 7 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.693, 100.000% |
| Arrival Data Path Delay | cell: 2.105, 53.561%; route: 1.550, 39.432%; tC2Q: 0.275, 7.007% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
Path21
Path Summary:
| Slack | 2.025 |
| Data Arrival Time | 5.624 |
| Data Required Time | 7.649 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_4_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.693 | 1.693 | tNET | RR | 1 | R17C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_1_s0/CLK |
| 1.969 | 0.275 | tC2Q | RR | 5 | R17C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_1_s0/Q |
| 2.097 | 0.128 | tNET | RR | 1 | R17C138[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd_g2b/rdaddr_bin_1_s0/I0 |
| 2.510 | 0.413 | tINS | RR | 4 | R17C138[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd_g2b/rdaddr_bin_1_s0/F |
| 2.958 | 0.448 | tNET | RR | 1 | R17C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd_g2b/rdaddr_bin_0_s/I1 |
| 3.286 | 0.329 | tINS | RR | 2 | R17C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd_g2b/rdaddr_bin_0_s/F |
| 3.627 | 0.341 | tNET | RR | 2 | R20C137[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_0_s/I1 |
| 4.020 | 0.392 | tINS | RR | 1 | R20C137[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_0_s/COUT |
| 4.020 | 0.000 | tNET | RR | 2 | R20C137[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_1_s/CIN |
| 4.056 | 0.036 | tINS | RR | 1 | R20C137[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_1_s/COUT |
| 4.056 | 0.000 | tNET | RR | 2 | R20C137[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_2_s/CIN |
| 4.231 | 0.175 | tINS | RR | 1 | R20C137[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_2_s/SUM |
| 4.340 | 0.109 | tNET | RR | 1 | R20C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n82_s1/I2 |
| 4.734 | 0.394 | tINS | RR | 2 | R20C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n82_s1/F |
| 4.738 | 0.004 | tNET | RR | 1 | R20C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n82_s0/I2 |
| 5.103 | 0.365 | tINS | RR | 5 | R20C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n82_s0/F |
| 5.624 | 0.520 | tNET | RR | 1 | R17C138[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_4_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.873 | 1.700 | tNET | RR | 1 | R17C138[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_4_s0/CLK |
| 7.649 | -0.224 | tSu | 1 | R17C138[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_4_s0 |
Path Statistics:
| Clock Skew | 0.007 |
| Setup Relationship | 6.173 |
| Logic Level | 7 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.693, 100.000% |
| Arrival Data Path Delay | cell: 2.105, 53.561%; route: 1.550, 39.432%; tC2Q: 0.275, 7.007% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
Path22
Path Summary:
| Slack | 2.026 |
| Data Arrival Time | 5.789 |
| Data Required Time | 7.815 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_43_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.483 | 1.518 | tNET | FF | 1 | R23C132[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n399_s5/I2 |
| 3.691 | 0.208 | tINS | FR | 2 | R23C132[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n399_s5/F |
| 4.252 | 0.562 | tNET | RR | 1 | R22C130[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n399_s3/I0 |
| 4.661 | 0.409 | tINS | RR | 3 | R22C130[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n399_s3/F |
| 5.423 | 0.762 | tNET | RR | 1 | R18C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n407_s2/I0 |
| 5.789 | 0.365 | tINS | RR | 1 | R18C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n407_s2/F |
| 5.789 | 0.000 | tNET | RR | 1 | R18C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_43_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.861 | 1.688 | tNET | RR | 1 | R18C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_43_s0/CLK |
| 7.815 | -0.046 | tSu | 1 | R18C124[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_43_s0 |
Path Statistics:
| Clock Skew | -0.012 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 0.982, 24.015%; route: 2.842, 69.514%; tC2Q: 0.265, 6.471% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.688, 100.000% |
Path23
Path Summary:
| Slack | 2.028 |
| Data Arrival Time | 5.800 |
| Data Required Time | 7.829 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_16_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.072 | 1.107 | tNET | FF | 1 | R20C134[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n986_s4/I2 |
| 3.480 | 0.409 | tINS | FR | 2 | R20C134[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n986_s4/F |
| 4.155 | 0.675 | tNET | RR | 1 | R21C130[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n986_s3/I0 |
| 4.568 | 0.413 | tINS | RR | 7 | R21C130[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n986_s3/F |
| 5.435 | 0.867 | tNET | RR | 1 | R18C122[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n434_s2/I1 |
| 5.800 | 0.365 | tINS | RR | 1 | R18C122[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n434_s2/F |
| 5.800 | 0.000 | tNET | RR | 1 | R18C122[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_16_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.874 | 1.701 | tNET | RR | 1 | R18C122[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_16_s0/CLK |
| 7.829 | -0.046 | tSu | 1 | R18C122[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_16_s0 |
Path Statistics:
| Clock Skew | 0.001 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 1.187, 28.951%; route: 2.649, 64.596%; tC2Q: 0.265, 6.453% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.701, 100.000% |
Path24
Path Summary:
| Slack | 2.046 |
| Data Arrival Time | 5.766 |
| Data Required Time | 7.812 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_44_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.483 | 1.518 | tNET | FF | 1 | R23C131[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n595_s4/I2 |
| 3.693 | 0.210 | tINS | FR | 2 | R23C131[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n595_s4/F |
| 4.319 | 0.626 | tNET | RR | 1 | R20C127[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n595_s3/I0 |
| 4.736 | 0.417 | tINS | RR | 4 | R20C127[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n595_s3/F |
| 5.558 | 0.823 | tNET | RR | 1 | R16C124[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n406_s2/I1 |
| 5.766 | 0.208 | tINS | RR | 1 | R16C124[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n406_s2/F |
| 5.766 | 0.000 | tNET | RR | 1 | R16C124[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_44_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.858 | 1.685 | tNET | RR | 1 | R16C124[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_44_s0/CLK |
| 7.812 | -0.046 | tSu | 1 | R16C124[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_44_s0 |
Path Statistics:
| Clock Skew | -0.015 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 0.834, 20.518%; route: 2.967, 72.975%; tC2Q: 0.265, 6.507% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.685, 100.000% |
Path25
Path Summary:
| Slack | 2.047 |
| Data Arrival Time | 5.798 |
| Data Required Time | 7.845 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_34_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.658 | 1.693 | tNET | FF | 1 | R21C131[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n788_s4/I2 |
| 3.986 | 0.329 | tINS | FR | 2 | R21C131[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n788_s4/F |
| 4.317 | 0.331 | tNET | RR | 1 | R21C128[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n786_s3/I1 |
| 4.734 | 0.417 | tINS | RR | 5 | R21C128[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n786_s3/F |
| 5.381 | 0.647 | tNET | RR | 1 | R21C123[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n416_s2/I1 |
| 5.798 | 0.417 | tINS | RR | 1 | R21C123[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n416_s2/F |
| 5.798 | 0.000 | tNET | RR | 1 | R21C123[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_34_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.891 | 1.718 | tNET | RR | 1 | R21C123[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_34_s0/CLK |
| 7.845 | -0.046 | tSu | 1 | R21C123[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_34_s0 |
Path Statistics:
| Clock Skew | 0.018 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 1.162, 28.355%; route: 2.671, 65.188%; tC2Q: 0.265, 6.457% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.718, 100.000% |
Path26
Path Summary:
| Slack | 2.052 |
| Data Arrival Time | 5.768 |
| Data Required Time | 7.820 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_20_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.072 | 1.107 | tNET | FF | 1 | R20C134[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n982_s4/I2 |
| 3.480 | 0.409 | tINS | FR | 2 | R20C134[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n982_s4/F |
| 4.027 | 0.546 | tNET | RR | 1 | R20C129[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n982_s3/I0 |
| 4.435 | 0.409 | tINS | RR | 7 | R20C129[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n982_s3/F |
| 5.351 | 0.916 | tNET | RR | 1 | R17C121[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n430_s2/I1 |
| 5.768 | 0.417 | tINS | RR | 1 | R17C121[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n430_s2/F |
| 5.768 | 0.000 | tNET | RR | 1 | R17C121[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_20_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.866 | 1.693 | tNET | RR | 1 | R17C121[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_20_s0/CLK |
| 7.820 | -0.046 | tSu | 1 | R17C121[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_20_s0 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 1.234, 30.332%; route: 2.569, 63.164%; tC2Q: 0.265, 6.504% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.693, 100.000% |
Path27
Path Summary:
| Slack | 2.064 |
| Data Arrival Time | 5.762 |
| Data Required Time | 7.826 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_42_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.284 | 1.319 | tNET | FF | 1 | R21C134[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n994_s4/I2 |
| 3.492 | 0.208 | tINS | FR | 2 | R21C134[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n994_s4/F |
| 4.069 | 0.577 | tNET | RR | 1 | R22C130[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n992_s3/I1 |
| 4.486 | 0.417 | tINS | RR | 8 | R22C130[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n992_s3/F |
| 5.353 | 0.868 | tNET | RR | 1 | R16C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n802_s2/I1 |
| 5.762 | 0.409 | tINS | RR | 1 | R16C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n802_s2/F |
| 5.762 | 0.000 | tNET | RR | 1 | R16C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_42_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.872 | 1.699 | tNET | RR | 1 | R16C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_42_s0/CLK |
| 7.826 | -0.046 | tSu | 1 | R16C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_42_s0 |
Path Statistics:
| Clock Skew | -0.001 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 1.033, 25.438%; route: 2.764, 68.048%; tC2Q: 0.265, 6.515% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.699, 100.000% |
Path28
Path Summary:
| Slack | 2.075 |
| Data Arrival Time | 5.778 |
| Data Required Time | 7.853 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_61_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.483 | 1.518 | tNET | FF | 1 | R23C132[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n399_s5/I2 |
| 3.691 | 0.208 | tINS | FR | 2 | R23C132[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n399_s5/F |
| 3.995 | 0.304 | tNET | RR | 1 | R22C131[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n397_s3/I1 |
| 4.412 | 0.417 | tINS | RR | 3 | R22C131[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n397_s3/F |
| 5.570 | 1.158 | tNET | RR | 1 | R20C126[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n586_s3/I0 |
| 5.778 | 0.208 | tINS | RR | 1 | R20C126[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n586_s3/F |
| 5.778 | 0.000 | tNET | RR | 1 | R20C126[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_61_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.899 | 1.726 | tNET | RR | 1 | R20C126[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_61_s0/CLK |
| 7.853 | -0.046 | tSu | 1 | R20C126[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_61_s0 |
Path Statistics:
| Clock Skew | 0.026 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 0.832, 20.415%; route: 2.981, 73.096%; tC2Q: 0.265, 6.489% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.726, 100.000% |
Path29
Path Summary:
| Slack | 2.078 |
| Data Arrival Time | 5.744 |
| Data Required Time | 7.822 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_41_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.658 | 1.693 | tNET | FF | 1 | R22C131[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n401_s7/I2 |
| 3.986 | 0.329 | tINS | FR | 2 | R22C131[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n401_s7/F |
| 4.112 | 0.126 | tNET | RR | 1 | R22C130[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n401_s3/I1 |
| 4.525 | 0.413 | tINS | RR | 3 | R22C130[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n401_s3/F |
| 5.536 | 1.011 | tNET | RR | 1 | R18C125[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n409_s2/I0 |
| 5.744 | 0.208 | tINS | RR | 1 | R18C125[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n409_s2/F |
| 5.744 | 0.000 | tNET | RR | 1 | R18C125[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_41_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.868 | 1.695 | tNET | RR | 1 | R18C125[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_41_s0/CLK |
| 7.822 | -0.046 | tSu | 1 | R18C125[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_41_s0 |
Path Statistics:
| Clock Skew | -0.005 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 0.949, 23.481%; route: 2.830, 69.976%; tC2Q: 0.265, 6.544% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.695, 100.000% |
Path30
Path Summary:
| Slack | 2.087 |
| Data Arrival Time | 5.764 |
| Data Required Time | 7.852 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_24_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.658 | 1.693 | tNET | FF | 1 | R21C131[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n788_s4/I2 |
| 3.986 | 0.329 | tINS | FR | 2 | R21C131[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n788_s4/F |
| 4.247 | 0.261 | tNET | RR | 1 | R21C129[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n788_s3/I0 |
| 4.656 | 0.409 | tINS | RR | 5 | R21C129[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n788_s3/F |
| 5.356 | 0.700 | tNET | RR | 1 | R21C122[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n426_s2/I0 |
| 5.764 | 0.409 | tINS | RR | 1 | R21C122[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n426_s2/F |
| 5.764 | 0.000 | tNET | RR | 1 | R21C122[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_24_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.897 | 1.724 | tNET | RR | 1 | R21C122[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_24_s0/CLK |
| 7.852 | -0.046 | tSu | 1 | R21C122[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_24_s0 |
Path Statistics:
| Clock Skew | 0.024 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 1.146, 28.189%; route: 2.654, 65.301%; tC2Q: 0.265, 6.510% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.724, 100.000% |
Path31
Path Summary:
| Slack | 2.087 |
| Data Arrival Time | 5.737 |
| Data Required Time | 7.825 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_37_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.299 | 1.335 | tNET | FF | 1 | R23C126[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1015_s4/I2 |
| 3.529 | 0.229 | tINS | FF | 2 | R23C126[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1015_s4/F |
| 3.790 | 0.261 | tNET | FF | 1 | R20C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1013_s3/I1 |
| 4.207 | 0.417 | tINS | FR | 5 | R20C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1013_s3/F |
| 5.329 | 1.122 | tNET | RR | 1 | R15C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1005_s5/I1 |
| 5.737 | 0.409 | tINS | RR | 1 | R15C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1005_s5/F |
| 5.737 | 0.000 | tNET | RR | 1 | R15C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_37_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.870 | 1.697 | tNET | RR | 1 | R15C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_37_s0/CLK |
| 7.825 | -0.046 | tSu | 1 | R15C122[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_37_s0 |
Path Statistics:
| Clock Skew | -0.003 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 1.055, 26.126%; route: 2.718, 67.321%; tC2Q: 0.265, 6.554% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.697, 100.000% |
Path32
Path Summary:
| Slack | 2.087 |
| Data Arrival Time | 5.733 |
| Data Required Time | 7.820 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_6_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.299 | 1.335 | tNET | FF | 1 | R23C127[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1036_s4/I2 |
| 3.507 | 0.208 | tINS | FR | 2 | R23C127[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1036_s4/F |
| 3.811 | 0.304 | tNET | RR | 1 | R20C127[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1036_s2/I0 |
| 4.206 | 0.394 | tINS | RR | 2 | R20C127[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1036_s2/F |
| 5.405 | 1.199 | tNET | RR | 1 | R17C131[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1036_s1/I0 |
| 5.733 | 0.329 | tINS | RR | 1 | R17C131[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1036_s1/F |
| 5.733 | 0.000 | tNET | RR | 1 | R17C131[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_6_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.866 | 1.693 | tNET | RR | 1 | R17C131[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_6_s0/CLK |
| 7.820 | -0.046 | tSu | 1 | R17C131[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_6_s0 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 0.931, 23.075%; route: 2.838, 70.364%; tC2Q: 0.265, 6.561% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.693, 100.000% |
Path33
Path Summary:
| Slack | 2.099 |
| Data Arrival Time | 5.719 |
| Data Required Time | 7.818 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_60_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.072 | 1.107 | tNET | FF | 1 | R20C134[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n982_s4/I2 |
| 3.480 | 0.409 | tINS | FR | 2 | R20C134[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n982_s4/F |
| 4.027 | 0.546 | tNET | RR | 1 | R20C129[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n982_s3/I0 |
| 4.435 | 0.409 | tINS | RR | 7 | R20C129[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n982_s3/F |
| 5.353 | 0.918 | tNET | RR | 1 | R15C127[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n982_s5/I0 |
| 5.719 | 0.365 | tINS | RR | 1 | R15C127[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n982_s5/F |
| 5.719 | 0.000 | tNET | RR | 1 | R15C127[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_60_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.864 | 1.691 | tNET | RR | 1 | R15C127[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_60_s0/CLK |
| 7.818 | -0.046 | tSu | 1 | R15C127[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_60_s0 |
Path Statistics:
| Clock Skew | -0.009 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 1.183, 29.429%; route: 2.571, 63.987%; tC2Q: 0.265, 6.585% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.691, 100.000% |
Path34
Path Summary:
| Slack | 2.109 |
| Data Arrival Time | 5.551 |
| Data Required Time | 7.660 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/fifo_half_latch_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.693 | 1.693 | tNET | RR | 1 | R17C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_1_s0/CLK |
| 1.969 | 0.275 | tC2Q | RR | 5 | R17C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_1_s0/Q |
| 2.097 | 0.128 | tNET | RR | 1 | R17C138[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd_g2b/rdaddr_bin_1_s0/I0 |
| 2.510 | 0.413 | tINS | RR | 4 | R17C138[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd_g2b/rdaddr_bin_1_s0/F |
| 2.958 | 0.448 | tNET | RR | 1 | R17C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd_g2b/rdaddr_bin_0_s/I1 |
| 3.286 | 0.329 | tINS | RR | 2 | R17C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd_g2b/rdaddr_bin_0_s/F |
| 3.627 | 0.341 | tNET | RR | 2 | R20C137[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_0_s/I1 |
| 4.020 | 0.392 | tINS | RR | 1 | R20C137[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_0_s/COUT |
| 4.020 | 0.000 | tNET | RR | 2 | R20C137[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_1_s/CIN |
| 4.056 | 0.036 | tINS | RR | 1 | R20C137[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_1_s/COUT |
| 4.056 | 0.000 | tNET | RR | 2 | R20C137[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_2_s/CIN |
| 4.231 | 0.175 | tINS | RR | 1 | R20C137[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_2_s/SUM |
| 4.340 | 0.109 | tNET | RR | 1 | R20C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n82_s1/I2 |
| 4.734 | 0.394 | tINS | RR | 2 | R20C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n82_s1/F |
| 4.860 | 0.126 | tNET | RR | 1 | R21C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/fifo_half_latch_s2/I0 |
| 5.274 | 0.413 | tINS | RR | 1 | R21C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/fifo_half_latch_s2/F |
| 5.551 | 0.277 | tNET | RR | 1 | R21C136[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/fifo_half_latch_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.884 | 1.711 | tNET | RR | 1 | R21C136[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/fifo_half_latch_s0/CLK |
| 7.660 | -0.224 | tSu | 1 | R21C136[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/fifo_half_latch_s0 |
Path Statistics:
| Clock Skew | 0.018 |
| Setup Relationship | 6.173 |
| Logic Level | 7 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.693, 100.000% |
| Arrival Data Path Delay | cell: 2.153, 55.810%; route: 1.429, 37.051%; tC2Q: 0.275, 7.140% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.711, 100.000% |
Path35
Path Summary:
| Slack | 2.114 |
| Data Arrival Time | 5.710 |
| Data Required Time | 7.825 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_54_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.483 | 1.518 | tNET | FF | 1 | R23C131[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n595_s4/I2 |
| 3.712 | 0.229 | tINS | FF | 2 | R23C131[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n595_s4/F |
| 4.222 | 0.509 | tNET | FF | 1 | R21C127[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n593_s3/I1 |
| 4.616 | 0.394 | tINS | FR | 4 | R21C127[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n593_s3/F |
| 5.316 | 0.700 | tNET | RR | 1 | R15C126[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n593_s4/I0 |
| 5.710 | 0.394 | tINS | RR | 1 | R15C126[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n593_s4/F |
| 5.710 | 0.000 | tNET | RR | 1 | R15C126[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_54_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.870 | 1.697 | tNET | RR | 1 | R15C126[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_54_s0/CLK |
| 7.825 | -0.046 | tSu | 1 | R15C126[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_54_s0 |
Path Statistics:
| Clock Skew | -0.003 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 1.018, 25.382%; route: 2.728, 68.021%; tC2Q: 0.265, 6.598% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.697, 100.000% |
Path36
Path Summary:
| Slack | 2.131 |
| Data Arrival Time | 5.690 |
| Data Required Time | 7.820 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_20_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.658 | 1.693 | tNET | FF | 1 | R21C131[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1000_s4/I2 |
| 3.865 | 0.208 | tINS | FR | 2 | R21C131[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1000_s4/F |
| 3.991 | 0.126 | tNET | RR | 1 | R21C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n998_s3/I1 |
| 4.400 | 0.409 | tINS | RR | 7 | R21C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n998_s3/F |
| 5.281 | 0.881 | tNET | RR | 1 | R17C121[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n627_s2/I1 |
| 5.690 | 0.409 | tINS | RR | 1 | R17C121[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n627_s2/F |
| 5.690 | 0.000 | tNET | RR | 1 | R17C121[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_20_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.866 | 1.693 | tNET | RR | 1 | R17C121[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_20_s0/CLK |
| 7.820 | -0.046 | tSu | 1 | R17C121[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_20_s0 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 1.025, 25.694%; route: 2.700, 67.674%; tC2Q: 0.265, 6.632% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.693, 100.000% |
Path37
Path Summary:
| Slack | 2.131 |
| Data Arrival Time | 5.687 |
| Data Required Time | 7.818 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_29_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.299 | 1.335 | tNET | FF | 1 | R23C126[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1015_s4/I2 |
| 3.529 | 0.229 | tINS | FF | 2 | R23C126[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1015_s4/F |
| 3.790 | 0.261 | tNET | FF | 1 | R20C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1013_s3/I1 |
| 4.207 | 0.417 | tINS | FR | 5 | R20C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1013_s3/F |
| 5.479 | 1.273 | tNET | RR | 1 | R15C121[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1013_s5/I0 |
| 5.687 | 0.208 | tINS | RR | 1 | R15C121[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1013_s5/F |
| 5.687 | 0.000 | tNET | RR | 1 | R15C121[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_29_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.864 | 1.691 | tNET | RR | 1 | R15C121[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_29_s0/CLK |
| 7.818 | -0.046 | tSu | 1 | R15C121[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_29_s0 |
Path Statistics:
| Clock Skew | -0.009 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 0.854, 21.422%; route: 2.868, 71.941%; tC2Q: 0.265, 6.637% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.691, 100.000% |
Path38
Path Summary:
| Slack | 2.143 |
| Data Arrival Time | 5.668 |
| Data Required Time | 7.811 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_44_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.072 | 1.107 | tNET | FF | 1 | R20C134[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n982_s4/I2 |
| 3.480 | 0.409 | tINS | FR | 2 | R20C134[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n982_s4/F |
| 4.027 | 0.546 | tNET | RR | 1 | R20C129[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n982_s3/I0 |
| 4.435 | 0.409 | tINS | RR | 7 | R20C129[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n982_s3/F |
| 5.460 | 1.025 | tNET | RR | 1 | R15C124[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n800_s2/I0 |
| 5.668 | 0.208 | tINS | RR | 1 | R15C124[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n800_s2/F |
| 5.668 | 0.000 | tNET | RR | 1 | R15C124[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_44_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.857 | 1.684 | tNET | RR | 1 | R15C124[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_44_s0/CLK |
| 7.811 | -0.046 | tSu | 1 | R15C124[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_44_s0 |
Path Statistics:
| Clock Skew | -0.016 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 1.025, 25.834%; route: 2.678, 67.498%; tC2Q: 0.265, 6.668% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.684, 100.000% |
Path39
Path Summary:
| Slack | 2.155 |
| Data Arrival Time | 5.665 |
| Data Required Time | 7.819 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_60_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.483 | 1.518 | tNET | FF | 1 | R23C131[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n595_s4/I2 |
| 3.693 | 0.210 | tINS | FR | 2 | R23C131[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n595_s4/F |
| 4.319 | 0.626 | tNET | RR | 1 | R20C127[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n595_s3/I0 |
| 4.736 | 0.417 | tINS | RR | 4 | R20C127[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n595_s3/F |
| 5.256 | 0.520 | tNET | RR | 1 | R16C127[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n587_s3/I1 |
| 5.665 | 0.409 | tINS | RR | 1 | R16C127[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n587_s3/F |
| 5.665 | 0.000 | tNET | RR | 1 | R16C127[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_60_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.865 | 1.692 | tNET | RR | 1 | R16C127[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_60_s0/CLK |
| 7.819 | -0.046 | tSu | 1 | R16C127[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_60_s0 |
Path Statistics:
| Clock Skew | -0.008 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 1.035, 26.107%; route: 2.665, 67.219%; tC2Q: 0.265, 6.674% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.692, 100.000% |
Path40
Path Summary:
| Slack | 2.158 |
| Data Arrival Time | 5.689 |
| Data Required Time | 7.847 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_51_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.483 | 1.518 | tNET | FF | 1 | R23C132[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n399_s5/I2 |
| 3.691 | 0.208 | tINS | FR | 2 | R23C132[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n399_s5/F |
| 4.252 | 0.562 | tNET | RR | 1 | R22C130[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n399_s3/I0 |
| 4.661 | 0.409 | tINS | RR | 3 | R22C130[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n399_s3/F |
| 5.360 | 0.699 | tNET | RR | 1 | R20C125[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n399_s1/I1 |
| 5.689 | 0.329 | tINS | RR | 1 | R20C125[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n399_s1/F |
| 5.689 | 0.000 | tNET | RR | 1 | R20C125[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_51_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.892 | 1.719 | tNET | RR | 1 | R20C125[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_51_s0/CLK |
| 7.847 | -0.046 | tSu | 1 | R20C125[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_51_s0 |
Path Statistics:
| Clock Skew | 0.019 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 0.945, 23.691%; route: 2.779, 69.675%; tC2Q: 0.265, 6.634% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.719, 100.000% |
Path41
Path Summary:
| Slack | 2.166 |
| Data Arrival Time | 5.674 |
| Data Required Time | 7.840 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/din_d0_28_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_36_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.726 | 1.726 | tNET | RR | 1 | R20C138[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/din_d0_28_s0/CLK |
| 1.991 | 0.265 | tC2Q | RF | 3 | R20C138[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/din_d0_28_s0/Q |
| 2.788 | 0.797 | tNET | FF | 1 | R20C132[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n784_s4/I0 |
| 3.205 | 0.417 | tINS | FR | 2 | R20C132[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n784_s4/F |
| 3.602 | 0.397 | tNET | RR | 1 | R21C128[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n784_s3/I0 |
| 4.018 | 0.417 | tINS | RR | 5 | R21C128[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n784_s3/F |
| 5.308 | 1.290 | tNET | RR | 1 | R20C124[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n414_s2/I1 |
| 5.674 | 0.365 | tINS | RR | 1 | R20C124[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n414_s2/F |
| 5.674 | 0.000 | tNET | RR | 1 | R20C124[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_36_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.886 | 1.713 | tNET | RR | 1 | R20C124[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_36_s0/CLK |
| 7.840 | -0.046 | tSu | 1 | R20C124[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_36_s0 |
Path Statistics:
| Clock Skew | -0.013 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.726, 100.000% |
| Arrival Data Path Delay | cell: 1.199, 30.369%; route: 2.484, 62.927%; tC2Q: 0.265, 6.703% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.713, 100.000% |
Path42
Path Summary:
| Slack | 2.171 |
| Data Arrival Time | 5.472 |
| Data Required Time | 7.642 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_0_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.693 | 1.693 | tNET | RR | 1 | R17C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_1_s0/CLK |
| 1.969 | 0.275 | tC2Q | RR | 5 | R17C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_1_s0/Q |
| 2.097 | 0.128 | tNET | RR | 1 | R17C138[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd_g2b/rdaddr_bin_1_s0/I0 |
| 2.510 | 0.413 | tINS | RR | 4 | R17C138[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd_g2b/rdaddr_bin_1_s0/F |
| 2.958 | 0.448 | tNET | RR | 1 | R17C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd_g2b/rdaddr_bin_0_s/I1 |
| 3.286 | 0.329 | tINS | RR | 2 | R17C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd_g2b/rdaddr_bin_0_s/F |
| 3.627 | 0.341 | tNET | RR | 2 | R20C137[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_0_s/I1 |
| 4.020 | 0.392 | tINS | RR | 1 | R20C137[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_0_s/COUT |
| 4.020 | 0.000 | tNET | RR | 2 | R20C137[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_1_s/CIN |
| 4.056 | 0.036 | tINS | RR | 1 | R20C137[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_1_s/COUT |
| 4.056 | 0.000 | tNET | RR | 2 | R20C137[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_2_s/CIN |
| 4.231 | 0.175 | tINS | RR | 1 | R20C137[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_2_s/SUM |
| 4.340 | 0.109 | tNET | RR | 1 | R20C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n82_s1/I2 |
| 4.734 | 0.394 | tINS | RR | 2 | R20C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n82_s1/F |
| 4.738 | 0.004 | tNET | RR | 1 | R20C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n82_s0/I2 |
| 5.103 | 0.365 | tINS | RR | 5 | R20C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n82_s0/F |
| 5.472 | 0.368 | tNET | RR | 1 | R17C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_0_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.866 | 1.693 | tNET | RR | 1 | R17C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_0_s0/CLK |
| 7.642 | -0.224 | tSu | 1 | R17C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_0_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.173 |
| Logic Level | 7 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.693, 100.000% |
| Arrival Data Path Delay | cell: 2.105, 55.717%; route: 1.398, 36.994%; tC2Q: 0.275, 7.289% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.693, 100.000% |
Path43
Path Summary:
| Slack | 2.171 |
| Data Arrival Time | 5.472 |
| Data Required Time | 7.642 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_1_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.693 | 1.693 | tNET | RR | 1 | R17C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_1_s0/CLK |
| 1.969 | 0.275 | tC2Q | RR | 5 | R17C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_1_s0/Q |
| 2.097 | 0.128 | tNET | RR | 1 | R17C138[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd_g2b/rdaddr_bin_1_s0/I0 |
| 2.510 | 0.413 | tINS | RR | 4 | R17C138[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd_g2b/rdaddr_bin_1_s0/F |
| 2.958 | 0.448 | tNET | RR | 1 | R17C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd_g2b/rdaddr_bin_0_s/I1 |
| 3.286 | 0.329 | tINS | RR | 2 | R17C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd_g2b/rdaddr_bin_0_s/F |
| 3.627 | 0.341 | tNET | RR | 2 | R20C137[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_0_s/I1 |
| 4.020 | 0.392 | tINS | RR | 1 | R20C137[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_0_s/COUT |
| 4.020 | 0.000 | tNET | RR | 2 | R20C137[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_1_s/CIN |
| 4.056 | 0.036 | tINS | RR | 1 | R20C137[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_1_s/COUT |
| 4.056 | 0.000 | tNET | RR | 2 | R20C137[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_2_s/CIN |
| 4.231 | 0.175 | tINS | RR | 1 | R20C137[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdusewd_temp_2_s/SUM |
| 4.340 | 0.109 | tNET | RR | 1 | R20C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n82_s1/I2 |
| 4.734 | 0.394 | tINS | RR | 2 | R20C137[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n82_s1/F |
| 4.738 | 0.004 | tNET | RR | 1 | R20C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n82_s0/I2 |
| 5.103 | 0.365 | tINS | RR | 5 | R20C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n82_s0/F |
| 5.472 | 0.368 | tNET | RR | 1 | R17C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_1_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.866 | 1.693 | tNET | RR | 1 | R17C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_1_s0/CLK |
| 7.642 | -0.224 | tSu | 1 | R17C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/rdaddr_gray_reg_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.173 |
| Logic Level | 7 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.693, 100.000% |
| Arrival Data Path Delay | cell: 2.105, 55.717%; route: 1.398, 36.994%; tC2Q: 0.275, 7.289% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.693, 100.000% |
Path44
Path Summary:
| Slack | 2.176 |
| Data Arrival Time | 5.675 |
| Data Required Time | 7.852 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_26_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.658 | 1.693 | tNET | FF | 1 | R21C131[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n788_s4/I2 |
| 3.986 | 0.329 | tINS | FR | 2 | R21C131[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n788_s4/F |
| 4.317 | 0.331 | tNET | RR | 1 | R21C128[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n786_s3/I1 |
| 4.734 | 0.417 | tINS | RR | 5 | R21C128[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n786_s3/F |
| 5.259 | 0.525 | tNET | RR | 1 | R21C122[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n424_s2/I0 |
| 5.675 | 0.417 | tINS | RR | 1 | R21C122[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n424_s2/F |
| 5.675 | 0.000 | tNET | RR | 1 | R21C122[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_26_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.897 | 1.724 | tNET | RR | 1 | R21C122[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_26_s0/CLK |
| 7.852 | -0.046 | tSu | 1 | R21C122[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_26_s0 |
Path Statistics:
| Clock Skew | 0.024 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 1.162, 29.228%; route: 2.549, 64.116%; tC2Q: 0.265, 6.656% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.724, 100.000% |
Path45
Path Summary:
| Slack | 2.185 |
| Data Arrival Time | 5.639 |
| Data Required Time | 7.825 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_37_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.483 | 1.518 | tNET | FF | 1 | R23C131[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n594_s4/I2 |
| 3.691 | 0.208 | tINS | FR | 2 | R23C131[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n594_s4/F |
| 4.210 | 0.519 | tNET | RR | 1 | R21C126[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n594_s3/I0 |
| 4.604 | 0.394 | tINS | RR | 4 | R21C126[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n594_s3/F |
| 5.431 | 0.827 | tNET | RR | 1 | R15C122[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n413_s2/I0 |
| 5.639 | 0.208 | tINS | RR | 1 | R15C122[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n413_s2/F |
| 5.639 | 0.000 | tNET | RR | 1 | R15C122[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_37_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.870 | 1.697 | tNET | RR | 1 | R15C122[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_37_s0/CLK |
| 7.825 | -0.046 | tSu | 1 | R15C122[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp0_37_s0 |
Path Statistics:
| Clock Skew | -0.003 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 0.810, 20.562%; route: 2.865, 72.721%; tC2Q: 0.265, 6.717% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.697, 100.000% |
Path46
Path Summary:
| Slack | 2.191 |
| Data Arrival Time | 5.630 |
| Data Required Time | 7.822 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_15_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.658 | 1.693 | tNET | FF | 1 | R21C131[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n995_s4/I2 |
| 3.986 | 0.329 | tINS | FR | 2 | R21C131[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n995_s4/F |
| 4.262 | 0.276 | tNET | RR | 1 | R22C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n995_s3/I0 |
| 4.679 | 0.417 | tINS | RR | 7 | R22C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n995_s3/F |
| 5.423 | 0.743 | tNET | RR | 1 | R18C123[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n632_s2/I0 |
| 5.630 | 0.208 | tINS | RR | 1 | R18C123[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n632_s2/F |
| 5.630 | 0.000 | tNET | RR | 1 | R18C123[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_15_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.868 | 1.695 | tNET | RR | 1 | R18C123[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_15_s0/CLK |
| 7.822 | -0.046 | tSu | 1 | R18C123[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_15_s0 |
Path Statistics:
| Clock Skew | -0.005 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 0.953, 24.250%; route: 2.713, 69.018%; tC2Q: 0.265, 6.732% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.695, 100.000% |
Path47
Path Summary:
| Slack | 2.194 |
| Data Arrival Time | 5.633 |
| Data Required Time | 7.827 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_14_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.287 | 1.322 | tNET | FF | 1 | R23C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1028_s3/I2 |
| 3.495 | 0.208 | tINS | FR | 2 | R23C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1028_s3/F |
| 3.948 | 0.454 | tNET | RR | 1 | R22C127[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1028_s2/I0 |
| 4.361 | 0.413 | tINS | RR | 3 | R22C127[3][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1028_s2/F |
| 5.425 | 1.064 | tNET | RR | 1 | R17C122[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1028_s1/I0 |
| 5.633 | 0.208 | tINS | RR | 1 | R17C122[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n1028_s1/F |
| 5.633 | 0.000 | tNET | RR | 1 | R17C122[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_14_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.873 | 1.700 | tNET | RR | 1 | R17C122[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_14_s0/CLK |
| 7.827 | -0.046 | tSu | 1 | R17C122[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_14_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 0.829, 21.076%; route: 2.839, 72.197%; tC2Q: 0.265, 6.728% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
Path48
Path Summary:
| Slack | 2.195 |
| Data Arrival Time | 5.627 |
| Data Required Time | 7.822 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_62_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.483 | 1.518 | tNET | FF | 1 | R23C132[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n398_s5/I2 |
| 3.712 | 0.229 | tINS | FF | 2 | R23C132[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n398_s5/F |
| 4.010 | 0.297 | tNET | FF | 1 | R20C132[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n396_s3/I1 |
| 4.423 | 0.413 | tINS | FR | 3 | R20C132[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n396_s3/F |
| 5.419 | 0.996 | tNET | RR | 1 | R18C127[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n585_s3/I0 |
| 5.627 | 0.208 | tINS | RR | 1 | R18C127[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n585_s3/F |
| 5.627 | 0.000 | tNET | RR | 1 | R18C127[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_62_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.868 | 1.695 | tNET | RR | 1 | R18C127[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_62_s0/CLK |
| 7.822 | -0.046 | tSu | 1 | R18C127[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp1_62_s0 |
Path Statistics:
| Clock Skew | -0.005 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 0.850, 21.659%; route: 2.812, 71.602%; tC2Q: 0.265, 6.738% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.695, 100.000% |
Path49
Path Summary:
| Slack | 2.209 |
| Data Arrival Time | 5.636 |
| Data Required Time | 7.845 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_34_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.284 | 1.319 | tNET | FF | 1 | R21C134[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n994_s4/I2 |
| 3.492 | 0.208 | tINS | FR | 2 | R21C134[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n994_s4/F |
| 4.069 | 0.577 | tNET | RR | 1 | R22C130[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n992_s3/I1 |
| 4.486 | 0.417 | tINS | RR | 8 | R22C130[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n992_s3/F |
| 5.270 | 0.785 | tNET | RR | 1 | R21C123[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n810_s2/I0 |
| 5.636 | 0.365 | tINS | RR | 1 | R21C123[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n810_s2/F |
| 5.636 | 0.000 | tNET | RR | 1 | R21C123[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_34_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.891 | 1.718 | tNET | RR | 1 | R21C123[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_34_s0/CLK |
| 7.845 | -0.046 | tSu | 1 | R21C123[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp2_34_s0 |
Path Statistics:
| Clock Skew | 0.018 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 0.990, 25.154%; route: 2.681, 68.123%; tC2Q: 0.265, 6.723% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.718, 100.000% |
Path50
Path Summary:
| Slack | 2.218 |
| Data Arrival Time | 5.601 |
| Data Required Time | 7.819 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_52_s0 |
| Launch Clk | serdes_tx_clk:[R] |
| Latch Clk | serdes_tx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_tx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 1.700 | 1.700 | tNET | RR | 1 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/CLK |
| 1.965 | 0.265 | tC2Q | RF | 122 | R17C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2_1_s0/Q |
| 3.072 | 1.107 | tNET | FF | 1 | R20C134[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n990_s4/I2 |
| 3.480 | 0.409 | tINS | FR | 2 | R20C134[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n990_s4/F |
| 3.877 | 0.397 | tNET | RR | 1 | R21C130[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n990_s3/I0 |
| 4.271 | 0.394 | tINS | RR | 8 | R21C130[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n990_s3/F |
| 5.184 | 0.913 | tNET | RR | 1 | R16C125[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n990_s5/I0 |
| 5.601 | 0.417 | tINS | RR | 1 | R16C125[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/n990_s5/F |
| 5.601 | 0.000 | tNET | RR | 1 | R16C125[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_52_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.173 | 6.173 | active clock edge time | ||||
| 6.173 | 0.000 | serdes_tx_clk | ||||
| 6.173 | 0.000 | tCL | RR | 646 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_TX_O_FABRIC_CLK |
| 7.865 | 1.692 | tNET | RR | 1 | R16C125[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_52_s0/CLK |
| 7.819 | -0.046 | tSu | 1 | R16C125[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/dout_tmp3_52_s0 |
Path Statistics:
| Clock Skew | -0.008 |
| Setup Relationship | 6.173 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.700, 100.000% |
| Arrival Data Path Delay | cell: 1.219, 31.264%; route: 2.416, 61.952%; tC2Q: 0.265, 6.784% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.692, 100.000% |
Setup Analysis Report[3]:
Report Command:report_timing -setup -from_clock [get_clocks {xgmii_clk}] -to_clock [get_clocks {xgmii_clk}] -max_paths 50 -max_common_paths 1
Path1
Path Summary:
| Slack | 0.875 |
| Data Arrival Time | 10.074 |
| Data Required Time | 10.949 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_31_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.585 | 4.585 | tNET | RR | 1 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/CLK |
| 4.860 | 0.275 | tC2Q | RR | 3 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q |
| 5.599 | 0.739 | tNET | RR | 1 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/I3 |
| 5.829 | 0.229 | tINS | RF | 2 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/F |
| 6.282 | 0.453 | tNET | FF | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/I2 |
| 6.647 | 0.365 | tINS | FR | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/F |
| 6.649 | 0.002 | tNET | RR | 1 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/I0 |
| 7.065 | 0.417 | tINS | RR | 72 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/F |
| 9.866 | 2.800 | tNET | RR | 1 | R39C95[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n361_s0/I2 |
| 10.074 | 0.208 | tINS | RR | 1 | R39C95[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n361_s0/F |
| 10.074 | 0.000 | tNET | RR | 1 | R39C95[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_31_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.995 | 4.595 | tNET | RR | 1 | R39C95[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_31_s0/CLK |
| 10.949 | -0.046 | tSu | 1 | R39C95[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_31_s0 |
Path Statistics:
| Clock Skew | 0.009 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.585, 100.000% |
| Arrival Data Path Delay | cell: 1.220, 22.219%; route: 3.994, 72.764%; tC2Q: 0.275, 5.018% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.595, 100.000% |
Path2
Path Summary:
| Slack | 0.875 |
| Data Arrival Time | 10.074 |
| Data Required Time | 10.949 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_63_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.585 | 4.585 | tNET | RR | 1 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/CLK |
| 4.860 | 0.275 | tC2Q | RR | 3 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q |
| 5.599 | 0.739 | tNET | RR | 1 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/I3 |
| 5.829 | 0.229 | tINS | RF | 2 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/F |
| 6.282 | 0.453 | tNET | FF | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/I2 |
| 6.647 | 0.365 | tINS | FR | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/F |
| 6.649 | 0.002 | tNET | RR | 1 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/I0 |
| 7.065 | 0.417 | tINS | RR | 72 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/F |
| 9.866 | 2.800 | tNET | RR | 1 | R39C95[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n329_s0/I2 |
| 10.074 | 0.208 | tINS | RR | 1 | R39C95[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n329_s0/F |
| 10.074 | 0.000 | tNET | RR | 1 | R39C95[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_63_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.995 | 4.595 | tNET | RR | 1 | R39C95[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_63_s0/CLK |
| 10.949 | -0.046 | tSu | 1 | R39C95[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_63_s0 |
Path Statistics:
| Clock Skew | 0.009 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.585, 100.000% |
| Arrival Data Path Delay | cell: 1.220, 22.219%; route: 3.994, 72.764%; tC2Q: 0.275, 5.018% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.595, 100.000% |
Path3
Path Summary:
| Slack | 0.876 |
| Data Arrival Time | 10.079 |
| Data Required Time | 10.955 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_44_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.585 | 4.585 | tNET | RR | 1 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/CLK |
| 4.860 | 0.275 | tC2Q | RR | 3 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q |
| 5.599 | 0.739 | tNET | RR | 1 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/I3 |
| 5.829 | 0.229 | tINS | RF | 2 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/F |
| 6.282 | 0.453 | tNET | FF | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/I2 |
| 6.647 | 0.365 | tINS | FR | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/F |
| 6.649 | 0.002 | tNET | RR | 1 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/I0 |
| 7.065 | 0.417 | tINS | RR | 72 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/F |
| 9.714 | 2.648 | tNET | RR | 1 | R39C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n348_s0/I2 |
| 10.079 | 0.365 | tINS | RR | 1 | R39C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n348_s0/F |
| 10.079 | 0.000 | tNET | RR | 1 | R39C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_44_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 11.001 | 4.601 | tNET | RR | 1 | R39C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_44_s0/CLK |
| 10.955 | -0.046 | tSu | 1 | R39C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_44_s0 |
Path Statistics:
| Clock Skew | 0.016 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.585, 100.000% |
| Arrival Data Path Delay | cell: 1.377, 25.063%; route: 3.842, 69.924%; tC2Q: 0.275, 5.013% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.601, 100.000% |
Path4
Path Summary:
| Slack | 0.878 |
| Data Arrival Time | 10.056 |
| Data Required Time | 10.934 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_21_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.555 | 4.555 | tNET | RR | 1 | R12C103[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/CLK |
| 4.830 | 0.275 | tC2Q | RR | 47 | R12C103[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/Q |
| 6.901 | 2.071 | tNET | RR | 1 | R6C97[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6879_s9/I2 |
| 7.310 | 0.409 | tINS | RR | 9 | R6C97[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6879_s9/F |
| 8.384 | 1.074 | tNET | RR | 1 | R9C105[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6748_s5/I2 |
| 8.792 | 0.409 | tINS | RR | 1 | R9C105[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6748_s5/F |
| 8.792 | 0.000 | tNET | RR | 1 | R9C105[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6748_s3/I0 |
| 8.900 | 0.108 | tINS | RR | 1 | R9C105[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6748_s3/O |
| 9.224 | 0.324 | tNET | RR | 1 | R11C105[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6928_s6/I1 |
| 9.641 | 0.417 | tINS | RR | 1 | R11C105[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6928_s6/F |
| 9.643 | 0.002 | tNET | RR | 1 | R11C105[3][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6928_s5/I2 |
| 10.056 | 0.413 | tINS | RR | 1 | R11C105[3][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6928_s5/F |
| 10.056 | 0.000 | tNET | RR | 1 | R11C105[3][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_21_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.980 | 4.580 | tNET | RR | 1 | R11C105[3][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_21_s0/CLK |
| 10.934 | -0.046 | tSu | 1 | R11C105[3][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_21_s0 |
Path Statistics:
| Clock Skew | 0.025 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.555, 100.000% |
| Arrival Data Path Delay | cell: 1.755, 31.902%; route: 3.471, 63.092%; tC2Q: 0.275, 5.006% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.580, 100.000% |
Path5
Path Summary:
| Slack | 0.892 |
| Data Arrival Time | 10.031 |
| Data Required Time | 10.923 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_4_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.585 | 4.585 | tNET | RR | 1 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/CLK |
| 4.860 | 0.275 | tC2Q | RR | 3 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q |
| 5.599 | 0.739 | tNET | RR | 1 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/I3 |
| 5.829 | 0.229 | tINS | RF | 2 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/F |
| 6.282 | 0.453 | tNET | FF | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/I2 |
| 6.647 | 0.365 | tINS | FR | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/F |
| 6.649 | 0.002 | tNET | RR | 1 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/I0 |
| 7.065 | 0.417 | tINS | RR | 72 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/F |
| 9.665 | 2.600 | tNET | RR | 1 | R34C95[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n388_s0/I2 |
| 10.031 | 0.365 | tINS | RR | 1 | R34C95[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n388_s0/F |
| 10.031 | 0.000 | tNET | RR | 1 | R34C95[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_4_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.969 | 4.569 | tNET | RR | 1 | R34C95[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_4_s0/CLK |
| 10.923 | -0.046 | tSu | 1 | R34C95[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_4_s0 |
Path Statistics:
| Clock Skew | -0.016 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.585, 100.000% |
| Arrival Data Path Delay | cell: 1.377, 25.287%; route: 3.793, 69.655%; tC2Q: 0.275, 5.057% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.569, 100.000% |
Path6
Path Summary:
| Slack | 0.892 |
| Data Arrival Time | 10.031 |
| Data Required Time | 10.923 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_26_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.585 | 4.585 | tNET | RR | 1 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/CLK |
| 4.860 | 0.275 | tC2Q | RR | 3 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q |
| 5.599 | 0.739 | tNET | RR | 1 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/I3 |
| 5.829 | 0.229 | tINS | RF | 2 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/F |
| 6.282 | 0.453 | tNET | FF | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/I2 |
| 6.647 | 0.365 | tINS | FR | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/F |
| 6.649 | 0.002 | tNET | RR | 1 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/I0 |
| 7.065 | 0.417 | tINS | RR | 72 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/F |
| 9.665 | 2.600 | tNET | RR | 1 | R34C95[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n366_s0/I2 |
| 10.031 | 0.365 | tINS | RR | 1 | R34C95[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n366_s0/F |
| 10.031 | 0.000 | tNET | RR | 1 | R34C95[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_26_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.969 | 4.569 | tNET | RR | 1 | R34C95[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_26_s0/CLK |
| 10.923 | -0.046 | tSu | 1 | R34C95[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_26_s0 |
Path Statistics:
| Clock Skew | -0.016 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.585, 100.000% |
| Arrival Data Path Delay | cell: 1.377, 25.287%; route: 3.793, 69.655%; tC2Q: 0.275, 5.057% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.569, 100.000% |
Path7
Path Summary:
| Slack | 0.892 |
| Data Arrival Time | 10.031 |
| Data Required Time | 10.923 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_58_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.585 | 4.585 | tNET | RR | 1 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/CLK |
| 4.860 | 0.275 | tC2Q | RR | 3 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q |
| 5.599 | 0.739 | tNET | RR | 1 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/I3 |
| 5.829 | 0.229 | tINS | RF | 2 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/F |
| 6.282 | 0.453 | tNET | FF | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/I2 |
| 6.647 | 0.365 | tINS | FR | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/F |
| 6.649 | 0.002 | tNET | RR | 1 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/I0 |
| 7.065 | 0.417 | tINS | RR | 72 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/F |
| 9.665 | 2.600 | tNET | RR | 1 | R34C95[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n334_s0/I2 |
| 10.031 | 0.365 | tINS | RR | 1 | R34C95[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n334_s0/F |
| 10.031 | 0.000 | tNET | RR | 1 | R34C95[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_58_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.969 | 4.569 | tNET | RR | 1 | R34C95[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_58_s0/CLK |
| 10.923 | -0.046 | tSu | 1 | R34C95[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_58_s0 |
Path Statistics:
| Clock Skew | -0.016 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.585, 100.000% |
| Arrival Data Path Delay | cell: 1.377, 25.287%; route: 3.793, 69.655%; tC2Q: 0.275, 5.057% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.569, 100.000% |
Path8
Path Summary:
| Slack | 0.894 |
| Data Arrival Time | 10.031 |
| Data Required Time | 10.924 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_33_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.585 | 4.585 | tNET | RR | 1 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/CLK |
| 4.860 | 0.275 | tC2Q | RR | 3 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q |
| 5.599 | 0.739 | tNET | RR | 1 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/I3 |
| 5.829 | 0.229 | tINS | RF | 2 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/F |
| 6.282 | 0.453 | tNET | FF | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/I2 |
| 6.647 | 0.365 | tINS | FR | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/F |
| 6.649 | 0.002 | tNET | RR | 1 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/I0 |
| 7.065 | 0.417 | tINS | RR | 72 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/F |
| 9.665 | 2.600 | tNET | RR | 1 | R35C95[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n359_s0/I2 |
| 10.031 | 0.365 | tINS | RR | 1 | R35C95[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n359_s0/F |
| 10.031 | 0.000 | tNET | RR | 1 | R35C95[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_33_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.970 | 4.570 | tNET | RR | 1 | R35C95[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_33_s0/CLK |
| 10.924 | -0.046 | tSu | 1 | R35C95[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_33_s0 |
Path Statistics:
| Clock Skew | -0.015 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.585, 100.000% |
| Arrival Data Path Delay | cell: 1.377, 25.287%; route: 3.793, 69.655%; tC2Q: 0.275, 5.057% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.570, 100.000% |
Path9
Path Summary:
| Slack | 0.913 |
| Data Arrival Time | 10.042 |
| Data Required Time | 10.955 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_12_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.585 | 4.585 | tNET | RR | 1 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/CLK |
| 4.860 | 0.275 | tC2Q | RR | 3 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q |
| 5.599 | 0.739 | tNET | RR | 1 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/I3 |
| 5.829 | 0.229 | tINS | RF | 2 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/F |
| 6.282 | 0.453 | tNET | FF | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/I2 |
| 6.647 | 0.365 | tINS | FR | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/F |
| 6.649 | 0.002 | tNET | RR | 1 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/I0 |
| 7.065 | 0.417 | tINS | RR | 72 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/F |
| 9.714 | 2.648 | tNET | RR | 1 | R39C94[3][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n380_s0/I2 |
| 10.042 | 0.329 | tINS | RR | 1 | R39C94[3][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n380_s0/F |
| 10.042 | 0.000 | tNET | RR | 1 | R39C94[3][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_12_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 11.001 | 4.601 | tNET | RR | 1 | R39C94[3][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_12_s0/CLK |
| 10.955 | -0.046 | tSu | 1 | R39C94[3][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_12_s0 |
Path Statistics:
| Clock Skew | 0.016 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.585, 100.000% |
| Arrival Data Path Delay | cell: 1.340, 24.557%; route: 3.842, 70.397%; tC2Q: 0.275, 5.047% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.601, 100.000% |
Path10
Path Summary:
| Slack | 1.022 |
| Data Arrival Time | 9.915 |
| Data Required Time | 10.938 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_28_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.585 | 4.585 | tNET | RR | 1 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/CLK |
| 4.860 | 0.275 | tC2Q | RR | 3 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q |
| 5.599 | 0.739 | tNET | RR | 1 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/I3 |
| 5.829 | 0.229 | tINS | RF | 2 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/F |
| 6.282 | 0.453 | tNET | FF | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/I2 |
| 6.647 | 0.365 | tINS | FR | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/F |
| 6.649 | 0.002 | tNET | RR | 1 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/I0 |
| 7.065 | 0.417 | tINS | RR | 72 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/F |
| 9.499 | 2.433 | tNET | RR | 1 | R35C93[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n364_s0/I2 |
| 9.915 | 0.417 | tINS | RR | 1 | R35C93[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n364_s0/F |
| 9.915 | 0.000 | tNET | RR | 1 | R35C93[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_28_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.984 | 4.584 | tNET | RR | 1 | R35C93[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_28_s0/CLK |
| 10.938 | -0.046 | tSu | 1 | R35C93[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_28_s0 |
Path Statistics:
| Clock Skew | -0.001 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.585, 100.000% |
| Arrival Data Path Delay | cell: 1.428, 26.796%; route: 3.627, 68.037%; tC2Q: 0.275, 5.167% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.584, 100.000% |
Path11
Path Summary:
| Slack | 1.022 |
| Data Arrival Time | 9.915 |
| Data Required Time | 10.938 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_60_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.585 | 4.585 | tNET | RR | 1 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/CLK |
| 4.860 | 0.275 | tC2Q | RR | 3 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q |
| 5.599 | 0.739 | tNET | RR | 1 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/I3 |
| 5.829 | 0.229 | tINS | RF | 2 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/F |
| 6.282 | 0.453 | tNET | FF | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/I2 |
| 6.647 | 0.365 | tINS | FR | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/F |
| 6.649 | 0.002 | tNET | RR | 1 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/I0 |
| 7.065 | 0.417 | tINS | RR | 72 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/F |
| 9.499 | 2.433 | tNET | RR | 1 | R35C93[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n332_s0/I2 |
| 9.915 | 0.417 | tINS | RR | 1 | R35C93[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n332_s0/F |
| 9.915 | 0.000 | tNET | RR | 1 | R35C93[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_60_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.984 | 4.584 | tNET | RR | 1 | R35C93[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_60_s0/CLK |
| 10.938 | -0.046 | tSu | 1 | R35C93[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_60_s0 |
Path Statistics:
| Clock Skew | -0.001 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.585, 100.000% |
| Arrival Data Path Delay | cell: 1.428, 26.796%; route: 3.627, 68.037%; tC2Q: 0.275, 5.167% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.584, 100.000% |
Path12
Path Summary:
| Slack | 1.047 |
| Data Arrival Time | 9.875 |
| Data Required Time | 10.922 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_1_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.585 | 4.585 | tNET | RR | 1 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/CLK |
| 4.860 | 0.275 | tC2Q | RR | 3 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q |
| 5.599 | 0.739 | tNET | RR | 1 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/I3 |
| 5.829 | 0.229 | tINS | RF | 2 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/F |
| 6.282 | 0.453 | tNET | FF | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/I2 |
| 6.647 | 0.365 | tINS | FR | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/F |
| 6.649 | 0.002 | tNET | RR | 1 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/I0 |
| 7.065 | 0.417 | tINS | RR | 72 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/F |
| 9.509 | 2.444 | tNET | RR | 1 | R33C95[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n391_s0/I2 |
| 9.875 | 0.365 | tINS | RR | 1 | R33C95[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n391_s0/F |
| 9.875 | 0.000 | tNET | RR | 1 | R33C95[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_1_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.968 | 4.568 | tNET | RR | 1 | R33C95[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_1_s0/CLK |
| 10.922 | -0.046 | tSu | 1 | R33C95[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_1_s0 |
Path Statistics:
| Clock Skew | -0.018 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.585, 100.000% |
| Arrival Data Path Delay | cell: 1.377, 26.031%; route: 3.637, 68.762%; tC2Q: 0.275, 5.206% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.568, 100.000% |
Path13
Path Summary:
| Slack | 1.047 |
| Data Arrival Time | 9.875 |
| Data Required Time | 10.922 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_36_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.585 | 4.585 | tNET | RR | 1 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/CLK |
| 4.860 | 0.275 | tC2Q | RR | 3 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q |
| 5.599 | 0.739 | tNET | RR | 1 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/I3 |
| 5.829 | 0.229 | tINS | RF | 2 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/F |
| 6.282 | 0.453 | tNET | FF | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/I2 |
| 6.647 | 0.365 | tINS | FR | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/F |
| 6.649 | 0.002 | tNET | RR | 1 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/I0 |
| 7.065 | 0.417 | tINS | RR | 72 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/F |
| 9.509 | 2.444 | tNET | RR | 1 | R33C95[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n356_s0/I2 |
| 9.875 | 0.365 | tINS | RR | 1 | R33C95[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n356_s0/F |
| 9.875 | 0.000 | tNET | RR | 1 | R33C95[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_36_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.968 | 4.568 | tNET | RR | 1 | R33C95[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_36_s0/CLK |
| 10.922 | -0.046 | tSu | 1 | R33C95[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_36_s0 |
Path Statistics:
| Clock Skew | -0.018 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.585, 100.000% |
| Arrival Data Path Delay | cell: 1.377, 26.031%; route: 3.637, 68.762%; tC2Q: 0.275, 5.206% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.568, 100.000% |
Path14
Path Summary:
| Slack | 1.047 |
| Data Arrival Time | 9.875 |
| Data Required Time | 10.922 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxc_align_reg_2_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.585 | 4.585 | tNET | RR | 1 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/CLK |
| 4.860 | 0.275 | tC2Q | RR | 3 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q |
| 5.599 | 0.739 | tNET | RR | 1 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/I3 |
| 5.829 | 0.229 | tINS | RF | 2 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/F |
| 6.282 | 0.453 | tNET | FF | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/I2 |
| 6.647 | 0.365 | tINS | FR | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/F |
| 6.649 | 0.002 | tNET | RR | 1 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/I0 |
| 7.065 | 0.417 | tINS | RR | 72 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/F |
| 9.509 | 2.444 | tNET | RR | 1 | R33C95[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n326_s0/I2 |
| 9.875 | 0.365 | tINS | RR | 1 | R33C95[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n326_s0/F |
| 9.875 | 0.000 | tNET | RR | 1 | R33C95[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxc_align_reg_2_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.968 | 4.568 | tNET | RR | 1 | R33C95[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxc_align_reg_2_s0/CLK |
| 10.922 | -0.046 | tSu | 1 | R33C95[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxc_align_reg_2_s0 |
Path Statistics:
| Clock Skew | -0.018 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.585, 100.000% |
| Arrival Data Path Delay | cell: 1.377, 26.031%; route: 3.637, 68.762%; tC2Q: 0.275, 5.206% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.568, 100.000% |
Path15
Path Summary:
| Slack | 1.054 |
| Data Arrival Time | 9.875 |
| Data Required Time | 10.928 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_9_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.585 | 4.585 | tNET | RR | 1 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/CLK |
| 4.860 | 0.275 | tC2Q | RR | 3 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q |
| 5.599 | 0.739 | tNET | RR | 1 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/I3 |
| 5.829 | 0.229 | tINS | RF | 2 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/F |
| 6.282 | 0.453 | tNET | FF | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/I2 |
| 6.647 | 0.365 | tINS | FR | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/F |
| 6.649 | 0.002 | tNET | RR | 1 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/I0 |
| 7.065 | 0.417 | tINS | RR | 72 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/F |
| 9.509 | 2.444 | tNET | RR | 1 | R33C94[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n383_s0/I2 |
| 9.875 | 0.365 | tINS | RR | 1 | R33C94[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n383_s0/F |
| 9.875 | 0.000 | tNET | RR | 1 | R33C94[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_9_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.974 | 4.574 | tNET | RR | 1 | R33C94[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_9_s0/CLK |
| 10.928 | -0.046 | tSu | 1 | R33C94[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_9_s0 |
Path Statistics:
| Clock Skew | -0.011 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.585, 100.000% |
| Arrival Data Path Delay | cell: 1.377, 26.031%; route: 3.637, 68.762%; tC2Q: 0.275, 5.206% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.574, 100.000% |
Path16
Path Summary:
| Slack | 1.054 |
| Data Arrival Time | 9.875 |
| Data Required Time | 10.928 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_41_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.585 | 4.585 | tNET | RR | 1 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/CLK |
| 4.860 | 0.275 | tC2Q | RR | 3 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q |
| 5.599 | 0.739 | tNET | RR | 1 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/I3 |
| 5.829 | 0.229 | tINS | RF | 2 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/F |
| 6.282 | 0.453 | tNET | FF | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/I2 |
| 6.647 | 0.365 | tINS | FR | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/F |
| 6.649 | 0.002 | tNET | RR | 1 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/I0 |
| 7.065 | 0.417 | tINS | RR | 72 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/F |
| 9.509 | 2.444 | tNET | RR | 1 | R33C94[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n351_s0/I2 |
| 9.875 | 0.365 | tINS | RR | 1 | R33C94[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n351_s0/F |
| 9.875 | 0.000 | tNET | RR | 1 | R33C94[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_41_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.974 | 4.574 | tNET | RR | 1 | R33C94[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_41_s0/CLK |
| 10.928 | -0.046 | tSu | 1 | R33C94[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_41_s0 |
Path Statistics:
| Clock Skew | -0.011 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.585, 100.000% |
| Arrival Data Path Delay | cell: 1.377, 26.031%; route: 3.637, 68.762%; tC2Q: 0.275, 5.206% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.574, 100.000% |
Path17
Path Summary:
| Slack | 1.081 |
| Data Arrival Time | 9.863 |
| Data Required Time | 10.945 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_16_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.555 | 4.555 | tNET | RR | 1 | R12C103[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/CLK |
| 4.830 | 0.275 | tC2Q | RR | 47 | R12C103[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/Q |
| 6.901 | 2.071 | tNET | RR | 1 | R6C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6746_s6/I1 |
| 7.315 | 0.413 | tINS | RR | 1 | R6C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6746_s6/F |
| 7.316 | 0.002 | tNET | RR | 1 | R6C97[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6753_s5/I2 |
| 7.733 | 0.417 | tINS | RR | 28 | R6C97[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6753_s5/F |
| 8.512 | 0.779 | tNET | RR | 1 | R13C104[3][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6753_s3/S0 |
| 8.693 | 0.182 | tINS | RR | 1 | R13C104[3][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6753_s3/O |
| 9.265 | 0.571 | tNET | RR | 1 | R9C101[3][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6933_s6/I1 |
| 9.494 | 0.229 | tINS | RF | 1 | R9C101[3][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6933_s6/F |
| 9.498 | 0.004 | tNET | FF | 1 | R9C101[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6933_s5/I2 |
| 9.863 | 0.365 | tINS | FR | 1 | R9C101[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6933_s5/F |
| 9.863 | 0.000 | tNET | RR | 1 | R9C101[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_16_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.990 | 4.590 | tNET | RR | 1 | R9C101[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_16_s0/CLK |
| 10.945 | -0.046 | tSu | 1 | R9C101[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_16_s0 |
Path Statistics:
| Clock Skew | 0.036 |
| Setup Relationship | 6.400 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.555, 100.000% |
| Arrival Data Path Delay | cell: 1.607, 30.262%; route: 3.427, 64.550%; tC2Q: 0.275, 5.188% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.590, 100.000% |
Path18
Path Summary:
| Slack | 1.084 |
| Data Arrival Time | 9.838 |
| Data Required Time | 10.922 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxc_align_reg_6_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.585 | 4.585 | tNET | RR | 1 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/CLK |
| 4.860 | 0.275 | tC2Q | RR | 3 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q |
| 5.599 | 0.739 | tNET | RR | 1 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/I3 |
| 5.829 | 0.229 | tINS | RF | 2 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/F |
| 6.282 | 0.453 | tNET | FF | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/I2 |
| 6.647 | 0.365 | tINS | FR | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/F |
| 6.649 | 0.002 | tNET | RR | 1 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/I0 |
| 7.065 | 0.417 | tINS | RR | 72 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/F |
| 9.509 | 2.444 | tNET | RR | 1 | R33C95[3][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n322_s0/I2 |
| 9.838 | 0.329 | tINS | RR | 1 | R33C95[3][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n322_s0/F |
| 9.838 | 0.000 | tNET | RR | 1 | R33C95[3][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxc_align_reg_6_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.968 | 4.568 | tNET | RR | 1 | R33C95[3][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxc_align_reg_6_s0/CLK |
| 10.922 | -0.046 | tSu | 1 | R33C95[3][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxc_align_reg_6_s0 |
Path Statistics:
| Clock Skew | -0.018 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.585, 100.000% |
| Arrival Data Path Delay | cell: 1.340, 25.512%; route: 3.637, 69.245%; tC2Q: 0.275, 5.243% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.568, 100.000% |
Path19
Path Summary:
| Slack | 1.133 |
| Data Arrival Time | 9.780 |
| Data Required Time | 10.913 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_17_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.555 | 4.555 | tNET | RR | 1 | R12C103[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/CLK |
| 4.830 | 0.275 | tC2Q | RR | 47 | R12C103[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/Q |
| 6.901 | 2.071 | tNET | RR | 1 | R6C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6746_s6/I1 |
| 7.315 | 0.413 | tINS | RR | 1 | R6C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6746_s6/F |
| 7.316 | 0.002 | tNET | RR | 1 | R6C97[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6753_s5/I2 |
| 7.733 | 0.417 | tINS | RR | 28 | R6C97[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6753_s5/F |
| 8.029 | 0.296 | tNET | RR | 1 | R6C96[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6752_s3/S0 |
| 8.211 | 0.182 | tINS | RR | 1 | R6C96[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6752_s3/O |
| 8.918 | 0.707 | tNET | RR | 1 | R13C96[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6932_s6/I1 |
| 9.247 | 0.329 | tINS | RR | 1 | R13C96[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6932_s6/F |
| 9.371 | 0.124 | tNET | RR | 1 | R13C95[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6932_s5/I2 |
| 9.780 | 0.409 | tINS | RR | 1 | R13C95[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6932_s5/F |
| 9.780 | 0.000 | tNET | RR | 1 | R13C95[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_17_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.959 | 4.559 | tNET | RR | 1 | R13C95[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_17_s0/CLK |
| 10.913 | -0.046 | tSu | 1 | R13C95[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_17_s0 |
Path Statistics:
| Clock Skew | 0.004 |
| Setup Relationship | 6.400 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.555, 100.000% |
| Arrival Data Path Delay | cell: 1.749, 33.468%; route: 3.201, 61.261%; tC2Q: 0.275, 5.271% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.559, 100.000% |
Path20
Path Summary:
| Slack | 1.149 |
| Data Arrival Time | 9.789 |
| Data Required Time | 10.938 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_19_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.555 | 4.555 | tNET | RR | 1 | R12C103[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/CLK |
| 4.830 | 0.275 | tC2Q | RR | 47 | R12C103[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/Q |
| 6.901 | 2.071 | tNET | RR | 1 | R6C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6746_s6/I1 |
| 7.315 | 0.413 | tINS | RR | 1 | R6C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6746_s6/F |
| 7.316 | 0.002 | tNET | RR | 1 | R6C97[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6753_s5/I2 |
| 7.733 | 0.417 | tINS | RR | 28 | R6C97[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6753_s5/F |
| 8.027 | 0.294 | tNET | RR | 1 | R7C96[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6750_s3/S0 |
| 8.209 | 0.182 | tINS | RR | 1 | R7C96[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6750_s3/O |
| 8.769 | 0.560 | tNET | RR | 1 | R8C96[3][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6930_s6/I1 |
| 9.097 | 0.329 | tINS | RR | 1 | R8C96[3][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6930_s6/F |
| 9.372 | 0.275 | tNET | RR | 1 | R9C94[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6930_s5/I2 |
| 9.789 | 0.417 | tINS | RR | 1 | R9C94[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6930_s5/F |
| 9.789 | 0.000 | tNET | RR | 1 | R9C94[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_19_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.984 | 4.584 | tNET | RR | 1 | R9C94[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_19_s0/CLK |
| 10.938 | -0.046 | tSu | 1 | R9C94[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_19_s0 |
Path Statistics:
| Clock Skew | 0.029 |
| Setup Relationship | 6.400 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.555, 100.000% |
| Arrival Data Path Delay | cell: 1.757, 33.565%; route: 3.202, 61.173%; tC2Q: 0.275, 5.262% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.584, 100.000% |
Path21
Path Summary:
| Slack | 1.168 |
| Data Arrival Time | 9.763 |
| Data Required Time | 10.931 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_20_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.585 | 4.585 | tNET | RR | 1 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/CLK |
| 4.860 | 0.275 | tC2Q | RR | 3 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q |
| 5.599 | 0.739 | tNET | RR | 1 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/I3 |
| 5.829 | 0.229 | tINS | RF | 2 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/F |
| 6.282 | 0.453 | tNET | FF | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/I2 |
| 6.647 | 0.365 | tINS | FR | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/F |
| 6.649 | 0.002 | tNET | RR | 1 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/I0 |
| 7.065 | 0.417 | tINS | RR | 72 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/F |
| 9.347 | 2.281 | tNET | RR | 1 | R35C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n372_s0/I2 |
| 9.763 | 0.417 | tINS | RR | 1 | R35C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n372_s0/F |
| 9.763 | 0.000 | tNET | RR | 1 | R35C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_20_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.977 | 4.577 | tNET | RR | 1 | R35C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_20_s0/CLK |
| 10.931 | -0.046 | tSu | 1 | R35C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_20_s0 |
Path Statistics:
| Clock Skew | -0.008 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.585, 100.000% |
| Arrival Data Path Delay | cell: 1.428, 27.583%; route: 3.474, 67.098%; tC2Q: 0.275, 5.319% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.577, 100.000% |
Path22
Path Summary:
| Slack | 1.168 |
| Data Arrival Time | 9.763 |
| Data Required Time | 10.931 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_52_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.585 | 4.585 | tNET | RR | 1 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/CLK |
| 4.860 | 0.275 | tC2Q | RR | 3 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q |
| 5.599 | 0.739 | tNET | RR | 1 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/I3 |
| 5.829 | 0.229 | tINS | RF | 2 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/F |
| 6.282 | 0.453 | tNET | FF | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/I2 |
| 6.647 | 0.365 | tINS | FR | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/F |
| 6.649 | 0.002 | tNET | RR | 1 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/I0 |
| 7.065 | 0.417 | tINS | RR | 72 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/F |
| 9.347 | 2.281 | tNET | RR | 1 | R35C94[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n340_s0/I2 |
| 9.763 | 0.417 | tINS | RR | 1 | R35C94[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n340_s0/F |
| 9.763 | 0.000 | tNET | RR | 1 | R35C94[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_52_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.977 | 4.577 | tNET | RR | 1 | R35C94[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_52_s0/CLK |
| 10.931 | -0.046 | tSu | 1 | R35C94[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_52_s0 |
Path Statistics:
| Clock Skew | -0.008 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.585, 100.000% |
| Arrival Data Path Delay | cell: 1.428, 27.583%; route: 3.474, 67.098%; tC2Q: 0.275, 5.319% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.577, 100.000% |
Path23
Path Summary:
| Slack | 1.215 |
| Data Arrival Time | 9.714 |
| Data Required Time | 10.928 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_23_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.585 | 4.585 | tNET | RR | 1 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/CLK |
| 4.860 | 0.275 | tC2Q | RR | 3 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q |
| 5.599 | 0.739 | tNET | RR | 1 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/I3 |
| 5.829 | 0.229 | tINS | RF | 2 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/F |
| 6.282 | 0.453 | tNET | FF | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/I2 |
| 6.647 | 0.365 | tINS | FR | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/F |
| 6.649 | 0.002 | tNET | RR | 1 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/I0 |
| 7.065 | 0.417 | tINS | RR | 72 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/F |
| 9.348 | 2.283 | tNET | RR | 1 | R33C96[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n369_s0/I2 |
| 9.714 | 0.365 | tINS | RR | 1 | R33C96[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n369_s0/F |
| 9.714 | 0.000 | tNET | RR | 1 | R33C96[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_23_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.974 | 4.574 | tNET | RR | 1 | R33C96[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_23_s0/CLK |
| 10.928 | -0.046 | tSu | 1 | R33C96[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_23_s0 |
Path Statistics:
| Clock Skew | -0.011 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.585, 100.000% |
| Arrival Data Path Delay | cell: 1.377, 26.849%; route: 3.476, 67.781%; tC2Q: 0.275, 5.370% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.574, 100.000% |
Path24
Path Summary:
| Slack | 1.247 |
| Data Arrival Time | 9.662 |
| Data Required Time | 10.909 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_12_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.555 | 4.555 | tNET | RR | 1 | R12C103[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/CLK |
| 4.830 | 0.275 | tC2Q | RR | 47 | R12C103[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/Q |
| 6.901 | 2.071 | tNET | RR | 1 | R6C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6746_s6/I1 |
| 7.315 | 0.413 | tINS | RR | 1 | R6C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6746_s6/F |
| 7.316 | 0.002 | tNET | RR | 1 | R6C97[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6753_s5/I2 |
| 7.733 | 0.417 | tINS | RR | 28 | R6C97[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6753_s5/F |
| 8.814 | 1.081 | tNET | RR | 1 | R11C105[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6937_s7/I2 |
| 9.179 | 0.365 | tINS | RR | 1 | R11C105[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6937_s7/F |
| 9.454 | 0.275 | tNET | RR | 1 | R12C107[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6937_s5/I1 |
| 9.662 | 0.208 | tINS | RR | 1 | R12C107[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6937_s5/F |
| 9.662 | 0.000 | tNET | RR | 1 | R12C107[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_12_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.955 | 4.555 | tNET | RR | 1 | R12C107[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_12_s0/CLK |
| 10.909 | -0.046 | tSu | 1 | R12C107[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_12_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.555, 100.000% |
| Arrival Data Path Delay | cell: 1.403, 27.474%; route: 3.429, 67.134%; tC2Q: 0.275, 5.393% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.555, 100.000% |
Path25
Path Summary:
| Slack | 1.274 |
| Data Arrival Time | 9.644 |
| Data Required Time | 10.917 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_22_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.555 | 4.555 | tNET | RR | 1 | R12C103[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/CLK |
| 4.830 | 0.275 | tC2Q | RR | 47 | R12C103[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/Q |
| 6.901 | 2.071 | tNET | RR | 1 | R6C97[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6879_s9/I2 |
| 7.310 | 0.409 | tINS | RR | 9 | R6C97[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6879_s9/F |
| 8.107 | 0.797 | tNET | RR | 1 | R14C97[3][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6747_s5/I2 |
| 8.521 | 0.413 | tINS | RR | 1 | R14C97[3][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6747_s5/F |
| 8.521 | 0.000 | tNET | RR | 1 | R14C97[3][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6747_s3/I0 |
| 8.629 | 0.108 | tINS | RR | 1 | R14C97[3][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6747_s3/O |
| 8.903 | 0.275 | tNET | RR | 1 | R14C96[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6927_s6/I1 |
| 9.111 | 0.208 | tINS | RR | 1 | R14C96[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6927_s6/F |
| 9.235 | 0.124 | tNET | RR | 1 | R14C95[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6927_s5/I2 |
| 9.644 | 0.409 | tINS | RR | 1 | R14C95[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6927_s5/F |
| 9.644 | 0.000 | tNET | RR | 1 | R14C95[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_22_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.963 | 4.563 | tNET | RR | 1 | R14C95[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_22_s0/CLK |
| 10.917 | -0.046 | tSu | 1 | R14C95[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_22_s0 |
Path Statistics:
| Clock Skew | 0.009 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.555, 100.000% |
| Arrival Data Path Delay | cell: 1.546, 30.383%; route: 3.267, 64.205%; tC2Q: 0.275, 5.412% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.563, 100.000% |
Path26
Path Summary:
| Slack | 1.321 |
| Data Arrival Time | 9.634 |
| Data Required Time | 10.955 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_23_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.555 | 4.555 | tNET | RR | 1 | R12C103[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/CLK |
| 4.830 | 0.275 | tC2Q | RR | 47 | R12C103[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/Q |
| 6.901 | 2.071 | tNET | RR | 1 | R6C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6746_s6/I1 |
| 7.315 | 0.413 | tINS | RR | 1 | R6C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6746_s6/F |
| 7.316 | 0.002 | tNET | RR | 1 | R6C97[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6753_s5/I2 |
| 7.733 | 0.417 | tINS | RR | 28 | R6C97[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6753_s5/F |
| 8.587 | 0.854 | tNET | RR | 1 | R6C102[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6746_s3/S0 |
| 8.769 | 0.182 | tINS | RR | 1 | R6C102[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6746_s3/O |
| 8.893 | 0.124 | tNET | RR | 1 | R6C101[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6926_s6/I1 |
| 9.101 | 0.208 | tINS | RR | 1 | R6C101[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6926_s6/F |
| 9.225 | 0.124 | tNET | RR | 1 | R7C101[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6926_s5/I2 |
| 9.634 | 0.409 | tINS | RR | 1 | R7C101[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6926_s5/F |
| 9.634 | 0.000 | tNET | RR | 1 | R7C101[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_23_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 11.001 | 4.601 | tNET | RR | 1 | R7C101[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_23_s0/CLK |
| 10.955 | -0.046 | tSu | 1 | R7C101[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_23_s0 |
Path Statistics:
| Clock Skew | 0.046 |
| Setup Relationship | 6.400 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.555, 100.000% |
| Arrival Data Path Delay | cell: 1.628, 32.055%; route: 3.176, 62.523%; tC2Q: 0.275, 5.422% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.601, 100.000% |
Path27
Path Summary:
| Slack | 1.338 |
| Data Arrival Time | 9.614 |
| Data Required Time | 10.952 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/cal_crc_64bit_20_s1 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/cal_crc_64bit_29_s1 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.595 | 4.595 | tNET | RR | 1 | R3C111[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/cal_crc_64bit_20_s1/CLK |
| 4.870 | 0.275 | tC2Q | RR | 9 | R3C111[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/cal_crc_64bit_20_s1/Q |
| 5.944 | 1.074 | tNET | RR | 1 | R7C108[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n3456_s5/I1 |
| 6.360 | 0.417 | tINS | RR | 4 | R7C108[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n3456_s5/F |
| 6.486 | 0.126 | tNET | RR | 1 | R7C109[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n3469_s15/I2 |
| 6.815 | 0.329 | tINS | RR | 1 | R7C109[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n3469_s15/F |
| 7.074 | 0.259 | tNET | RR | 1 | R5C109[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n3469_s10/I3 |
| 7.439 | 0.365 | tINS | RR | 2 | R5C109[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n3469_s10/F |
| 8.451 | 1.012 | tNET | RR | 1 | R5C112[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n3447_s2/I0 |
| 8.868 | 0.417 | tINS | RR | 1 | R5C112[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n3447_s2/F |
| 9.197 | 0.329 | tNET | RR | 1 | R5C108[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n3447_s1/I1 |
| 9.614 | 0.417 | tINS | RR | 1 | R5C108[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n3447_s1/F |
| 9.614 | 0.000 | tNET | RR | 1 | R5C108[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/cal_crc_64bit_29_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.998 | 4.598 | tNET | RR | 1 | R5C108[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/cal_crc_64bit_29_s1/CLK |
| 10.952 | -0.046 | tSu | 1 | R5C108[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/cal_crc_64bit_29_s1 |
Path Statistics:
| Clock Skew | 0.003 |
| Setup Relationship | 6.400 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.595, 100.000% |
| Arrival Data Path Delay | cell: 1.944, 38.730%; route: 2.800, 55.783%; tC2Q: 0.275, 5.487% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.598, 100.000% |
Path28
Path Summary:
| Slack | 1.361 |
| Data Arrival Time | 9.555 |
| Data Required Time | 10.916 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_20_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.555 | 4.555 | tNET | RR | 1 | R12C103[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/CLK |
| 4.830 | 0.275 | tC2Q | RR | 47 | R12C103[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/Q |
| 6.901 | 2.071 | tNET | RR | 1 | R6C97[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6879_s9/I2 |
| 7.310 | 0.409 | tINS | RR | 9 | R6C97[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6879_s9/F |
| 8.647 | 1.337 | tNET | RR | 1 | R11C106[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6749_s5/I2 |
| 8.833 | 0.186 | tINS | RF | 1 | R11C106[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6749_s5/F |
| 8.833 | 0.000 | tNET | FF | 1 | R11C106[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6749_s3/I0 |
| 8.989 | 0.156 | tINS | FF | 1 | R11C106[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6749_s3/O |
| 9.137 | 0.148 | tNET | FF | 1 | R12C106[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6929_s6/I1 |
| 9.345 | 0.208 | tINS | FR | 1 | R12C106[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6929_s6/F |
| 9.347 | 0.002 | tNET | RR | 1 | R12C106[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6929_s5/I2 |
| 9.555 | 0.208 | tINS | RR | 1 | R12C106[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6929_s5/F |
| 9.555 | 0.000 | tNET | RR | 1 | R12C106[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_20_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.961 | 4.561 | tNET | RR | 1 | R12C106[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_20_s0/CLK |
| 10.916 | -0.046 | tSu | 1 | R12C106[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_20_s0 |
Path Statistics:
| Clock Skew | 0.007 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.555, 100.000% |
| Arrival Data Path Delay | cell: 1.166, 23.328%; route: 3.558, 71.164%; tC2Q: 0.275, 5.508% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.561, 100.000% |
Path29
Path Summary:
| Slack | 1.372 |
| Data Arrival Time | 9.556 |
| Data Required Time | 10.928 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_55_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.585 | 4.585 | tNET | RR | 1 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/CLK |
| 4.860 | 0.275 | tC2Q | RR | 3 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q |
| 5.599 | 0.739 | tNET | RR | 1 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/I3 |
| 5.829 | 0.229 | tINS | RF | 2 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/F |
| 6.282 | 0.453 | tNET | FF | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/I2 |
| 6.647 | 0.365 | tINS | FR | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/F |
| 6.649 | 0.002 | tNET | RR | 1 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/I0 |
| 7.065 | 0.417 | tINS | RR | 72 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/F |
| 9.348 | 2.283 | tNET | RR | 1 | R33C96[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n337_s0/I2 |
| 9.556 | 0.208 | tINS | RR | 1 | R33C96[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n337_s0/F |
| 9.556 | 0.000 | tNET | RR | 1 | R33C96[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_55_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.974 | 4.574 | tNET | RR | 1 | R33C96[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_55_s0/CLK |
| 10.928 | -0.046 | tSu | 1 | R33C96[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_55_s0 |
Path Statistics:
| Clock Skew | -0.011 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.585, 100.000% |
| Arrival Data Path Delay | cell: 1.220, 24.532%; route: 3.476, 69.928%; tC2Q: 0.275, 5.540% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.574, 100.000% |
Path30
Path Summary:
| Slack | 1.373 |
| Data Arrival Time | 9.556 |
| Data Required Time | 10.930 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_0_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.585 | 4.585 | tNET | RR | 1 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/CLK |
| 4.860 | 0.275 | tC2Q | RR | 3 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q |
| 5.599 | 0.739 | tNET | RR | 1 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/I3 |
| 5.829 | 0.229 | tINS | RF | 2 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/F |
| 6.282 | 0.453 | tNET | FF | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/I2 |
| 6.647 | 0.365 | tINS | FR | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/F |
| 6.649 | 0.002 | tNET | RR | 1 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/I0 |
| 7.065 | 0.417 | tINS | RR | 72 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/F |
| 9.348 | 2.283 | tNET | RR | 1 | R34C96[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n392_s0/I2 |
| 9.556 | 0.208 | tINS | RR | 1 | R34C96[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n392_s0/F |
| 9.556 | 0.000 | tNET | RR | 1 | R34C96[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_0_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.976 | 4.576 | tNET | RR | 1 | R34C96[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_0_s0/CLK |
| 10.930 | -0.046 | tSu | 1 | R34C96[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_0_s0 |
Path Statistics:
| Clock Skew | -0.009 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.585, 100.000% |
| Arrival Data Path Delay | cell: 1.220, 24.532%; route: 3.476, 69.928%; tC2Q: 0.275, 5.540% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.576, 100.000% |
Path31
Path Summary:
| Slack | 1.373 |
| Data Arrival Time | 9.556 |
| Data Required Time | 10.930 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_32_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.585 | 4.585 | tNET | RR | 1 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/CLK |
| 4.860 | 0.275 | tC2Q | RR | 3 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q |
| 5.599 | 0.739 | tNET | RR | 1 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/I3 |
| 5.829 | 0.229 | tINS | RF | 2 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/F |
| 6.282 | 0.453 | tNET | FF | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/I2 |
| 6.647 | 0.365 | tINS | FR | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/F |
| 6.649 | 0.002 | tNET | RR | 1 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/I0 |
| 7.065 | 0.417 | tINS | RR | 72 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/F |
| 9.348 | 2.283 | tNET | RR | 1 | R34C96[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n360_s0/I2 |
| 9.556 | 0.208 | tINS | RR | 1 | R34C96[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n360_s0/F |
| 9.556 | 0.000 | tNET | RR | 1 | R34C96[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_32_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.976 | 4.576 | tNET | RR | 1 | R34C96[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_32_s0/CLK |
| 10.930 | -0.046 | tSu | 1 | R34C96[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_32_s0 |
Path Statistics:
| Clock Skew | -0.009 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.585, 100.000% |
| Arrival Data Path Delay | cell: 1.220, 24.532%; route: 3.476, 69.928%; tC2Q: 0.275, 5.540% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.576, 100.000% |
Path32
Path Summary:
| Slack | 1.374 |
| Data Arrival Time | 9.575 |
| Data Required Time | 10.950 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_11_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.555 | 4.555 | tNET | RR | 1 | R12C103[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/CLK |
| 4.830 | 0.275 | tC2Q | RR | 47 | R12C103[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/Q |
| 6.901 | 2.071 | tNET | RR | 1 | R6C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6746_s6/I1 |
| 7.315 | 0.413 | tINS | RR | 1 | R6C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6746_s6/F |
| 7.316 | 0.002 | tNET | RR | 1 | R6C97[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6753_s5/I2 |
| 7.733 | 0.417 | tINS | RR | 28 | R6C97[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6753_s5/F |
| 8.457 | 0.724 | tNET | RR | 1 | R7C100[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6938_s7/I2 |
| 8.785 | 0.329 | tINS | RR | 1 | R7C100[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6938_s7/F |
| 9.210 | 0.425 | tNET | RR | 1 | R8C97[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6938_s5/I1 |
| 9.575 | 0.365 | tINS | RR | 1 | R8C97[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6938_s5/F |
| 9.575 | 0.000 | tNET | RR | 1 | R8C97[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_11_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.996 | 4.596 | tNET | RR | 1 | R8C97[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_11_s0/CLK |
| 10.950 | -0.046 | tSu | 1 | R8C97[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_11_s0 |
Path Statistics:
| Clock Skew | 0.041 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.555, 100.000% |
| Arrival Data Path Delay | cell: 1.524, 30.349%; route: 3.222, 64.166%; tC2Q: 0.275, 5.485% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.596, 100.000% |
Path33
Path Summary:
| Slack | 1.375 |
| Data Arrival Time | 9.556 |
| Data Required Time | 10.931 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_16_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.585 | 4.585 | tNET | RR | 1 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/CLK |
| 4.860 | 0.275 | tC2Q | RR | 3 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q |
| 5.599 | 0.739 | tNET | RR | 1 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/I3 |
| 5.829 | 0.229 | tINS | RF | 2 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/F |
| 6.282 | 0.453 | tNET | FF | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/I2 |
| 6.647 | 0.365 | tINS | FR | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/F |
| 6.649 | 0.002 | tNET | RR | 1 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/I0 |
| 7.065 | 0.417 | tINS | RR | 72 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/F |
| 9.191 | 2.125 | tNET | RR | 1 | R35C96[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n376_s0/I2 |
| 9.556 | 0.365 | tINS | RR | 1 | R35C96[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n376_s0/F |
| 9.556 | 0.000 | tNET | RR | 1 | R35C96[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_16_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.977 | 4.577 | tNET | RR | 1 | R35C96[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_16_s0/CLK |
| 10.931 | -0.046 | tSu | 1 | R35C96[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_16_s0 |
Path Statistics:
| Clock Skew | -0.008 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.585, 100.000% |
| Arrival Data Path Delay | cell: 1.377, 27.700%; route: 3.319, 66.760%; tC2Q: 0.275, 5.540% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.577, 100.000% |
Path34
Path Summary:
| Slack | 1.375 |
| Data Arrival Time | 9.556 |
| Data Required Time | 10.931 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_18_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.585 | 4.585 | tNET | RR | 1 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/CLK |
| 4.860 | 0.275 | tC2Q | RR | 3 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q |
| 5.599 | 0.739 | tNET | RR | 1 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/I3 |
| 5.829 | 0.229 | tINS | RF | 2 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/F |
| 6.282 | 0.453 | tNET | FF | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/I2 |
| 6.647 | 0.365 | tINS | FR | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/F |
| 6.649 | 0.002 | tNET | RR | 1 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/I0 |
| 7.065 | 0.417 | tINS | RR | 72 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/F |
| 9.191 | 2.125 | tNET | RR | 1 | R35C96[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n374_s0/I2 |
| 9.556 | 0.365 | tINS | RR | 1 | R35C96[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n374_s0/F |
| 9.556 | 0.000 | tNET | RR | 1 | R35C96[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_18_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.977 | 4.577 | tNET | RR | 1 | R35C96[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_18_s0/CLK |
| 10.931 | -0.046 | tSu | 1 | R35C96[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_18_s0 |
Path Statistics:
| Clock Skew | -0.008 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.585, 100.000% |
| Arrival Data Path Delay | cell: 1.377, 27.700%; route: 3.319, 66.760%; tC2Q: 0.275, 5.540% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.577, 100.000% |
Path35
Path Summary:
| Slack | 1.382 |
| Data Arrival Time | 9.556 |
| Data Required Time | 10.938 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_8_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.585 | 4.585 | tNET | RR | 1 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/CLK |
| 4.860 | 0.275 | tC2Q | RR | 3 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q |
| 5.599 | 0.739 | tNET | RR | 1 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/I3 |
| 5.829 | 0.229 | tINS | RF | 2 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/F |
| 6.282 | 0.453 | tNET | FF | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/I2 |
| 6.647 | 0.365 | tINS | FR | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/F |
| 6.649 | 0.002 | tNET | RR | 1 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/I0 |
| 7.065 | 0.417 | tINS | RR | 72 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/F |
| 9.191 | 2.125 | tNET | RR | 1 | R35C97[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n384_s0/I2 |
| 9.556 | 0.365 | tINS | RR | 1 | R35C97[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n384_s0/F |
| 9.556 | 0.000 | tNET | RR | 1 | R35C97[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_8_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.984 | 4.584 | tNET | RR | 1 | R35C97[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_8_s0/CLK |
| 10.938 | -0.046 | tSu | 1 | R35C97[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_8_s0 |
Path Statistics:
| Clock Skew | -0.001 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.585, 100.000% |
| Arrival Data Path Delay | cell: 1.377, 27.700%; route: 3.319, 66.760%; tC2Q: 0.275, 5.540% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.584, 100.000% |
Path36
Path Summary:
| Slack | 1.382 |
| Data Arrival Time | 9.556 |
| Data Required Time | 10.938 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_40_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.585 | 4.585 | tNET | RR | 1 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/CLK |
| 4.860 | 0.275 | tC2Q | RR | 3 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q |
| 5.599 | 0.739 | tNET | RR | 1 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/I3 |
| 5.829 | 0.229 | tINS | RF | 2 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/F |
| 6.282 | 0.453 | tNET | FF | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/I2 |
| 6.647 | 0.365 | tINS | FR | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/F |
| 6.649 | 0.002 | tNET | RR | 1 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/I0 |
| 7.065 | 0.417 | tINS | RR | 72 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/F |
| 9.191 | 2.125 | tNET | RR | 1 | R35C97[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n352_s0/I2 |
| 9.556 | 0.365 | tINS | RR | 1 | R35C97[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n352_s0/F |
| 9.556 | 0.000 | tNET | RR | 1 | R35C97[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_40_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.984 | 4.584 | tNET | RR | 1 | R35C97[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_40_s0/CLK |
| 10.938 | -0.046 | tSu | 1 | R35C97[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_40_s0 |
Path Statistics:
| Clock Skew | -0.001 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.585, 100.000% |
| Arrival Data Path Delay | cell: 1.377, 27.700%; route: 3.319, 66.760%; tC2Q: 0.275, 5.540% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.584, 100.000% |
Path37
Path Summary:
| Slack | 1.382 |
| Data Arrival Time | 9.556 |
| Data Required Time | 10.938 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_48_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.585 | 4.585 | tNET | RR | 1 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/CLK |
| 4.860 | 0.275 | tC2Q | RR | 3 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q |
| 5.599 | 0.739 | tNET | RR | 1 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/I3 |
| 5.829 | 0.229 | tINS | RF | 2 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/F |
| 6.282 | 0.453 | tNET | FF | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/I2 |
| 6.647 | 0.365 | tINS | FR | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/F |
| 6.649 | 0.002 | tNET | RR | 1 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/I0 |
| 7.065 | 0.417 | tINS | RR | 72 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/F |
| 9.191 | 2.125 | tNET | RR | 1 | R35C97[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n344_s0/I2 |
| 9.556 | 0.365 | tINS | RR | 1 | R35C97[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n344_s0/F |
| 9.556 | 0.000 | tNET | RR | 1 | R35C97[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_48_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.984 | 4.584 | tNET | RR | 1 | R35C97[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_48_s0/CLK |
| 10.938 | -0.046 | tSu | 1 | R35C97[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_48_s0 |
Path Statistics:
| Clock Skew | -0.001 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.585, 100.000% |
| Arrival Data Path Delay | cell: 1.377, 27.700%; route: 3.319, 66.760%; tC2Q: 0.275, 5.540% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.584, 100.000% |
Path38
Path Summary:
| Slack | 1.382 |
| Data Arrival Time | 9.556 |
| Data Required Time | 10.938 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_50_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.585 | 4.585 | tNET | RR | 1 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/CLK |
| 4.860 | 0.275 | tC2Q | RR | 3 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q |
| 5.599 | 0.739 | tNET | RR | 1 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/I3 |
| 5.829 | 0.229 | tINS | RF | 2 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/F |
| 6.282 | 0.453 | tNET | FF | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/I2 |
| 6.647 | 0.365 | tINS | FR | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/F |
| 6.649 | 0.002 | tNET | RR | 1 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/I0 |
| 7.065 | 0.417 | tINS | RR | 72 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/F |
| 9.191 | 2.125 | tNET | RR | 1 | R35C97[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n342_s0/I2 |
| 9.556 | 0.365 | tINS | RR | 1 | R35C97[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n342_s0/F |
| 9.556 | 0.000 | tNET | RR | 1 | R35C97[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_50_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.984 | 4.584 | tNET | RR | 1 | R35C97[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_50_s0/CLK |
| 10.938 | -0.046 | tSu | 1 | R35C97[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_50_s0 |
Path Statistics:
| Clock Skew | -0.001 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.585, 100.000% |
| Arrival Data Path Delay | cell: 1.377, 27.700%; route: 3.319, 66.760%; tC2Q: 0.275, 5.540% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.584, 100.000% |
Path39
Path Summary:
| Slack | 1.394 |
| Data Arrival Time | 9.523 |
| Data Required Time | 10.917 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_18_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.555 | 4.555 | tNET | RR | 1 | R12C103[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/CLK |
| 4.830 | 0.275 | tC2Q | RR | 47 | R12C103[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/Q |
| 6.901 | 2.071 | tNET | RR | 1 | R6C97[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6879_s9/I2 |
| 7.310 | 0.409 | tINS | RR | 9 | R6C97[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6879_s9/F |
| 7.912 | 0.602 | tNET | RR | 1 | R12C97[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6751_s5/I2 |
| 8.329 | 0.417 | tINS | RR | 1 | R12C97[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6751_s5/F |
| 8.329 | 0.000 | tNET | RR | 1 | R12C97[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6751_s3/I0 |
| 8.437 | 0.108 | tINS | RR | 1 | R12C97[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6751_s3/O |
| 8.589 | 0.152 | tNET | RR | 1 | R14C97[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6931_s6/I1 |
| 8.954 | 0.365 | tINS | RR | 1 | R14C97[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6931_s6/F |
| 9.106 | 0.152 | tNET | RR | 1 | R14C95[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6931_s5/I2 |
| 9.523 | 0.417 | tINS | RR | 1 | R14C95[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6931_s5/F |
| 9.523 | 0.000 | tNET | RR | 1 | R14C95[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_18_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.963 | 4.563 | tNET | RR | 1 | R14C95[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_18_s0/CLK |
| 10.917 | -0.046 | tSu | 1 | R14C95[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_18_s0 |
Path Statistics:
| Clock Skew | 0.009 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.555, 100.000% |
| Arrival Data Path Delay | cell: 1.715, 34.526%; route: 2.978, 59.931%; tC2Q: 0.275, 5.543% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.563, 100.000% |
Path40
Path Summary:
| Slack | 1.524 |
| Data Arrival Time | 9.397 |
| Data Required Time | 10.921 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_13_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.555 | 4.555 | tNET | RR | 1 | R12C103[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/CLK |
| 4.830 | 0.275 | tC2Q | RR | 47 | R12C103[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/Q |
| 6.901 | 2.071 | tNET | RR | 1 | R6C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6746_s6/I1 |
| 7.315 | 0.413 | tINS | RR | 1 | R6C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6746_s6/F |
| 7.316 | 0.002 | tNET | RR | 1 | R6C97[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6753_s5/I2 |
| 7.733 | 0.417 | tINS | RR | 28 | R6C97[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6753_s5/F |
| 8.508 | 0.775 | tNET | RR | 1 | R13C107[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6936_s7/I2 |
| 8.836 | 0.329 | tINS | RR | 1 | R13C107[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6936_s7/F |
| 8.989 | 0.152 | tNET | RR | 1 | R11C107[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6936_s5/I1 |
| 9.397 | 0.409 | tINS | RR | 1 | R11C107[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6936_s5/F |
| 9.397 | 0.000 | tNET | RR | 1 | R11C107[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_13_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.967 | 4.567 | tNET | RR | 1 | R11C107[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_13_s0/CLK |
| 10.921 | -0.046 | tSu | 1 | R11C107[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_13_s0 |
Path Statistics:
| Clock Skew | 0.012 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.555, 100.000% |
| Arrival Data Path Delay | cell: 1.567, 32.358%; route: 3.000, 61.955%; tC2Q: 0.275, 5.687% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.567, 100.000% |
Path41
Path Summary:
| Slack | 1.533 |
| Data Arrival Time | 9.400 |
| Data Required Time | 10.932 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxc_align_reg_5_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.585 | 4.585 | tNET | RR | 1 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/CLK |
| 4.860 | 0.275 | tC2Q | RR | 3 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q |
| 5.599 | 0.739 | tNET | RR | 1 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/I3 |
| 5.829 | 0.229 | tINS | RF | 2 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/F |
| 6.282 | 0.453 | tNET | FF | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/I2 |
| 6.647 | 0.365 | tINS | FR | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/F |
| 6.649 | 0.002 | tNET | RR | 1 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/I0 |
| 7.065 | 0.417 | tINS | RR | 72 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/F |
| 8.983 | 1.917 | tNET | RR | 1 | R36C98[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n323_s0/I2 |
| 9.400 | 0.417 | tINS | RR | 1 | R36C98[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n323_s0/F |
| 9.400 | 0.000 | tNET | RR | 1 | R36C98[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxc_align_reg_5_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.978 | 4.578 | tNET | RR | 1 | R36C98[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxc_align_reg_5_s0/CLK |
| 10.932 | -0.046 | tSu | 1 | R36C98[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxc_align_reg_5_s0 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.585, 100.000% |
| Arrival Data Path Delay | cell: 1.428, 29.666%; route: 3.111, 64.614%; tC2Q: 0.275, 5.720% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.578, 100.000% |
Path42
Path Summary:
| Slack | 1.538 |
| Data Arrival Time | 9.393 |
| Data Required Time | 10.931 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_25_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.585 | 4.585 | tNET | RR | 1 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/CLK |
| 4.860 | 0.275 | tC2Q | RR | 3 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q |
| 5.599 | 0.739 | tNET | RR | 1 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/I3 |
| 5.829 | 0.229 | tINS | RF | 2 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/F |
| 6.282 | 0.453 | tNET | FF | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/I2 |
| 6.647 | 0.365 | tINS | FR | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/F |
| 6.649 | 0.002 | tNET | RR | 1 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/I0 |
| 7.065 | 0.417 | tINS | RR | 72 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/F |
| 9.028 | 1.962 | tNET | RR | 1 | R35C98[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n367_s0/I2 |
| 9.393 | 0.365 | tINS | RR | 1 | R35C98[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n367_s0/F |
| 9.393 | 0.000 | tNET | RR | 1 | R35C98[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_25_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.977 | 4.577 | tNET | RR | 1 | R35C98[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_25_s0/CLK |
| 10.931 | -0.046 | tSu | 1 | R35C98[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_25_s0 |
Path Statistics:
| Clock Skew | -0.008 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.585, 100.000% |
| Arrival Data Path Delay | cell: 1.377, 28.638%; route: 3.156, 65.634%; tC2Q: 0.275, 5.728% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.577, 100.000% |
Path43
Path Summary:
| Slack | 1.538 |
| Data Arrival Time | 9.393 |
| Data Required Time | 10.931 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_57_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.585 | 4.585 | tNET | RR | 1 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/CLK |
| 4.860 | 0.275 | tC2Q | RR | 3 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q |
| 5.599 | 0.739 | tNET | RR | 1 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/I3 |
| 5.829 | 0.229 | tINS | RF | 2 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/F |
| 6.282 | 0.453 | tNET | FF | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/I2 |
| 6.647 | 0.365 | tINS | FR | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/F |
| 6.649 | 0.002 | tNET | RR | 1 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/I0 |
| 7.065 | 0.417 | tINS | RR | 72 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/F |
| 9.028 | 1.962 | tNET | RR | 1 | R35C98[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n335_s0/I2 |
| 9.393 | 0.365 | tINS | RR | 1 | R35C98[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n335_s0/F |
| 9.393 | 0.000 | tNET | RR | 1 | R35C98[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_57_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.977 | 4.577 | tNET | RR | 1 | R35C98[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_57_s0/CLK |
| 10.931 | -0.046 | tSu | 1 | R35C98[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_57_s0 |
Path Statistics:
| Clock Skew | -0.008 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.585, 100.000% |
| Arrival Data Path Delay | cell: 1.377, 28.638%; route: 3.156, 65.634%; tC2Q: 0.275, 5.728% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.577, 100.000% |
Path44
Path Summary:
| Slack | 1.548 |
| Data Arrival Time | 9.392 |
| Data Required Time | 10.939 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_24_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.585 | 4.585 | tNET | RR | 1 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/CLK |
| 4.860 | 0.275 | tC2Q | RR | 3 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q |
| 5.599 | 0.739 | tNET | RR | 1 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/I3 |
| 5.829 | 0.229 | tINS | RF | 2 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/F |
| 6.282 | 0.453 | tNET | FF | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/I2 |
| 6.647 | 0.365 | tINS | FR | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/F |
| 6.649 | 0.002 | tNET | RR | 1 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/I0 |
| 7.065 | 0.417 | tINS | RR | 72 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/F |
| 9.026 | 1.961 | tNET | RR | 1 | R36C97[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n368_s0/I2 |
| 9.392 | 0.365 | tINS | RR | 1 | R36C97[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n368_s0/F |
| 9.392 | 0.000 | tNET | RR | 1 | R36C97[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_24_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.985 | 4.585 | tNET | RR | 1 | R36C97[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_24_s0/CLK |
| 10.939 | -0.046 | tSu | 1 | R36C97[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_24_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.585, 100.000% |
| Arrival Data Path Delay | cell: 1.377, 28.649%; route: 3.154, 65.621%; tC2Q: 0.275, 5.730% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.585, 100.000% |
Path45
Path Summary:
| Slack | 1.548 |
| Data Arrival Time | 9.392 |
| Data Required Time | 10.939 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_56_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.585 | 4.585 | tNET | RR | 1 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/CLK |
| 4.860 | 0.275 | tC2Q | RR | 3 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q |
| 5.599 | 0.739 | tNET | RR | 1 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/I3 |
| 5.829 | 0.229 | tINS | RF | 2 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/F |
| 6.282 | 0.453 | tNET | FF | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/I2 |
| 6.647 | 0.365 | tINS | FR | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/F |
| 6.649 | 0.002 | tNET | RR | 1 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/I0 |
| 7.065 | 0.417 | tINS | RR | 72 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/F |
| 9.026 | 1.961 | tNET | RR | 1 | R36C97[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n336_s0/I2 |
| 9.392 | 0.365 | tINS | RR | 1 | R36C97[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n336_s0/F |
| 9.392 | 0.000 | tNET | RR | 1 | R36C97[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_56_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.985 | 4.585 | tNET | RR | 1 | R36C97[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_56_s0/CLK |
| 10.939 | -0.046 | tSu | 1 | R36C97[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_align_reg_56_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.585, 100.000% |
| Arrival Data Path Delay | cell: 1.377, 28.649%; route: 3.154, 65.621%; tC2Q: 0.275, 5.730% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.585, 100.000% |
Path46
Path Summary:
| Slack | 1.555 |
| Data Arrival Time | 9.377 |
| Data Required Time | 10.932 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxc_align_reg_1_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.585 | 4.585 | tNET | RR | 1 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/CLK |
| 4.860 | 0.275 | tC2Q | RR | 3 | R36C113[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxd_reg0_35_s0/Q |
| 5.599 | 0.739 | tNET | RR | 1 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/I3 |
| 5.829 | 0.229 | tINS | RF | 2 | R34C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s6/F |
| 6.282 | 0.453 | tNET | FF | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/I2 |
| 6.647 | 0.365 | tINS | FR | 1 | R30C94[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/dword_shift_s4/F |
| 6.649 | 0.002 | tNET | RR | 1 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/I0 |
| 7.065 | 0.417 | tINS | RR | 72 | R30C94[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n321_s1/F |
| 8.983 | 1.917 | tNET | RR | 1 | R36C98[3][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n327_s0/I2 |
| 9.377 | 0.394 | tINS | RR | 1 | R36C98[3][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/n327_s0/F |
| 9.377 | 0.000 | tNET | RR | 1 | R36C98[3][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxc_align_reg_1_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.978 | 4.578 | tNET | RR | 1 | R36C98[3][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxc_align_reg_1_s0/CLK |
| 10.932 | -0.046 | tSu | 1 | R36C98[3][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_rx_ctrl/rxc_align_reg_1_s0 |
Path Statistics:
| Clock Skew | -0.007 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.585, 100.000% |
| Arrival Data Path Delay | cell: 1.406, 29.336%; route: 3.111, 64.917%; tC2Q: 0.275, 5.747% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.578, 100.000% |
Path47
Path Summary:
| Slack | 1.579 |
| Data Arrival Time | 9.342 |
| Data Required Time | 10.922 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_6_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.555 | 4.555 | tNET | RR | 1 | R12C103[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/CLK |
| 4.830 | 0.275 | tC2Q | RR | 47 | R12C103[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/Q |
| 6.901 | 2.071 | tNET | RR | 1 | R6C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6746_s6/I1 |
| 7.315 | 0.413 | tINS | RR | 1 | R6C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6746_s6/F |
| 7.316 | 0.002 | tNET | RR | 1 | R6C97[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6753_s5/I2 |
| 7.733 | 0.417 | tINS | RR | 28 | R6C97[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6753_s5/F |
| 8.647 | 0.914 | tNET | RR | 1 | R15C99[3][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6943_s10/I3 |
| 8.975 | 0.329 | tINS | RR | 1 | R15C99[3][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6943_s10/F |
| 8.977 | 0.002 | tNET | RR | 1 | R15C99[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6943_s5/I1 |
| 9.342 | 0.365 | tINS | RR | 1 | R15C99[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6943_s5/F |
| 9.342 | 0.000 | tNET | RR | 1 | R15C99[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_6_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.968 | 4.568 | tNET | RR | 1 | R15C99[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_6_s0/CLK |
| 10.922 | -0.046 | tSu | 1 | R15C99[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_6_s0 |
Path Statistics:
| Clock Skew | 0.013 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.555, 100.000% |
| Arrival Data Path Delay | cell: 1.524, 31.826%; route: 2.988, 62.421%; tC2Q: 0.275, 5.752% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.568, 100.000% |
Path48
Path Summary:
| Slack | 1.591 |
| Data Arrival Time | 9.322 |
| Data Required Time | 10.913 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_4_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.555 | 4.555 | tNET | RR | 1 | R12C103[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/CLK |
| 4.830 | 0.275 | tC2Q | RR | 47 | R12C103[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/Q |
| 6.901 | 2.071 | tNET | RR | 1 | R6C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6746_s6/I1 |
| 7.315 | 0.413 | tINS | RR | 1 | R6C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6746_s6/F |
| 7.316 | 0.002 | tNET | RR | 1 | R6C97[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6753_s5/I2 |
| 7.733 | 0.417 | tINS | RR | 28 | R6C97[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6753_s5/F |
| 8.905 | 1.172 | tNET | RR | 1 | R13C107[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6945_s10/I3 |
| 9.113 | 0.208 | tINS | RR | 1 | R13C107[0][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6945_s10/F |
| 9.115 | 0.002 | tNET | RR | 1 | R13C107[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6945_s5/I1 |
| 9.322 | 0.208 | tINS | RR | 1 | R13C107[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6945_s5/F |
| 9.322 | 0.000 | tNET | RR | 1 | R13C107[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_4_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.959 | 4.559 | tNET | RR | 1 | R13C107[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_4_s0/CLK |
| 10.913 | -0.046 | tSu | 1 | R13C107[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_4_s0 |
Path Statistics:
| Clock Skew | 0.004 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.555, 100.000% |
| Arrival Data Path Delay | cell: 1.246, 26.126%; route: 3.247, 68.098%; tC2Q: 0.275, 5.776% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.559, 100.000% |
Path49
Path Summary:
| Slack | 1.604 |
| Data Arrival Time | 9.324 |
| Data Required Time | 10.928 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_2_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.555 | 4.555 | tNET | RR | 1 | R12C103[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/CLK |
| 4.830 | 0.275 | tC2Q | RR | 47 | R12C103[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/Q |
| 6.901 | 2.071 | tNET | RR | 1 | R6C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6746_s6/I1 |
| 7.315 | 0.413 | tINS | RR | 1 | R6C97[3][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6746_s6/F |
| 7.316 | 0.002 | tNET | RR | 1 | R6C97[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6753_s5/I2 |
| 7.733 | 0.417 | tINS | RR | 28 | R6C97[2][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6753_s5/F |
| 8.451 | 0.718 | tNET | RR | 1 | R15C101[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6947_s10/I3 |
| 8.817 | 0.365 | tINS | RR | 1 | R15C101[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6947_s10/F |
| 8.959 | 0.142 | tNET | RR | 1 | R15C100[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6947_s5/I1 |
| 9.324 | 0.365 | tINS | RR | 1 | R15C100[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6947_s5/F |
| 9.324 | 0.000 | tNET | RR | 1 | R15C100[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_2_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.974 | 4.574 | tNET | RR | 1 | R15C100[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_2_s0/CLK |
| 10.928 | -0.046 | tSu | 1 | R15C100[0][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_2_s0 |
Path Statistics:
| Clock Skew | 0.020 |
| Setup Relationship | 6.400 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.555, 100.000% |
| Arrival Data Path Delay | cell: 1.561, 32.720%; route: 2.934, 61.506%; tC2Q: 0.275, 5.774% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.574, 100.000% |
Path50
Path Summary:
| Slack | 1.617 |
| Data Arrival Time | 9.296 |
| Data Required Time | 10.913 |
| From | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1 |
| To | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_24_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.555 | 4.555 | tNET | RR | 1 | R12C103[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/CLK |
| 4.830 | 0.275 | tC2Q | RR | 47 | R12C103[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/send_data_last_flag_pipe8_s1/Q |
| 6.901 | 2.071 | tNET | RR | 1 | R6C97[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6950_s8/I1 |
| 7.318 | 0.417 | tINS | RR | 10 | R6C97[1][A] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6950_s8/F |
| 8.188 | 0.870 | tNET | RR | 1 | R13C106[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6925_s6/I2 |
| 8.605 | 0.417 | tINS | RR | 1 | R13C106[1][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6925_s6/F |
| 8.880 | 0.275 | tNET | RR | 1 | R13C103[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6925_s5/I2 |
| 9.296 | 0.417 | tINS | RR | 1 | R13C103[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/n6925_s5/F |
| 9.296 | 0.000 | tNET | RR | 1 | R13C103[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_24_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.959 | 4.559 | tNET | RR | 1 | R13C103[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_24_s0/CLK |
| 10.913 | -0.046 | tSu | 1 | R13C103[2][B] | u_Ten_Giga_Ethernet_MAC_Top/xgmac/u_xgmac_tx_ctrl/u_xgmac_tx_crc/crc_send_data_24_s0 |
Path Statistics:
| Clock Skew | 0.004 |
| Setup Relationship | 6.400 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.555, 100.000% |
| Arrival Data Path Delay | cell: 1.250, 26.364%; route: 3.216, 67.828%; tC2Q: 0.275, 5.808% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.559, 100.000% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 0.181 |
| Data Arrival Time | 2.529 |
| Data Required Time | 2.348 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_11_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.316 | 2.316 | tNET | RR | 1 | R45C102[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_11_s0/CLK |
| 2.445 | 0.130 | tC2Q | RR | 1 | R45C102[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_11_s0/Q |
| 2.529 | 0.084 | tNET | RR | 1 | BSRAM_R46[21][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[11] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.315 | 2.315 | tNET | RR | 1 | BSRAM_R46[21][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
| 2.348 | 0.033 | tHld | 1 | BSRAM_R46[21][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Path Statistics:
| Clock Skew | -0.001 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.316, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.084, 39.241%; tC2Q: 0.130, 60.759% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.315, 100.000% |
Path2
Path Summary:
| Slack | 0.181 |
| Data Arrival Time | 2.529 |
| Data Required Time | 2.348 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_10_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.316 | 2.316 | tNET | RR | 1 | R45C102[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_10_s0/CLK |
| 2.445 | 0.130 | tC2Q | RR | 1 | R45C102[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_10_s0/Q |
| 2.529 | 0.084 | tNET | RR | 1 | BSRAM_R46[21][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[10] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.315 | 2.315 | tNET | RR | 1 | BSRAM_R46[21][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
| 2.348 | 0.033 | tHld | 1 | BSRAM_R46[21][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Path Statistics:
| Clock Skew | -0.001 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.316, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.084, 39.241%; tC2Q: 0.130, 60.759% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.315, 100.000% |
Path3
Path Summary:
| Slack | 0.181 |
| Data Arrival Time | 2.529 |
| Data Required Time | 2.348 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_17_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.316 | 2.316 | tNET | RR | 1 | R9C138[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_17_s0/CLK |
| 2.445 | 0.130 | tC2Q | RR | 1 | R9C138[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_17_s0/Q |
| 2.529 | 0.084 | tNET | RR | 1 | BSRAM_R10[30][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/DI[17] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.315 | 2.315 | tNET | RR | 1 | BSRAM_R10[30][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/CLKA |
| 2.348 | 0.033 | tHld | 1 | BSRAM_R10[30][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s |
Path Statistics:
| Clock Skew | -0.001 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.316, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.084, 39.241%; tC2Q: 0.130, 60.759% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.315, 100.000% |
Path4
Path Summary:
| Slack | 0.184 |
| Data Arrival Time | 2.529 |
| Data Required Time | 2.345 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_80_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPB_mem_mem_0_2_s |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.316 | 2.316 | tNET | RR | 1 | R45C98[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_80_s0/CLK |
| 2.445 | 0.130 | tC2Q | RR | 1 | R45C98[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_80_s0/Q |
| 2.529 | 0.084 | tNET | RR | 1 | BSRAM_R46[20] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPB_mem_mem_0_2_s/DI[0] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.311 | 2.311 | tNET | RR | 1 | BSRAM_R46[20] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPB_mem_mem_0_2_s/CLKA |
| 2.345 | 0.033 | tHld | 1 | BSRAM_R46[20] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPB_mem_mem_0_2_s |
Path Statistics:
| Clock Skew | -0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.316, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.084, 39.241%; tC2Q: 0.130, 60.759% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.311, 100.000% |
Path5
Path Summary:
| Slack | 0.184 |
| Data Arrival Time | 2.525 |
| Data Required Time | 2.341 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_72_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.312 | 2.312 | tNET | RR | 1 | R45C107[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_72_s0/CLK |
| 2.442 | 0.130 | tC2Q | RR | 1 | R45C107[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_72_s0/Q |
| 2.525 | 0.084 | tNET | RR | 1 | BSRAM_R46[22] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[8] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.308 | 2.308 | tNET | RR | 1 | BSRAM_R46[22] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA |
| 2.341 | 0.033 | tHld | 1 | BSRAM_R46[22] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Path Statistics:
| Clock Skew | -0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.312, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.084, 39.241%; tC2Q: 0.130, 60.759% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.308, 100.000% |
Path6
Path Summary:
| Slack | 0.184 |
| Data Arrival Time | 2.525 |
| Data Required Time | 2.341 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_69_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.312 | 2.312 | tNET | RR | 1 | R45C107[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_69_s0/CLK |
| 2.442 | 0.130 | tC2Q | RR | 1 | R45C107[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_69_s0/Q |
| 2.525 | 0.084 | tNET | RR | 1 | BSRAM_R46[22] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[5] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.308 | 2.308 | tNET | RR | 1 | BSRAM_R46[22] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA |
| 2.341 | 0.033 | tHld | 1 | BSRAM_R46[22] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Path Statistics:
| Clock Skew | -0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.312, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.084, 39.241%; tC2Q: 0.130, 60.759% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.308, 100.000% |
Path7
Path Summary:
| Slack | 0.184 |
| Data Arrival Time | 1.008 |
| Data Required Time | 0.823 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_60_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/gowin_add_SDPX9B_mem_mem_0_1_s |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 0.795 | 0.795 | tNET | RR | 1 | R45C137[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_60_s0/CLK |
| 0.924 | 0.130 | tC2Q | RR | 1 | R45C137[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_60_s0/Q |
| 1.008 | 0.084 | tNET | RR | 1 | BSRAM_R46[29][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/gowin_add_SDPX9B_mem_mem_0_1_s/DI[6] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 0.790 | 0.790 | tNET | RR | 1 | BSRAM_R46[29][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/gowin_add_SDPX9B_mem_mem_0_1_s/CLKA |
| 0.823 | 0.033 | tHld | 1 | BSRAM_R46[29][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/gowin_add_SDPX9B_mem_mem_0_1_s |
Path Statistics:
| Clock Skew | -0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.795, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.084, 39.241%; tC2Q: 0.130, 60.759% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.790, 100.000% |
Path8
Path Summary:
| Slack | 0.184 |
| Data Arrival Time | 2.529 |
| Data Required Time | 2.345 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_20_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/gowin_add_SDPX9B_phase_fifo_rd_data_phase_fifo_rd_data_0_0_s |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.316 | 2.316 | tNET | RR | 1 | R9C140[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_20_s0/CLK |
| 2.445 | 0.130 | tC2Q | RR | 1 | R9C140[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_20_s0/Q |
| 2.529 | 0.084 | tNET | RR | 1 | BSRAM_R10[30][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/gowin_add_SDPX9B_phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/DI[2] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.311 | 2.311 | tNET | RR | 1 | BSRAM_R10[30][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/gowin_add_SDPX9B_phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/CLKA |
| 2.345 | 0.033 | tHld | 1 | BSRAM_R10[30][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/gowin_add_SDPX9B_phase_fifo_rd_data_phase_fifo_rd_data_0_0_s |
Path Statistics:
| Clock Skew | -0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.316, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.084, 39.241%; tC2Q: 0.130, 60.759% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.311, 100.000% |
Path9
Path Summary:
| Slack | 0.185 |
| Data Arrival Time | 2.536 |
| Data Required Time | 2.351 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPB_mem_mem_0_0_s |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.322 | 2.322 | tNET | RR | 1 | R45C92[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0/CLK |
| 2.452 | 0.130 | tC2Q | RR | 1 | R45C92[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0/Q |
| 2.536 | 0.084 | tNET | RR | 1 | BSRAM_R46[19][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPB_mem_mem_0_0_s/DI[3] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.318 | 2.318 | tNET | RR | 1 | BSRAM_R46[19][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPB_mem_mem_0_0_s/CLKA |
| 2.351 | 0.033 | tHld | 1 | BSRAM_R46[19][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPB_mem_mem_0_0_s |
Path Statistics:
| Clock Skew | -0.005 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.322, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.084, 39.241%; tC2Q: 0.130, 60.759% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.318, 100.000% |
Path10
Path Summary:
| Slack | 0.185 |
| Data Arrival Time | 2.533 |
| Data Required Time | 2.348 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_7_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.319 | 2.319 | tNET | RR | 1 | R45C101[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_7_s0/CLK |
| 2.449 | 0.130 | tC2Q | RR | 1 | R45C101[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_7_s0/Q |
| 2.533 | 0.084 | tNET | RR | 1 | BSRAM_R46[21][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[7] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.315 | 2.315 | tNET | RR | 1 | BSRAM_R46[21][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
| 2.348 | 0.033 | tHld | 1 | BSRAM_R46[21][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Path Statistics:
| Clock Skew | -0.005 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.319, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.084, 39.241%; tC2Q: 0.130, 60.759% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.315, 100.000% |
Path11
Path Summary:
| Slack | 0.185 |
| Data Arrival Time | 2.533 |
| Data Required Time | 2.348 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_1_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.319 | 2.319 | tNET | RR | 1 | R45C101[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_1_s0/CLK |
| 2.449 | 0.130 | tC2Q | RR | 1 | R45C101[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_1_s0/Q |
| 2.533 | 0.084 | tNET | RR | 1 | BSRAM_R46[21][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[1] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.315 | 2.315 | tNET | RR | 1 | BSRAM_R46[21][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
| 2.348 | 0.033 | tHld | 1 | BSRAM_R46[21][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Path Statistics:
| Clock Skew | -0.005 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.319, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.084, 39.241%; tC2Q: 0.130, 60.759% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.315, 100.000% |
Path12
Path Summary:
| Slack | 0.185 |
| Data Arrival Time | 2.533 |
| Data Required Time | 2.348 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_4_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.319 | 2.319 | tNET | RR | 1 | R9C137[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_4_s0/CLK |
| 2.449 | 0.130 | tC2Q | RR | 1 | R9C137[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_4_s0/Q |
| 2.533 | 0.084 | tNET | RR | 1 | BSRAM_R10[30][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/DI[4] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.315 | 2.315 | tNET | RR | 1 | BSRAM_R10[30][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/CLKA |
| 2.348 | 0.033 | tHld | 1 | BSRAM_R10[30][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s |
Path Statistics:
| Clock Skew | -0.005 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.319, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.084, 39.241%; tC2Q: 0.130, 60.759% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.315, 100.000% |
Path13
Path Summary:
| Slack | 0.185 |
| Data Arrival Time | 2.533 |
| Data Required Time | 2.348 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.319 | 2.319 | tNET | RR | 1 | R9C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_2_s0/CLK |
| 2.449 | 0.130 | tC2Q | RR | 1 | R9C137[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrdata2ram_2_s0/Q |
| 2.533 | 0.084 | tNET | RR | 1 | BSRAM_R10[30][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/DI[2] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.315 | 2.315 | tNET | RR | 1 | BSRAM_R10[30][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/CLKA |
| 2.348 | 0.033 | tHld | 1 | BSRAM_R10[30][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s |
Path Statistics:
| Clock Skew | -0.005 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.319, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.084, 39.241%; tC2Q: 0.130, 60.759% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.315, 100.000% |
Path14
Path Summary:
| Slack | 0.188 |
| Data Arrival Time | 2.529 |
| Data Required Time | 2.341 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_58_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPB_mem_mem_0_1_s |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.316 | 2.316 | tNET | RR | 1 | R45C96[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_58_s0/CLK |
| 2.445 | 0.130 | tC2Q | RR | 1 | R45C96[2][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_58_s0/Q |
| 2.529 | 0.084 | tNET | RR | 1 | BSRAM_R46[19][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPB_mem_mem_0_1_s/DI[10] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.308 | 2.308 | tNET | RR | 1 | BSRAM_R46[19][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPB_mem_mem_0_1_s/CLKA |
| 2.341 | 0.033 | tHld | 1 | BSRAM_R46[19][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPB_mem_mem_0_1_s |
Path Statistics:
| Clock Skew | -0.008 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.316, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.084, 39.241%; tC2Q: 0.130, 60.759% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.308, 100.000% |
Path15
Path Summary:
| Slack | 0.188 |
| Data Arrival Time | 2.529 |
| Data Required Time | 2.341 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_79_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.316 | 2.316 | tNET | RR | 1 | R45C108[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_79_s0/CLK |
| 2.445 | 0.130 | tC2Q | RR | 1 | R45C108[1][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_79_s0/Q |
| 2.529 | 0.084 | tNET | RR | 1 | BSRAM_R46[22] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[15] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.308 | 2.308 | tNET | RR | 1 | BSRAM_R46[22] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA |
| 2.341 | 0.033 | tHld | 1 | BSRAM_R46[22] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Path Statistics:
| Clock Skew | -0.008 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.316, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.084, 39.241%; tC2Q: 0.130, 60.759% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.308, 100.000% |
Path16
Path Summary:
| Slack | 0.188 |
| Data Arrival Time | 2.529 |
| Data Required Time | 2.341 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_78_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.316 | 2.316 | tNET | RR | 1 | R45C108[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_78_s0/CLK |
| 2.445 | 0.130 | tC2Q | RR | 1 | R45C108[1][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_78_s0/Q |
| 2.529 | 0.084 | tNET | RR | 1 | BSRAM_R46[22] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[14] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.308 | 2.308 | tNET | RR | 1 | BSRAM_R46[22] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA |
| 2.341 | 0.033 | tHld | 1 | BSRAM_R46[22] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s |
Path Statistics:
| Clock Skew | -0.008 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.316, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.084, 39.241%; tC2Q: 0.130, 60.759% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.308, 100.000% |
Path17
Path Summary:
| Slack | 0.188 |
| Data Arrival Time | 1.008 |
| Data Required Time | 0.820 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_31_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/gowin_add_SDPX9B_mem_mem_0_0_s |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 0.795 | 0.795 | tNET | RR | 1 | R45C135[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_31_s0/CLK |
| 0.924 | 0.130 | tC2Q | RR | 1 | R45C135[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_31_s0/Q |
| 1.008 | 0.084 | tNET | RR | 1 | BSRAM_R46[28] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/gowin_add_SDPX9B_mem_mem_0_0_s/DI[13] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 0.787 | 0.787 | tNET | RR | 1 | BSRAM_R46[28] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/gowin_add_SDPX9B_mem_mem_0_0_s/CLKA |
| 0.820 | 0.033 | tHld | 1 | BSRAM_R46[28] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/gowin_add_SDPX9B_mem_mem_0_0_s |
Path Statistics:
| Clock Skew | -0.008 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.795, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.084, 39.241%; tC2Q: 0.130, 60.759% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.787, 100.000% |
Path18
Path Summary:
| Slack | 0.188 |
| Data Arrival Time | 1.008 |
| Data Required Time | 0.820 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_28_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/gowin_add_SDPX9B_mem_mem_0_0_s |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 0.795 | 0.795 | tNET | RR | 1 | R45C135[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_28_s0/CLK |
| 0.924 | 0.130 | tC2Q | RR | 1 | R45C135[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_28_s0/Q |
| 1.008 | 0.084 | tNET | RR | 1 | BSRAM_R46[28] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/gowin_add_SDPX9B_mem_mem_0_0_s/DI[10] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 0.787 | 0.787 | tNET | RR | 1 | BSRAM_R46[28] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/gowin_add_SDPX9B_mem_mem_0_0_s/CLKA |
| 0.820 | 0.033 | tHld | 1 | BSRAM_R46[28] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/gowin_add_SDPX9B_mem_mem_0_0_s |
Path Statistics:
| Clock Skew | -0.008 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.795, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.084, 39.241%; tC2Q: 0.130, 60.759% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.787, 100.000% |
Path19
Path Summary:
| Slack | 0.188 |
| Data Arrival Time | 2.533 |
| Data Required Time | 2.345 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_42_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.319 | 2.319 | tNET | RR | 1 | R45C105[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_42_s0/CLK |
| 2.449 | 0.130 | tC2Q | RR | 1 | R45C105[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_42_s0/Q |
| 2.533 | 0.084 | tNET | RR | 1 | BSRAM_R46[21][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[10] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.311 | 2.311 | tNET | RR | 1 | BSRAM_R46[21][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
| 2.345 | 0.033 | tHld | 1 | BSRAM_R46[21][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
| Clock Skew | -0.008 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.319, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.084, 39.241%; tC2Q: 0.130, 60.759% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.311, 100.000% |
Path20
Path Summary:
| Slack | 0.188 |
| Data Arrival Time | 2.533 |
| Data Required Time | 2.345 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_41_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.319 | 2.319 | tNET | RR | 1 | R45C105[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_41_s0/CLK |
| 2.449 | 0.130 | tC2Q | RR | 1 | R45C105[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_41_s0/Q |
| 2.533 | 0.084 | tNET | RR | 1 | BSRAM_R46[21][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[9] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.311 | 2.311 | tNET | RR | 1 | BSRAM_R46[21][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
| 2.345 | 0.033 | tHld | 1 | BSRAM_R46[21][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Path Statistics:
| Clock Skew | -0.008 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.319, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.084, 39.241%; tC2Q: 0.130, 60.759% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.311, 100.000% |
Path21
Path Summary:
| Slack | 0.188 |
| Data Arrival Time | 1.038 |
| Data Required Time | 0.850 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/serdes_pcs_rx_rden_o_s0 |
| To | u_SerDes_Top/gtr12_quad_inst1 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 0.815 | 0.815 | tNET | RR | 1 | R2C112[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/serdes_pcs_rx_rden_o_s0/CLK |
| 0.942 | 0.127 | tC2Q | RF | 1 | R2C112[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/serdes_pcs_rx_rden_o_s0/Q |
| 1.038 | 0.096 | tNET | FF | 1 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_RX_IF_FIFO_RDEN |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 0.813 | 0.813 | tNET | RR | 1 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_FABRIC_RX_CLK |
| 0.850 | 0.037 | tHld | 1 | R0C38 | u_SerDes_Top/gtr12_quad_inst1 |
Path Statistics:
| Clock Skew | -0.002 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.815, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.096, 43.145%; tC2Q: 0.127, 56.855% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.813, 100.000% |
Path22
Path Summary:
| Slack | 0.190 |
| Data Arrival Time | 2.534 |
| Data Required Time | 2.345 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_82_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPB_mem_mem_0_2_s |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.316 | 2.316 | tNET | RR | 1 | R45C98[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_82_s0/CLK |
| 2.445 | 0.130 | tC2Q | RR | 1 | R45C98[0][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_82_s0/Q |
| 2.534 | 0.089 | tNET | RR | 1 | BSRAM_R46[20] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPB_mem_mem_0_2_s/DI[2] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.311 | 2.311 | tNET | RR | 1 | BSRAM_R46[20] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPB_mem_mem_0_2_s/CLKA |
| 2.345 | 0.033 | tHld | 1 | BSRAM_R46[20] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPB_mem_mem_0_2_s |
Path Statistics:
| Clock Skew | -0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.316, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.089, 40.741%; tC2Q: 0.130, 59.259% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.311, 100.000% |
Path23
Path Summary:
| Slack | 0.193 |
| Data Arrival Time | 1.013 |
| Data Required Time | 0.820 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_32_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/gowin_add_SDPX9B_mem_mem_0_0_s |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 0.795 | 0.795 | tNET | RR | 1 | R45C135[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_32_s0/CLK |
| 0.924 | 0.130 | tC2Q | RR | 1 | R45C135[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/wr_rxd_32_s0/Q |
| 1.013 | 0.089 | tNET | RR | 1 | BSRAM_R46[28] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/gowin_add_SDPX9B_mem_mem_0_0_s/DI[14] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 0.787 | 0.787 | tNET | RR | 1 | BSRAM_R46[28] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/gowin_add_SDPX9B_mem_mem_0_0_s/CLKA |
| 0.820 | 0.033 | tHld | 1 | BSRAM_R46[28] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/gowin_add_SDPX9B_mem_mem_0_0_s |
Path Statistics:
| Clock Skew | -0.008 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.795, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.089, 40.741%; tC2Q: 0.130, 59.259% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.787, 100.000% |
Path24
Path Summary:
| Slack | 0.194 |
| Data Arrival Time | 2.546 |
| Data Required Time | 2.351 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPB_mem_mem_0_0_s |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.327 | 2.327 | tNET | RR | 1 | R44C92[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0/CLK |
| 2.457 | 0.130 | tC2Q | RR | 1 | R44C92[2][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0/Q |
| 2.546 | 0.089 | tNET | RR | 1 | BSRAM_R46[19][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPB_mem_mem_0_0_s/DI[8] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.318 | 2.318 | tNET | RR | 1 | BSRAM_R46[19][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPB_mem_mem_0_0_s/CLKA |
| 2.351 | 0.033 | tHld | 1 | BSRAM_R46[19][A] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPB_mem_mem_0_0_s |
Path Statistics:
| Clock Skew | -0.009 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.327, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.089, 40.741%; tC2Q: 0.130, 59.259% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.318, 100.000% |
Path25
Path Summary:
| Slack | 0.206 |
| Data Arrival Time | 2.547 |
| Data Required Time | 2.341 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_50_s0 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPB_mem_mem_0_1_s |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.326 | 2.326 | tNET | RR | 1 | R42C94[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_50_s0/CLK |
| 2.456 | 0.130 | tC2Q | RR | 1 | R42C94[0][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_50_s0/Q |
| 2.547 | 0.091 | tNET | RR | 1 | BSRAM_R46[19][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPB_mem_mem_0_1_s/DI[2] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.308 | 2.308 | tNET | RR | 1 | BSRAM_R46[19][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPB_mem_mem_0_1_s/CLKA |
| 2.341 | 0.033 | tHld | 1 | BSRAM_R46[19][B] | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPB_mem_mem_0_1_s |
Path Statistics:
| Clock Skew | -0.019 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.326, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.091, 41.224%; tC2Q: 0.130, 58.776% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.308, 100.000% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 2.250 |
| Data Arrival Time | 8.476 |
| Data Required Time | 10.725 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe0_4_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.601 | 4.601 | tNET | RR | 1 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
| 4.866 | 0.265 | tC2Q | RF | 1257 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
| 8.476 | 3.610 | tNET | FF | 1 | R16C138[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe0_4_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.976 | 4.576 | tNET | RR | 1 | R16C138[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe0_4_s0/CLK |
| 10.725 | -0.250 | tSu | 1 | R16C138[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe0_4_s0 |
Path Statistics:
| Clock Skew | -0.026 |
| Setup Relationship | 6.400 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.601, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.610, 93.171%; tC2Q: 0.265, 6.829% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.576, 100.000% |
Path2
Path Summary:
| Slack | 2.250 |
| Data Arrival Time | 8.476 |
| Data Required Time | 10.725 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_4_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.601 | 4.601 | tNET | RR | 1 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
| 4.866 | 0.265 | tC2Q | RF | 1257 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
| 8.476 | 3.610 | tNET | FF | 1 | R16C138[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_4_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.976 | 4.576 | tNET | RR | 1 | R16C138[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_4_s0/CLK |
| 10.725 | -0.250 | tSu | 1 | R16C138[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_4_s0 |
Path Statistics:
| Clock Skew | -0.026 |
| Setup Relationship | 6.400 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.601, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.610, 93.171%; tC2Q: 0.265, 6.829% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.576, 100.000% |
Path3
Path Summary:
| Slack | 2.250 |
| Data Arrival Time | 8.476 |
| Data Required Time | 10.725 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr2ram_0_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.601 | 4.601 | tNET | RR | 1 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
| 4.866 | 0.265 | tC2Q | RF | 1257 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
| 8.476 | 3.610 | tNET | FF | 1 | R16C138[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr2ram_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.976 | 4.576 | tNET | RR | 1 | R16C138[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr2ram_0_s0/CLK |
| 10.725 | -0.250 | tSu | 1 | R16C138[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr2ram_0_s0 |
Path Statistics:
| Clock Skew | -0.026 |
| Setup Relationship | 6.400 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.601, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.610, 93.171%; tC2Q: 0.265, 6.829% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.576, 100.000% |
Path4
Path Summary:
| Slack | 2.250 |
| Data Arrival Time | 8.476 |
| Data Required Time | 10.725 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr2ram_1_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.601 | 4.601 | tNET | RR | 1 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
| 4.866 | 0.265 | tC2Q | RF | 1257 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
| 8.476 | 3.610 | tNET | FF | 1 | R16C138[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr2ram_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.976 | 4.576 | tNET | RR | 1 | R16C138[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr2ram_1_s0/CLK |
| 10.725 | -0.250 | tSu | 1 | R16C138[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr2ram_1_s0 |
Path Statistics:
| Clock Skew | -0.026 |
| Setup Relationship | 6.400 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.601, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.610, 93.171%; tC2Q: 0.265, 6.829% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.576, 100.000% |
Path5
Path Summary:
| Slack | 2.250 |
| Data Arrival Time | 8.476 |
| Data Required Time | 10.725 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr2ram_2_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.601 | 4.601 | tNET | RR | 1 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
| 4.866 | 0.265 | tC2Q | RF | 1257 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
| 8.476 | 3.610 | tNET | FF | 1 | R16C138[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr2ram_2_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.976 | 4.576 | tNET | RR | 1 | R16C138[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr2ram_2_s0/CLK |
| 10.725 | -0.250 | tSu | 1 | R16C138[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr2ram_2_s0 |
Path Statistics:
| Clock Skew | -0.026 |
| Setup Relationship | 6.400 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.601, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.610, 93.171%; tC2Q: 0.265, 6.829% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.576, 100.000% |
Path6
Path Summary:
| Slack | 2.256 |
| Data Arrival Time | 8.476 |
| Data Required Time | 10.732 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr2ram_3_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.601 | 4.601 | tNET | RR | 1 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
| 4.866 | 0.265 | tC2Q | RF | 1257 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
| 8.476 | 3.610 | tNET | FF | 1 | R16C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr2ram_3_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.982 | 4.582 | tNET | RR | 1 | R16C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr2ram_3_s0/CLK |
| 10.732 | -0.250 | tSu | 1 | R16C137[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr2ram_3_s0 |
Path Statistics:
| Clock Skew | -0.019 |
| Setup Relationship | 6.400 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.601, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.610, 93.171%; tC2Q: 0.265, 6.829% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.582, 100.000% |
Path7
Path Summary:
| Slack | 2.287 |
| Data Arrival Time | 8.457 |
| Data Required Time | 10.744 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_4_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.577 | 4.577 | tNET | RR | 1 | R35C128[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/CLK |
| 4.842 | 0.265 | tC2Q | RF | 450 | R35C128[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q |
| 8.457 | 3.616 | tNET | FF | 1 | R43C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_4_s0/PRESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.994 | 4.594 | tNET | RR | 1 | R43C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_4_s0/CLK |
| 10.744 | -0.250 | tSu | 1 | R43C130[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_4_s0 |
Path Statistics:
| Clock Skew | 0.017 |
| Setup Relationship | 6.400 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.577, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.616, 93.181%; tC2Q: 0.265, 6.819% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.594, 100.000% |
Path8
Path Summary:
| Slack | 2.287 |
| Data Arrival Time | 8.457 |
| Data Required Time | 10.744 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_tmp_4_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.577 | 4.577 | tNET | RR | 1 | R35C128[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/CLK |
| 4.842 | 0.265 | tC2Q | RF | 450 | R35C128[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q |
| 8.457 | 3.616 | tNET | FF | 1 | R43C130[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_tmp_4_s0/PRESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.994 | 4.594 | tNET | RR | 1 | R43C130[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_tmp_4_s0/CLK |
| 10.744 | -0.250 | tSu | 1 | R43C130[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_tmp_4_s0 |
Path Statistics:
| Clock Skew | 0.017 |
| Setup Relationship | 6.400 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.577, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.616, 93.181%; tC2Q: 0.265, 6.819% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.594, 100.000% |
Path9
Path Summary:
| Slack | 2.287 |
| Data Arrival Time | 8.457 |
| Data Required Time | 10.744 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d4_4_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.577 | 4.577 | tNET | RR | 1 | R35C128[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/CLK |
| 4.842 | 0.265 | tC2Q | RF | 450 | R35C128[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q |
| 8.457 | 3.616 | tNET | FF | 1 | R43C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d4_4_s0/PRESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.994 | 4.594 | tNET | RR | 1 | R43C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d4_4_s0/CLK |
| 10.744 | -0.250 | tSu | 1 | R43C130[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d4_4_s0 |
Path Statistics:
| Clock Skew | 0.017 |
| Setup Relationship | 6.400 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.577, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.616, 93.181%; tC2Q: 0.265, 6.819% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.594, 100.000% |
Path10
Path Summary:
| Slack | 2.287 |
| Data Arrival Time | 8.457 |
| Data Required Time | 10.744 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d3_4_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.577 | 4.577 | tNET | RR | 1 | R35C128[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/CLK |
| 4.842 | 0.265 | tC2Q | RF | 450 | R35C128[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q |
| 8.457 | 3.616 | tNET | FF | 1 | R43C130[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d3_4_s0/PRESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.994 | 4.594 | tNET | RR | 1 | R43C130[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d3_4_s0/CLK |
| 10.744 | -0.250 | tSu | 1 | R43C130[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d3_4_s0 |
Path Statistics:
| Clock Skew | 0.017 |
| Setup Relationship | 6.400 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.577, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.616, 93.181%; tC2Q: 0.265, 6.819% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.594, 100.000% |
Path11
Path Summary:
| Slack | 2.287 |
| Data Arrival Time | 8.457 |
| Data Required Time | 10.744 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d2_4_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.577 | 4.577 | tNET | RR | 1 | R35C128[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/CLK |
| 4.842 | 0.265 | tC2Q | RF | 450 | R35C128[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q |
| 8.457 | 3.616 | tNET | FF | 1 | R43C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d2_4_s0/PRESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.994 | 4.594 | tNET | RR | 1 | R43C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d2_4_s0/CLK |
| 10.744 | -0.250 | tSu | 1 | R43C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d2_4_s0 |
Path Statistics:
| Clock Skew | 0.017 |
| Setup Relationship | 6.400 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.577, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.616, 93.181%; tC2Q: 0.265, 6.819% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.594, 100.000% |
Path12
Path Summary:
| Slack | 2.288 |
| Data Arrival Time | 8.457 |
| Data Required Time | 10.746 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_31_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.577 | 4.577 | tNET | RR | 1 | R35C128[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/CLK |
| 4.842 | 0.265 | tC2Q | RF | 450 | R35C128[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q |
| 8.457 | 3.616 | tNET | FF | 1 | R42C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_31_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.996 | 4.596 | tNET | RR | 1 | R42C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_31_s0/CLK |
| 10.746 | -0.250 | tSu | 1 | R42C130[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_31_s0 |
Path Statistics:
| Clock Skew | 0.019 |
| Setup Relationship | 6.400 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.577, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.616, 93.181%; tC2Q: 0.265, 6.819% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.596, 100.000% |
Path13
Path Summary:
| Slack | 2.288 |
| Data Arrival Time | 8.457 |
| Data Required Time | 10.746 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_tmp_31_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.577 | 4.577 | tNET | RR | 1 | R35C128[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/CLK |
| 4.842 | 0.265 | tC2Q | RF | 450 | R35C128[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q |
| 8.457 | 3.616 | tNET | FF | 1 | R42C130[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_tmp_31_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.996 | 4.596 | tNET | RR | 1 | R42C130[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_tmp_31_s0/CLK |
| 10.746 | -0.250 | tSu | 1 | R42C130[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_tmp_31_s0 |
Path Statistics:
| Clock Skew | 0.019 |
| Setup Relationship | 6.400 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.577, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.616, 93.181%; tC2Q: 0.265, 6.819% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.596, 100.000% |
Path14
Path Summary:
| Slack | 2.314 |
| Data Arrival Time | 8.408 |
| Data Required Time | 10.722 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_pseudo_random_generators/dout_19_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.601 | 4.601 | tNET | RR | 1 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
| 4.866 | 0.265 | tC2Q | RF | 1257 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
| 8.408 | 3.542 | tNET | FF | 1 | R13C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_pseudo_random_generators/dout_19_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.972 | 4.572 | tNET | RR | 1 | R13C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_pseudo_random_generators/dout_19_s0/CLK |
| 10.722 | -0.250 | tSu | 1 | R13C141[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_pseudo_random_generators/dout_19_s0 |
Path Statistics:
| Clock Skew | -0.029 |
| Setup Relationship | 6.400 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.601, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.542, 93.050%; tC2Q: 0.265, 6.950% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.572, 100.000% |
Path15
Path Summary:
| Slack | 2.314 |
| Data Arrival Time | 8.408 |
| Data Required Time | 10.722 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_pseudo_random_generators/dout_62_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.601 | 4.601 | tNET | RR | 1 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
| 4.866 | 0.265 | tC2Q | RF | 1257 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
| 8.408 | 3.542 | tNET | FF | 1 | R13C141[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_pseudo_random_generators/dout_62_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.972 | 4.572 | tNET | RR | 1 | R13C141[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_pseudo_random_generators/dout_62_s0/CLK |
| 10.722 | -0.250 | tSu | 1 | R13C141[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_pseudo_random_generators/dout_62_s0 |
Path Statistics:
| Clock Skew | -0.029 |
| Setup Relationship | 6.400 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.601, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.542, 93.050%; tC2Q: 0.265, 6.950% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.572, 100.000% |
Path16
Path Summary:
| Slack | 2.314 |
| Data Arrival Time | 8.408 |
| Data Required Time | 10.722 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/phase_fifo_wr_data_47_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.601 | 4.601 | tNET | RR | 1 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
| 4.866 | 0.265 | tC2Q | RF | 1257 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
| 8.408 | 3.542 | tNET | FF | 1 | R13C141[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/phase_fifo_wr_data_47_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.972 | 4.572 | tNET | RR | 1 | R13C141[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/phase_fifo_wr_data_47_s0/CLK |
| 10.722 | -0.250 | tSu | 1 | R13C141[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/phase_fifo_wr_data_47_s0 |
Path Statistics:
| Clock Skew | -0.029 |
| Setup Relationship | 6.400 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.601, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.542, 93.050%; tC2Q: 0.265, 6.950% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.572, 100.000% |
Path17
Path Summary:
| Slack | 2.314 |
| Data Arrival Time | 8.408 |
| Data Required Time | 10.722 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/phase_fifo_wr_data_64_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.601 | 4.601 | tNET | RR | 1 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
| 4.866 | 0.265 | tC2Q | RF | 1257 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
| 8.408 | 3.542 | tNET | FF | 1 | R13C141[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/phase_fifo_wr_data_64_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.972 | 4.572 | tNET | RR | 1 | R13C141[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/phase_fifo_wr_data_64_s0/CLK |
| 10.722 | -0.250 | tSu | 1 | R13C141[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/phase_fifo_wr_data_64_s0 |
Path Statistics:
| Clock Skew | -0.029 |
| Setup Relationship | 6.400 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.601, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.542, 93.050%; tC2Q: 0.265, 6.950% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.572, 100.000% |
Path18
Path Summary:
| Slack | 2.314 |
| Data Arrival Time | 8.408 |
| Data Required Time | 10.722 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/phase_fifo_wr_data_65_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.601 | 4.601 | tNET | RR | 1 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
| 4.866 | 0.265 | tC2Q | RF | 1257 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
| 8.408 | 3.542 | tNET | FF | 1 | R13C141[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/phase_fifo_wr_data_65_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.972 | 4.572 | tNET | RR | 1 | R13C141[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/phase_fifo_wr_data_65_s0/CLK |
| 10.722 | -0.250 | tSu | 1 | R13C141[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/phase_fifo_wr_data_65_s0 |
Path Statistics:
| Clock Skew | -0.029 |
| Setup Relationship | 6.400 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.601, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.542, 93.050%; tC2Q: 0.265, 6.950% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.572, 100.000% |
Path19
Path Summary:
| Slack | 2.418 |
| Data Arrival Time | 8.300 |
| Data Required Time | 10.719 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_4_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.601 | 4.601 | tNET | RR | 1 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
| 4.866 | 0.265 | tC2Q | RF | 1257 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
| 8.300 | 3.434 | tNET | FF | 1 | R16C135[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_4_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.969 | 4.569 | tNET | RR | 1 | R16C135[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_4_s0/CLK |
| 10.719 | -0.250 | tSu | 1 | R16C135[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_4_s0 |
Path Statistics:
| Clock Skew | -0.032 |
| Setup Relationship | 6.400 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.601, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.434, 92.847%; tC2Q: 0.265, 7.153% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.569, 100.000% |
Path20
Path Summary:
| Slack | 2.418 |
| Data Arrival Time | 8.300 |
| Data Required Time | 10.719 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_0_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.601 | 4.601 | tNET | RR | 1 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
| 4.866 | 0.265 | tC2Q | RF | 1257 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
| 8.300 | 3.434 | tNET | FF | 1 | R16C135[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.969 | 4.569 | tNET | RR | 1 | R16C135[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_0_s0/CLK |
| 10.719 | -0.250 | tSu | 1 | R16C135[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_0_s0 |
Path Statistics:
| Clock Skew | -0.032 |
| Setup Relationship | 6.400 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.601, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.434, 92.847%; tC2Q: 0.265, 7.153% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.569, 100.000% |
Path21
Path Summary:
| Slack | 2.418 |
| Data Arrival Time | 8.300 |
| Data Required Time | 10.719 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_1_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.601 | 4.601 | tNET | RR | 1 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
| 4.866 | 0.265 | tC2Q | RF | 1257 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
| 8.300 | 3.434 | tNET | FF | 1 | R16C135[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.969 | 4.569 | tNET | RR | 1 | R16C135[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_1_s0/CLK |
| 10.719 | -0.250 | tSu | 1 | R16C135[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_1_s0 |
Path Statistics:
| Clock Skew | -0.032 |
| Setup Relationship | 6.400 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.601, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.434, 92.847%; tC2Q: 0.265, 7.153% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.569, 100.000% |
Path22
Path Summary:
| Slack | 2.418 |
| Data Arrival Time | 8.300 |
| Data Required Time | 10.719 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_2_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.601 | 4.601 | tNET | RR | 1 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
| 4.866 | 0.265 | tC2Q | RF | 1257 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
| 8.300 | 3.434 | tNET | FF | 1 | R16C135[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_2_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.969 | 4.569 | tNET | RR | 1 | R16C135[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_2_s0/CLK |
| 10.719 | -0.250 | tSu | 1 | R16C135[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_2_s0 |
Path Statistics:
| Clock Skew | -0.032 |
| Setup Relationship | 6.400 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.601, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.434, 92.847%; tC2Q: 0.265, 7.153% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.569, 100.000% |
Path23
Path Summary:
| Slack | 2.418 |
| Data Arrival Time | 8.300 |
| Data Required Time | 10.719 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_3_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.601 | 4.601 | tNET | RR | 1 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
| 4.866 | 0.265 | tC2Q | RF | 1257 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
| 8.300 | 3.434 | tNET | FF | 1 | R16C135[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_3_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.969 | 4.569 | tNET | RR | 1 | R16C135[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_3_s0/CLK |
| 10.719 | -0.250 | tSu | 1 | R16C135[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_3_s0 |
Path Statistics:
| Clock Skew | -0.032 |
| Setup Relationship | 6.400 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.601, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.434, 92.847%; tC2Q: 0.265, 7.153% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.569, 100.000% |
Path24
Path Summary:
| Slack | 2.425 |
| Data Arrival Time | 8.300 |
| Data Required Time | 10.725 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_dly1_0_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.601 | 4.601 | tNET | RR | 1 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
| 4.866 | 0.265 | tC2Q | RF | 1257 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
| 8.300 | 3.434 | tNET | FF | 1 | R16C136[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_dly1_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.976 | 4.576 | tNET | RR | 1 | R16C136[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_dly1_0_s0/CLK |
| 10.725 | -0.250 | tSu | 1 | R16C136[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_dly1_0_s0 |
Path Statistics:
| Clock Skew | -0.026 |
| Setup Relationship | 6.400 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.601, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.434, 92.847%; tC2Q: 0.265, 7.153% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.576, 100.000% |
Path25
Path Summary:
| Slack | 2.425 |
| Data Arrival Time | 8.300 |
| Data Required Time | 10.725 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_dly1_1_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 4.601 | 4.601 | tNET | RR | 1 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
| 4.866 | 0.265 | tC2Q | RF | 1257 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
| 8.300 | 3.434 | tNET | FF | 1 | R16C136[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_dly1_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 6.400 | 6.400 | active clock edge time | ||||
| 6.400 | 0.000 | xgmii_clk | ||||
| 6.400 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 10.976 | 4.576 | tNET | RR | 1 | R16C136[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_dly1_1_s0/CLK |
| 10.725 | -0.250 | tSu | 1 | R16C136[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_dly1_1_s0 |
Path Statistics:
| Clock Skew | -0.026 |
| Setup Relationship | 6.400 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 4.601, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.434, 92.847%; tC2Q: 0.265, 7.153% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 4.576, 100.000% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 0.335 |
| Data Arrival Time | 1.073 |
| Data Required Time | 0.737 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_wr_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_wr_d1_2_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 0.809 | 0.809 | tNET | RR | 1 | R42C128[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_wr_rstn_d2_s0/CLK |
| 0.938 | 0.130 | tC2Q | RR | 458 | R42C128[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_wr_rstn_d2_s0/Q |
| 1.073 | 0.134 | tNET | RR | 1 | R50C129[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_wr_d1_2_s0/PRESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 0.785 | 0.785 | tNET | RR | 1 | R50C129[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_wr_d1_2_s0/CLK |
| 0.737 | -0.048 | tHld | 1 | R50C129[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_wr_d1_2_s0 |
Path Statistics:
| Clock Skew | -0.024 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.809, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.134, 50.853%; tC2Q: 0.130, 49.147% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.785, 100.000% |
Path2
Path Summary:
| Slack | 0.335 |
| Data Arrival Time | 1.073 |
| Data Required Time | 0.737 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_wr_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_wr_d1_10_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 0.809 | 0.809 | tNET | RR | 1 | R42C128[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_wr_rstn_d2_s0/CLK |
| 0.938 | 0.130 | tC2Q | RR | 458 | R42C128[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_wr_rstn_d2_s0/Q |
| 1.073 | 0.134 | tNET | RR | 1 | R50C129[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_wr_d1_10_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 0.785 | 0.785 | tNET | RR | 1 | R50C129[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_wr_d1_10_s0/CLK |
| 0.737 | -0.048 | tHld | 1 | R50C129[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_wr_d1_10_s0 |
Path Statistics:
| Clock Skew | -0.024 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.809, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.134, 50.853%; tC2Q: 0.130, 49.147% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.785, 100.000% |
Path3
Path Summary:
| Slack | 0.335 |
| Data Arrival Time | 1.073 |
| Data Required Time | 0.737 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_wr_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_wr_d1_16_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 0.809 | 0.809 | tNET | RR | 1 | R42C128[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_wr_rstn_d2_s0/CLK |
| 0.938 | 0.130 | tC2Q | RR | 458 | R42C128[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_wr_rstn_d2_s0/Q |
| 1.073 | 0.134 | tNET | RR | 1 | R50C129[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_wr_d1_16_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 0.785 | 0.785 | tNET | RR | 1 | R50C129[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_wr_d1_16_s0/CLK |
| 0.737 | -0.048 | tHld | 1 | R50C129[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_wr_d1_16_s0 |
Path Statistics:
| Clock Skew | -0.024 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.809, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.134, 50.853%; tC2Q: 0.130, 49.147% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.785, 100.000% |
Path4
Path Summary:
| Slack | 0.335 |
| Data Arrival Time | 1.073 |
| Data Required Time | 0.737 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_wr_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_wr_d1_37_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 0.809 | 0.809 | tNET | RR | 1 | R42C128[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_wr_rstn_d2_s0/CLK |
| 0.938 | 0.130 | tC2Q | RR | 458 | R42C128[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_wr_rstn_d2_s0/Q |
| 1.073 | 0.134 | tNET | RR | 1 | R50C129[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_wr_d1_37_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 0.785 | 0.785 | tNET | RR | 1 | R50C129[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_wr_d1_37_s0/CLK |
| 0.737 | -0.048 | tHld | 1 | R50C129[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_wr_d1_37_s0 |
Path Statistics:
| Clock Skew | -0.024 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.809, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.134, 50.853%; tC2Q: 0.130, 49.147% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.785, 100.000% |
Path5
Path Summary:
| Slack | 0.351 |
| Data Arrival Time | 2.619 |
| Data Required Time | 2.269 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_0_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.312 | 2.312 | tNET | RR | 1 | R35C128[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/CLK |
| 2.441 | 0.130 | tC2Q | RR | 450 | R35C128[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q |
| 2.619 | 0.178 | tNET | RR | 1 | R36C129[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.316 | 2.316 | tNET | RR | 1 | R36C129[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_0_s0/CLK |
| 2.269 | -0.048 | tHld | 1 | R36C129[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_0_s0 |
Path Statistics:
| Clock Skew | 0.005 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.312, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.178, 57.895%; tC2Q: 0.130, 42.105% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.316, 100.000% |
Path6
Path Summary:
| Slack | 0.351 |
| Data Arrival Time | 2.619 |
| Data Required Time | 2.269 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_tmp_0_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.312 | 2.312 | tNET | RR | 1 | R35C128[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/CLK |
| 2.441 | 0.130 | tC2Q | RR | 450 | R35C128[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q |
| 2.619 | 0.178 | tNET | RR | 1 | R36C129[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_tmp_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.316 | 2.316 | tNET | RR | 1 | R36C129[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_tmp_0_s0/CLK |
| 2.269 | -0.048 | tHld | 1 | R36C129[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_tmp_0_s0 |
Path Statistics:
| Clock Skew | 0.005 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.312, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.178, 57.895%; tC2Q: 0.130, 42.105% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.316, 100.000% |
Path7
Path Summary:
| Slack | 0.351 |
| Data Arrival Time | 2.619 |
| Data Required Time | 2.269 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d4_0_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.312 | 2.312 | tNET | RR | 1 | R35C128[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/CLK |
| 2.441 | 0.130 | tC2Q | RR | 450 | R35C128[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q |
| 2.619 | 0.178 | tNET | RR | 1 | R36C129[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d4_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.316 | 2.316 | tNET | RR | 1 | R36C129[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d4_0_s0/CLK |
| 2.269 | -0.048 | tHld | 1 | R36C129[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d4_0_s0 |
Path Statistics:
| Clock Skew | 0.005 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.312, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.178, 57.895%; tC2Q: 0.130, 42.105% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.316, 100.000% |
Path8
Path Summary:
| Slack | 0.351 |
| Data Arrival Time | 2.619 |
| Data Required Time | 2.269 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d3_0_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.312 | 2.312 | tNET | RR | 1 | R35C128[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/CLK |
| 2.441 | 0.130 | tC2Q | RR | 450 | R35C128[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q |
| 2.619 | 0.178 | tNET | RR | 1 | R36C129[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d3_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.316 | 2.316 | tNET | RR | 1 | R36C129[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d3_0_s0/CLK |
| 2.269 | -0.048 | tHld | 1 | R36C129[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d3_0_s0 |
Path Statistics:
| Clock Skew | 0.005 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.312, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.178, 57.895%; tC2Q: 0.130, 42.105% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.316, 100.000% |
Path9
Path Summary:
| Slack | 0.351 |
| Data Arrival Time | 2.619 |
| Data Required Time | 2.269 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d2_0_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.312 | 2.312 | tNET | RR | 1 | R35C128[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/CLK |
| 2.441 | 0.130 | tC2Q | RR | 450 | R35C128[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q |
| 2.619 | 0.178 | tNET | RR | 1 | R36C129[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d2_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.316 | 2.316 | tNET | RR | 1 | R36C129[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d2_0_s0/CLK |
| 2.269 | -0.048 | tHld | 1 | R36C129[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d2_0_s0 |
Path Statistics:
| Clock Skew | 0.005 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.312, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.178, 57.895%; tC2Q: 0.130, 42.105% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.316, 100.000% |
Path10
Path Summary:
| Slack | 0.361 |
| Data Arrival Time | 2.621 |
| Data Required Time | 2.260 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_5_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.312 | 2.312 | tNET | RR | 1 | R35C128[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/CLK |
| 2.441 | 0.130 | tC2Q | RR | 450 | R35C128[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q |
| 2.621 | 0.180 | tNET | RR | 1 | R35C131[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_5_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.308 | 2.308 | tNET | RR | 1 | R35C131[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_5_s0/CLK |
| 2.260 | -0.048 | tHld | 1 | R35C131[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_5_s0 |
Path Statistics:
| Clock Skew | -0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.312, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.180, 58.140%; tC2Q: 0.130, 41.860% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.308, 100.000% |
Path11
Path Summary:
| Slack | 0.361 |
| Data Arrival Time | 2.621 |
| Data Required Time | 2.260 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_tmp_5_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.312 | 2.312 | tNET | RR | 1 | R35C128[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/CLK |
| 2.441 | 0.130 | tC2Q | RR | 450 | R35C128[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q |
| 2.621 | 0.180 | tNET | RR | 1 | R35C131[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_tmp_5_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.308 | 2.308 | tNET | RR | 1 | R35C131[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_tmp_5_s0/CLK |
| 2.260 | -0.048 | tHld | 1 | R35C131[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_tmp_5_s0 |
Path Statistics:
| Clock Skew | -0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.312, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.180, 58.140%; tC2Q: 0.130, 41.860% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.308, 100.000% |
Path12
Path Summary:
| Slack | 0.361 |
| Data Arrival Time | 2.621 |
| Data Required Time | 2.260 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d4_5_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.312 | 2.312 | tNET | RR | 1 | R35C128[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/CLK |
| 2.441 | 0.130 | tC2Q | RR | 450 | R35C128[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q |
| 2.621 | 0.180 | tNET | RR | 1 | R35C131[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d4_5_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.308 | 2.308 | tNET | RR | 1 | R35C131[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d4_5_s0/CLK |
| 2.260 | -0.048 | tHld | 1 | R35C131[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d4_5_s0 |
Path Statistics:
| Clock Skew | -0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.312, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.180, 58.140%; tC2Q: 0.130, 41.860% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.308, 100.000% |
Path13
Path Summary:
| Slack | 0.361 |
| Data Arrival Time | 2.621 |
| Data Required Time | 2.260 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d3_5_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.312 | 2.312 | tNET | RR | 1 | R35C128[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/CLK |
| 2.441 | 0.130 | tC2Q | RR | 450 | R35C128[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q |
| 2.621 | 0.180 | tNET | RR | 1 | R35C131[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d3_5_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.308 | 2.308 | tNET | RR | 1 | R35C131[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d3_5_s0/CLK |
| 2.260 | -0.048 | tHld | 1 | R35C131[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d3_5_s0 |
Path Statistics:
| Clock Skew | -0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.312, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.180, 58.140%; tC2Q: 0.130, 41.860% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.308, 100.000% |
Path14
Path Summary:
| Slack | 0.361 |
| Data Arrival Time | 2.621 |
| Data Required Time | 2.260 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d2_5_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.312 | 2.312 | tNET | RR | 1 | R35C128[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/CLK |
| 2.441 | 0.130 | tC2Q | RR | 450 | R35C128[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/ctc_rd_rstn_d2_s0/Q |
| 2.621 | 0.180 | tNET | RR | 1 | R35C131[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d2_5_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.308 | 2.308 | tNET | RR | 1 | R35C131[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d2_5_s0/CLK |
| 2.260 | -0.048 | tHld | 1 | R35C131[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/rxd_rd_d2_5_s0 |
Path Statistics:
| Clock Skew | -0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.312, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.180, 58.140%; tC2Q: 0.130, 41.860% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.308, 100.000% |
Path15
Path Summary:
| Slack | 0.362 |
| Data Arrival Time | 1.129 |
| Data Required Time | 0.767 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_rx_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/block_payload_d3_21_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 0.812 | 0.812 | tNET | RR | 1 | R38C119[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_rx_rstn_d2_s0/CLK |
| 0.941 | 0.130 | tC2Q | RR | 1100 | R38C119[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_rx_rstn_d2_s0/Q |
| 1.129 | 0.188 | tNET | RR | 1 | R38C120[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/block_payload_d3_21_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 0.815 | 0.815 | tNET | RR | 1 | R38C120[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/block_payload_d3_21_s0/CLK |
| 0.767 | -0.048 | tHld | 1 | R38C120[3][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/block_payload_d3_21_s0 |
Path Statistics:
| Clock Skew | 0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.812, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.188, 59.207%; tC2Q: 0.130, 40.793% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.815, 100.000% |
Path16
Path Summary:
| Slack | 0.362 |
| Data Arrival Time | 1.129 |
| Data Required Time | 0.767 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_rx_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/block_payload_d2_21_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 0.812 | 0.812 | tNET | RR | 1 | R38C119[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_rx_rstn_d2_s0/CLK |
| 0.941 | 0.130 | tC2Q | RR | 1100 | R38C119[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_rx_rstn_d2_s0/Q |
| 1.129 | 0.188 | tNET | RR | 1 | R38C120[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/block_payload_d2_21_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 0.815 | 0.815 | tNET | RR | 1 | R38C120[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/block_payload_d2_21_s0/CLK |
| 0.767 | -0.048 | tHld | 1 | R38C120[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/block_payload_d2_21_s0 |
Path Statistics:
| Clock Skew | 0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.812, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.188, 59.207%; tC2Q: 0.130, 40.793% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.815, 100.000% |
Path17
Path Summary:
| Slack | 0.362 |
| Data Arrival Time | 1.129 |
| Data Required Time | 0.767 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_rx_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/block_payload_d2_41_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 0.812 | 0.812 | tNET | RR | 1 | R38C119[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_rx_rstn_d2_s0/CLK |
| 0.941 | 0.130 | tC2Q | RR | 1100 | R38C119[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_rx_rstn_d2_s0/Q |
| 1.129 | 0.188 | tNET | RR | 1 | R38C120[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/block_payload_d2_41_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 0.815 | 0.815 | tNET | RR | 1 | R38C120[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/block_payload_d2_41_s0/CLK |
| 0.767 | -0.048 | tHld | 1 | R38C120[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/block_payload_d2_41_s0 |
Path Statistics:
| Clock Skew | 0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.812, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.188, 59.207%; tC2Q: 0.130, 40.793% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.815, 100.000% |
Path18
Path Summary:
| Slack | 0.362 |
| Data Arrival Time | 1.129 |
| Data Required Time | 0.767 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_rx_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/block_payload_d1_14_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 0.812 | 0.812 | tNET | RR | 1 | R38C119[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_rx_rstn_d2_s0/CLK |
| 0.941 | 0.130 | tC2Q | RR | 1100 | R38C119[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_rx_rstn_d2_s0/Q |
| 1.129 | 0.188 | tNET | RR | 1 | R38C120[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/block_payload_d1_14_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 0.815 | 0.815 | tNET | RR | 1 | R38C120[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/block_payload_d1_14_s0/CLK |
| 0.767 | -0.048 | tHld | 1 | R38C120[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/block_payload_d1_14_s0 |
Path Statistics:
| Clock Skew | 0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.812, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.188, 59.207%; tC2Q: 0.130, 40.793% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.815, 100.000% |
Path19
Path Summary:
| Slack | 0.362 |
| Data Arrival Time | 1.129 |
| Data Required Time | 0.767 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_rx_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/block_payload_d1_39_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 0.812 | 0.812 | tNET | RR | 1 | R38C119[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_rx_rstn_d2_s0/CLK |
| 0.941 | 0.130 | tC2Q | RR | 1100 | R38C119[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_rx_rstn_d2_s0/Q |
| 1.129 | 0.188 | tNET | RR | 1 | R38C120[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/block_payload_d1_39_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 0.815 | 0.815 | tNET | RR | 1 | R38C120[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/block_payload_d1_39_s0/CLK |
| 0.767 | -0.048 | tHld | 1 | R38C120[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/block_payload_d1_39_s0 |
Path Statistics:
| Clock Skew | 0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.812, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.188, 59.207%; tC2Q: 0.130, 40.793% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.815, 100.000% |
Path20
Path Summary:
| Slack | 0.362 |
| Data Arrival Time | 1.129 |
| Data Required Time | 0.767 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_rx_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/block_payload_d1_41_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 0.812 | 0.812 | tNET | RR | 1 | R38C119[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_rx_rstn_d2_s0/CLK |
| 0.941 | 0.130 | tC2Q | RR | 1100 | R38C119[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_rx_rstn_d2_s0/Q |
| 1.129 | 0.188 | tNET | RR | 1 | R38C120[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/block_payload_d1_41_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 0.815 | 0.815 | tNET | RR | 1 | R38C120[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/block_payload_d1_41_s0/CLK |
| 0.767 | -0.048 | tHld | 1 | R38C120[1][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/block_payload_d1_41_s0 |
Path Statistics:
| Clock Skew | 0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.812, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.188, 59.207%; tC2Q: 0.130, 40.793% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.815, 100.000% |
Path21
Path Summary:
| Slack | 0.362 |
| Data Arrival Time | 1.129 |
| Data Required Time | 0.767 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_rx_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/block_payload_d1_52_s0 |
| Launch Clk | serdes_rx_clk:[R] |
| Latch Clk | serdes_rx_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 0.812 | 0.812 | tNET | RR | 1 | R38C119[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_rx_rstn_d2_s0/CLK |
| 0.941 | 0.130 | tC2Q | RR | 1100 | R38C119[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_rx_rstn_d2_s0/Q |
| 1.129 | 0.188 | tNET | RR | 1 | R38C120[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/block_payload_d1_52_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | serdes_rx_clk | ||||
| 0.000 | 0.000 | tCL | RR | 2038 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/LANE1_PCS_RX_O_FABRIC_CLK |
| 0.815 | 0.815 | tNET | RR | 1 | R38C120[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/block_payload_d1_52_s0/CLK |
| 0.767 | -0.048 | tHld | 1 | R38C120[0][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_decoder_64b66b/block_payload_d1_52_s0 |
Path Statistics:
| Clock Skew | 0.004 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.812, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.188, 59.207%; tC2Q: 0.130, 40.793% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.815, 100.000% |
Path22
Path Summary:
| Slack | 0.364 |
| Data Arrival Time | 2.646 |
| Data Required Time | 2.282 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d4_44_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.331 | 2.331 | tNET | RR | 1 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
| 2.461 | 0.130 | tC2Q | RR | 1257 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
| 2.646 | 0.185 | tNET | RR | 1 | R4C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d4_44_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.329 | 2.329 | tNET | RR | 1 | R4C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d4_44_s0/CLK |
| 2.282 | -0.048 | tHld | 1 | R4C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d4_44_s0 |
Path Statistics:
| Clock Skew | -0.002 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.331, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.185, 58.857%; tC2Q: 0.130, 41.143% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.329, 100.000% |
Path23
Path Summary:
| Slack | 0.364 |
| Data Arrival Time | 2.646 |
| Data Required Time | 2.282 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d3_44_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.331 | 2.331 | tNET | RR | 1 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
| 2.461 | 0.130 | tC2Q | RR | 1257 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
| 2.646 | 0.185 | tNET | RR | 1 | R4C126[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d3_44_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.329 | 2.329 | tNET | RR | 1 | R4C126[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d3_44_s0/CLK |
| 2.282 | -0.048 | tHld | 1 | R4C126[2][B] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d3_44_s0 |
Path Statistics:
| Clock Skew | -0.002 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.331, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.185, 58.857%; tC2Q: 0.130, 41.143% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.329, 100.000% |
Path24
Path Summary:
| Slack | 0.364 |
| Data Arrival Time | 2.646 |
| Data Required Time | 2.282 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d3_50_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.331 | 2.331 | tNET | RR | 1 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
| 2.461 | 0.130 | tC2Q | RR | 1257 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
| 2.646 | 0.185 | tNET | RR | 1 | R4C126[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d3_50_s0/PRESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.329 | 2.329 | tNET | RR | 1 | R4C126[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d3_50_s0/CLK |
| 2.282 | -0.048 | tHld | 1 | R4C126[0][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d3_50_s0 |
Path Statistics:
| Clock Skew | -0.002 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.331, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.185, 58.857%; tC2Q: 0.130, 41.143% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.329, 100.000% |
Path25
Path Summary:
| Slack | 0.364 |
| Data Arrival Time | 2.646 |
| Data Required Time | 2.282 |
| From | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0 |
| To | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d2_44_s0 |
| Launch Clk | xgmii_clk:[R] |
| Latch Clk | xgmii_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.331 | 2.331 | tNET | RR | 1 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/CLK |
| 2.461 | 0.130 | tC2Q | RR | 1257 | R3C126[2][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/xgmii_tx_rstn_d2_s0/Q |
| 2.646 | 0.185 | tNET | RR | 1 | R4C126[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d2_44_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | xgmii_clk | ||||
| 0.000 | 0.000 | tCL | RR | 5587 | R0C38 | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 2.329 | 2.329 | tNET | RR | 1 | R4C126[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d2_44_s0/CLK |
| 2.282 | -0.048 | tHld | 1 | R4C126[1][A] | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_encoder_64b66b/xgmii_txd_d2_44_s0 |
Path Statistics:
| Clock Skew | -0.002 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.331, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.185, 58.857%; tC2Q: 0.130, 41.143% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.329, 100.000% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
| Slack: | 0.371 |
| Actual Width: | 1.146 |
| Required Width: | 0.776 |
| Type: | Low Pulse Width |
| Clock: | xgmii_clk |
| Objects: | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPB_mem_mem_0_0_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 3.200 | 0.000 | active clock edge time | ||
| 3.200 | 0.000 | xgmii_clk | ||
| 3.200 | 0.000 | tCL | FF | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 7.572 | 4.372 | tNET | FF | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPB_mem_mem_0_0_s/CLKA |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 6.400 | 0.000 | active clock edge time | ||
| 6.400 | 0.000 | xgmii_clk | ||
| 6.400 | 0.000 | tCL | RR | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 8.718 | 2.318 | tNET | RR | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPB_mem_mem_0_0_s/CLKA |
MPW2
MPW Summary:
| Slack: | 0.374 |
| Actual Width: | 1.150 |
| Required Width: | 0.776 |
| Type: | Low Pulse Width |
| Clock: | xgmii_clk |
| Objects: | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 3.200 | 0.000 | active clock edge time | ||
| 3.200 | 0.000 | xgmii_clk | ||
| 3.200 | 0.000 | tCL | FF | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 7.565 | 4.365 | tNET | FF | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s/CLKB |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 6.400 | 0.000 | active clock edge time | ||
| 6.400 | 0.000 | xgmii_clk | ||
| 6.400 | 0.000 | tCL | RR | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 8.715 | 2.315 | tNET | RR | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_0_s/CLKB |
MPW3
MPW Summary:
| Slack: | 0.374 |
| Actual Width: | 1.150 |
| Required Width: | 0.776 |
| Type: | Low Pulse Width |
| Clock: | xgmii_clk |
| Objects: | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 3.200 | 0.000 | active clock edge time | ||
| 3.200 | 0.000 | xgmii_clk | ||
| 3.200 | 0.000 | tCL | FF | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 7.565 | 4.365 | tNET | FF | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/CLKA |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 6.400 | 0.000 | active clock edge time | ||
| 6.400 | 0.000 | xgmii_clk | ||
| 6.400 | 0.000 | tCL | RR | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 8.715 | 2.315 | tNET | RR | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/CLKA |
MPW4
MPW Summary:
| Slack: | 0.374 |
| Actual Width: | 1.150 |
| Required Width: | 0.776 |
| Type: | Low Pulse Width |
| Clock: | xgmii_clk |
| Objects: | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 3.200 | 0.000 | active clock edge time | ||
| 3.200 | 0.000 | xgmii_clk | ||
| 3.200 | 0.000 | tCL | FF | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 7.565 | 4.365 | tNET | FF | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 6.400 | 0.000 | active clock edge time | ||
| 6.400 | 0.000 | xgmii_clk | ||
| 6.400 | 0.000 | tCL | RR | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 8.715 | 2.315 | tNET | RR | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA |
MPW5
MPW Summary:
| Slack: | 0.377 |
| Actual Width: | 1.153 |
| Required Width: | 0.776 |
| Type: | Low Pulse Width |
| Clock: | xgmii_clk |
| Objects: | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_1_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 3.200 | 0.000 | active clock edge time | ||
| 3.200 | 0.000 | xgmii_clk | ||
| 3.200 | 0.000 | tCL | FF | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 7.558 | 4.358 | tNET | FF | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_1_s/CLKB |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 6.400 | 0.000 | active clock edge time | ||
| 6.400 | 0.000 | xgmii_clk | ||
| 6.400 | 0.000 | tCL | RR | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 8.711 | 2.311 | tNET | RR | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/mem_mem_0_1_s/CLKB |
MPW6
MPW Summary:
| Slack: | 0.377 |
| Actual Width: | 1.153 |
| Required Width: | 0.776 |
| Type: | Low Pulse Width |
| Clock: | xgmii_clk |
| Objects: | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 3.200 | 0.000 | active clock edge time | ||
| 3.200 | 0.000 | xgmii_clk | ||
| 3.200 | 0.000 | tCL | FF | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 7.558 | 4.358 | tNET | FF | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/CLKA |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 6.400 | 0.000 | active clock edge time | ||
| 6.400 | 0.000 | xgmii_clk | ||
| 6.400 | 0.000 | tCL | RR | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 8.711 | 2.311 | tNET | RR | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/phase_fifo_rd_data_phase_fifo_rd_data_0_1_s/CLKA |
MPW7
MPW Summary:
| Slack: | 0.377 |
| Actual Width: | 1.153 |
| Required Width: | 0.776 |
| Type: | Low Pulse Width |
| Clock: | xgmii_clk |
| Objects: | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 3.200 | 0.000 | active clock edge time | ||
| 3.200 | 0.000 | xgmii_clk | ||
| 3.200 | 0.000 | tCL | FF | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 7.558 | 4.358 | tNET | FF | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 6.400 | 0.000 | active clock edge time | ||
| 6.400 | 0.000 | xgmii_clk | ||
| 6.400 | 0.000 | tCL | RR | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 8.711 | 2.311 | tNET | RR | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA |
MPW8
MPW Summary:
| Slack: | 0.377 |
| Actual Width: | 1.153 |
| Required Width: | 0.776 |
| Type: | Low Pulse Width |
| Clock: | xgmii_clk |
| Objects: | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/gowin_add_SDPX9B_phase_fifo_rd_data_phase_fifo_rd_data_0_0_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 3.200 | 0.000 | active clock edge time | ||
| 3.200 | 0.000 | xgmii_clk | ||
| 3.200 | 0.000 | tCL | FF | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 7.558 | 4.358 | tNET | FF | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/gowin_add_SDPX9B_phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/CLKA |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 6.400 | 0.000 | active clock edge time | ||
| 6.400 | 0.000 | xgmii_clk | ||
| 6.400 | 0.000 | tCL | RR | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 8.711 | 2.311 | tNET | RR | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/gowin_add_SDPX9B_phase_fifo_rd_data_phase_fifo_rd_data_0_0_s/CLKA |
MPW9
MPW Summary:
| Slack: | 0.377 |
| Actual Width: | 1.153 |
| Required Width: | 0.776 |
| Type: | Low Pulse Width |
| Clock: | xgmii_clk |
| Objects: | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/gowin_add_SDPX9B_mem_mem_0_1_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 3.200 | 0.000 | active clock edge time | ||
| 3.200 | 0.000 | xgmii_clk | ||
| 3.200 | 0.000 | tCL | FF | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 7.558 | 4.358 | tNET | FF | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/gowin_add_SDPX9B_mem_mem_0_1_s/CLKB |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 6.400 | 0.000 | active clock edge time | ||
| 6.400 | 0.000 | xgmii_clk | ||
| 6.400 | 0.000 | tCL | RR | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 8.711 | 2.311 | tNET | RR | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/gowin_add_SDPX9B_mem_mem_0_1_s/CLKB |
MPW10
MPW Summary:
| Slack: | 0.377 |
| Actual Width: | 1.153 |
| Required Width: | 0.776 |
| Type: | Low Pulse Width |
| Clock: | xgmii_clk |
| Objects: | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPB_mem_mem_0_2_s |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 3.200 | 0.000 | active clock edge time | ||
| 3.200 | 0.000 | xgmii_clk | ||
| 3.200 | 0.000 | tCL | FF | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 7.558 | 4.358 | tNET | FF | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPB_mem_mem_0_2_s/CLKA |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 6.400 | 0.000 | active clock edge time | ||
| 6.400 | 0.000 | xgmii_clk | ||
| 6.400 | 0.000 | tCL | RR | u_SerDes_Top/gtr12_quad_inst1/FABRIC_LANE1_CMU_CK_REF_O |
| 8.711 | 2.311 | tNET | RR | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/gowin_add_SDPB_mem_mem_0_2_s/CLKA |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
| FANOUT | NET NAME | WORST SLACK | MAX DELAY |
|---|---|---|---|
| 5587 | tx_mac_clk | 0.875 | 4.655 |
| 2885 | block_lock | 1.096 | 3.432 |
| 2038 | u_SerDes_Top/q1_lane1_fabric_rx_clk | 0.959 | 1.726 |
| 646 | u_SerDes_Top/q1_lane1_fabric_tx_clk | 1.278 | 1.726 |
| 584 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/descrambler_valid_out | 2.964 | 2.825 |
| 358 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/baser_tx_rstn_d2 | 1.278 | 3.415 |
| 356 | gw_gao_inst_0/control0[0] | 20.125 | 4.095 |
| 349 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_ctc/vld_rd_d1 | 2.748 | 2.085 |
| 267 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_rx_data/u_gearbox_64_66_lock/u_gearbox_64_66/cnt[2] | 2.902 | 2.554 |
| 256 | u_SerDes_Top/Ten_Giga_Serial_Ethernet_Top_inst/u_xg_baser/u_xg_baser_data/u_tx_data/u_gearbox_66_64/rd_en_cnt_d2[2] | 3.692 | 1.775 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
| GRID LOC | ROUTE CONGESTIONS |
|---|---|
| R29C102 | 66.67% |
| R22C95 | 63.89% |
| R24C94 | 63.89% |
| R6C112 | 62.50% |
| R5C110 | 61.11% |
| R7C113 | 61.11% |
| R8C110 | 61.11% |
| R4C110 | 61.11% |
| R4C112 | 61.11% |
| R6C111 | 61.11% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
| SDC Command Type | State | Detail Command |
|---|---|---|
| TC_CLOCK | Actived | create_clock -name serdes_tx_clk -period 6.173 -waveform {0 3.087} [get_nets {u_SerDes_Top/q1_lane1_fabric_tx_clk}] |
| TC_CLOCK | Actived | create_clock -name serdes_rx_clk -period 6.173 -waveform {0 3.087} [get_nets {u_SerDes_Top/q1_lane1_fabric_rx_clk}] |
| TC_CLOCK | Actived | create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_nets {tck_pad_i}] |
| TC_CLOCK | Actived | create_clock -name xgmii_clk -period 6.4 -waveform {0 3.2} [get_nets {tx_mac_clk}] |
| TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {serdes_rx_clk}] -group [get_clocks {serdes_tx_clk}] -group [get_clocks {xgmii_clk}] -group [get_clocks {tck_pad_i}] |
| TC_REPORT_TIMING | Actived | report_timing -setup -from_clock [get_clocks {serdes_rx_clk}] -to_clock [get_clocks {serdes_rx_clk}] -max_paths 50 -max_common_paths 1 |
| TC_REPORT_TIMING | Actived | report_timing -setup -from_clock [get_clocks {serdes_tx_clk}] -to_clock [get_clocks {serdes_tx_clk}] -max_paths 50 -max_common_paths 1 |
| TC_REPORT_TIMING | Actived | report_timing -setup -from_clock [get_clocks {xgmii_clk}] -to_clock [get_clocks {xgmii_clk}] -max_paths 50 -max_common_paths 1 |