Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\SERDES_IP\IPlib\10GSERETH\data\xg_baser_wrapper.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\ipcore\SERDES_IP\IPlib\10GSERETH\data\xg_baser.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12.02 (64-bit) |
| Part Number | GW5AST-LV138FPG676AC2/I1 |
| Device | GW5AST-138 |
| Device Version | B |
| Created Time | Wed Mar 4 10:24:04 2026 |
| Legal Announcement | Copyright (C)2014-2026 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | Ten_Giga_Serial_Ethernet_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 113.023MB Running netlist conversion: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.117s, Peak memory usage = 113.023MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.231s, Peak memory usage = 113.023MB Optimizing Phase 1: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.307s, Peak memory usage = 113.023MB Optimizing Phase 2: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.209s, Peak memory usage = 113.023MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.335s, Peak memory usage = 113.023MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 113.023MB Inferring Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.08s, Peak memory usage = 113.023MB Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 113.023MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.117s, Peak memory usage = 113.023MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.115s, Peak memory usage = 113.023MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.036s, Peak memory usage = 113.023MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.421s, Elapsed time = 0h 0m 0.456s, Peak memory usage = 118.641MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.211s, Peak memory usage = 118.641MB Generate output files: CPU time = 0h 0m 0.453s, Elapsed time = 0h 0m 0.529s, Peak memory usage = 143.961MB |
| Total Time and Memory Usage | CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 143.961MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 381 |
| I/O Buf | 347 |
| IBUF | 152 |
| OBUF | 195 |
| Register | 4475 |
| DFFSE | 64 |
| DFFRE | 232 |
| DFFPE | 618 |
| DFFCE | 3561 |
| LUT | 3483 |
| LUT2 | 405 |
| LUT3 | 1515 |
| LUT4 | 1563 |
| ALU | 34 |
| ALU | 34 |
| INV | 48 |
| INV | 48 |
| BSRAM | 4 |
| SDPX9B | 4 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 3565(3531 LUT, 34 ALU) / 138240 | 3% |
| Register | 4475 / 139140 | 4% |
| --Register as Latch | 0 / 139140 | 0% |
| --Register as FF | 4475 / 139140 | 4% |
| BSRAM | 4 / 340 | 2% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | xgmii_tx_clk_i | Base | 10.000 | 100.000 | 0.000 | 5.000 | xgmii_tx_clk_i_ibuf/I | ||
| 2 | serdes_pcs_tx_clk_i | Base | 10.000 | 100.000 | 0.000 | 5.000 | serdes_pcs_tx_clk_i_ibuf/I | ||
| 3 | serdes_pcs_rx_clk_i | Base | 10.000 | 100.000 | 0.000 | 5.000 | serdes_pcs_rx_clk_i_ibuf/I | ||
| 4 | xgmii_rx_clk_i | Base | 10.000 | 100.000 | 0.000 | 5.000 | xgmii_rx_clk_i_ibuf/I |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | xgmii_tx_clk_i | 100.000(MHz) | 218.551(MHz) | 7 | TOP |
| 2 | serdes_pcs_tx_clk_i | 100.000(MHz) | 220.284(MHz) | 7 | TOP |
| 3 | serdes_pcs_rx_clk_i | 100.000(MHz) | 240.240(MHz) | 6 | TOP |
| 4 | xgmii_rx_clk_i | 100.000(MHz) | 258.038(MHz) | 4 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 5.424 |
| Data Arrival Time | 4.648 |
| Data Required Time | 10.073 |
| From | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0 |
| To | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_4_s0 |
| Launch Clk | xgmii_tx_clk_i[R] |
| Latch Clk | xgmii_tx_clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | xgmii_tx_clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | xgmii_tx_clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1331 | xgmii_tx_clk_i_ibuf/O |
| 0.297 | 0.297 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0/CLK |
| 0.572 | 0.275 | tC2Q | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0/Q |
| 0.869 | 0.297 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_1_s0/I0 |
| 1.286 | 0.417 | tINS | RR | 2 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_1_s0/F |
| 1.583 | 0.297 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_0_s/I1 |
| 1.992 | 0.409 | tINS | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_0_s/F |
| 2.289 | 0.297 | tNET | RR | 2 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_0_s/I1 |
| 2.721 | 0.432 | tINS | RF | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_0_s/COUT |
| 2.721 | 0.000 | tNET | FF | 2 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_1_s/CIN |
| 2.757 | 0.036 | tINS | FR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_1_s/COUT |
| 2.757 | 0.000 | tNET | RR | 2 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_2_s/CIN |
| 2.932 | 0.175 | tINS | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_2_s/SUM |
| 3.229 | 0.297 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s1/I1 |
| 3.638 | 0.409 | tINS | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s1/F |
| 3.935 | 0.297 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s0/I0 |
| 4.351 | 0.417 | tINS | RR | 5 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s0/F |
| 4.648 | 0.297 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_4_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | xgmii_tx_clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | xgmii_tx_clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1331 | xgmii_tx_clk_i_ibuf/O |
| 10.297 | 0.297 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_4_s0/CLK |
| 10.073 | -0.224 | tSu | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_4_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
| Arrival Data Path Delay: | cell: 2.294, 52.720%; route: 1.782, 40.951%; tC2Q: 0.275, 6.329% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
Path 2
Path Summary:| Slack | 5.424 |
| Data Arrival Time | 4.648 |
| Data Required Time | 10.073 |
| From | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0 |
| To | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_0_s0 |
| Launch Clk | xgmii_tx_clk_i[R] |
| Latch Clk | xgmii_tx_clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | xgmii_tx_clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | xgmii_tx_clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1331 | xgmii_tx_clk_i_ibuf/O |
| 0.297 | 0.297 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0/CLK |
| 0.572 | 0.275 | tC2Q | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0/Q |
| 0.869 | 0.297 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_1_s0/I0 |
| 1.286 | 0.417 | tINS | RR | 2 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_1_s0/F |
| 1.583 | 0.297 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_0_s/I1 |
| 1.992 | 0.409 | tINS | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_0_s/F |
| 2.289 | 0.297 | tNET | RR | 2 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_0_s/I1 |
| 2.721 | 0.432 | tINS | RF | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_0_s/COUT |
| 2.721 | 0.000 | tNET | FF | 2 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_1_s/CIN |
| 2.757 | 0.036 | tINS | FR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_1_s/COUT |
| 2.757 | 0.000 | tNET | RR | 2 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_2_s/CIN |
| 2.932 | 0.175 | tINS | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_2_s/SUM |
| 3.229 | 0.297 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s1/I1 |
| 3.638 | 0.409 | tINS | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s1/F |
| 3.935 | 0.297 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s0/I0 |
| 4.351 | 0.417 | tINS | RR | 5 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s0/F |
| 4.648 | 0.297 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_0_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | xgmii_tx_clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | xgmii_tx_clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1331 | xgmii_tx_clk_i_ibuf/O |
| 10.297 | 0.297 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_0_s0/CLK |
| 10.073 | -0.224 | tSu | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
| Arrival Data Path Delay: | cell: 2.294, 52.720%; route: 1.782, 40.951%; tC2Q: 0.275, 6.329% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
Path 3
Path Summary:| Slack | 5.424 |
| Data Arrival Time | 4.648 |
| Data Required Time | 10.073 |
| From | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0 |
| To | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_1_s0 |
| Launch Clk | xgmii_tx_clk_i[R] |
| Latch Clk | xgmii_tx_clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | xgmii_tx_clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | xgmii_tx_clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1331 | xgmii_tx_clk_i_ibuf/O |
| 0.297 | 0.297 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0/CLK |
| 0.572 | 0.275 | tC2Q | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0/Q |
| 0.869 | 0.297 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_1_s0/I0 |
| 1.286 | 0.417 | tINS | RR | 2 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_1_s0/F |
| 1.583 | 0.297 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_0_s/I1 |
| 1.992 | 0.409 | tINS | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_0_s/F |
| 2.289 | 0.297 | tNET | RR | 2 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_0_s/I1 |
| 2.721 | 0.432 | tINS | RF | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_0_s/COUT |
| 2.721 | 0.000 | tNET | FF | 2 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_1_s/CIN |
| 2.757 | 0.036 | tINS | FR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_1_s/COUT |
| 2.757 | 0.000 | tNET | RR | 2 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_2_s/CIN |
| 2.932 | 0.175 | tINS | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_2_s/SUM |
| 3.229 | 0.297 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s1/I1 |
| 3.638 | 0.409 | tINS | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s1/F |
| 3.935 | 0.297 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s0/I0 |
| 4.351 | 0.417 | tINS | RR | 5 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s0/F |
| 4.648 | 0.297 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_1_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | xgmii_tx_clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | xgmii_tx_clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1331 | xgmii_tx_clk_i_ibuf/O |
| 10.297 | 0.297 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_1_s0/CLK |
| 10.073 | -0.224 | tSu | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_1_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
| Arrival Data Path Delay: | cell: 2.294, 52.720%; route: 1.782, 40.951%; tC2Q: 0.275, 6.329% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
Path 4
Path Summary:| Slack | 5.424 |
| Data Arrival Time | 4.648 |
| Data Required Time | 10.073 |
| From | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0 |
| To | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_2_s0 |
| Launch Clk | xgmii_tx_clk_i[R] |
| Latch Clk | xgmii_tx_clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | xgmii_tx_clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | xgmii_tx_clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1331 | xgmii_tx_clk_i_ibuf/O |
| 0.297 | 0.297 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0/CLK |
| 0.572 | 0.275 | tC2Q | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0/Q |
| 0.869 | 0.297 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_1_s0/I0 |
| 1.286 | 0.417 | tINS | RR | 2 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_1_s0/F |
| 1.583 | 0.297 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_0_s/I1 |
| 1.992 | 0.409 | tINS | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_0_s/F |
| 2.289 | 0.297 | tNET | RR | 2 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_0_s/I1 |
| 2.721 | 0.432 | tINS | RF | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_0_s/COUT |
| 2.721 | 0.000 | tNET | FF | 2 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_1_s/CIN |
| 2.757 | 0.036 | tINS | FR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_1_s/COUT |
| 2.757 | 0.000 | tNET | RR | 2 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_2_s/CIN |
| 2.932 | 0.175 | tINS | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_2_s/SUM |
| 3.229 | 0.297 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s1/I1 |
| 3.638 | 0.409 | tINS | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s1/F |
| 3.935 | 0.297 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s0/I0 |
| 4.351 | 0.417 | tINS | RR | 5 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s0/F |
| 4.648 | 0.297 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_2_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | xgmii_tx_clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | xgmii_tx_clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1331 | xgmii_tx_clk_i_ibuf/O |
| 10.297 | 0.297 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_2_s0/CLK |
| 10.073 | -0.224 | tSu | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_2_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
| Arrival Data Path Delay: | cell: 2.294, 52.720%; route: 1.782, 40.951%; tC2Q: 0.275, 6.329% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
Path 5
Path Summary:| Slack | 5.424 |
| Data Arrival Time | 4.648 |
| Data Required Time | 10.073 |
| From | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0 |
| To | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_3_s0 |
| Launch Clk | xgmii_tx_clk_i[R] |
| Latch Clk | xgmii_tx_clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | xgmii_tx_clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | xgmii_tx_clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1331 | xgmii_tx_clk_i_ibuf/O |
| 0.297 | 0.297 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0/CLK |
| 0.572 | 0.275 | tC2Q | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wraddr_gray/pipe1_1_s0/Q |
| 0.869 | 0.297 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_1_s0/I0 |
| 1.286 | 0.417 | tINS | RR | 2 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_1_s0/F |
| 1.583 | 0.297 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_0_s/I1 |
| 1.992 | 0.409 | tINS | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/u_rd2wr_g2b/rd2wraddr_bin_0_s/F |
| 2.289 | 0.297 | tNET | RR | 2 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_0_s/I1 |
| 2.721 | 0.432 | tINS | RF | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_0_s/COUT |
| 2.721 | 0.000 | tNET | FF | 2 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_1_s/CIN |
| 2.757 | 0.036 | tINS | FR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_1_s/COUT |
| 2.757 | 0.000 | tNET | RR | 2 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_2_s/CIN |
| 2.932 | 0.175 | tINS | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wrusewd_temp_2_s/SUM |
| 3.229 | 0.297 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s1/I1 |
| 3.638 | 0.409 | tINS | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s1/F |
| 3.935 | 0.297 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s0/I0 |
| 4.351 | 0.417 | tINS | RR | 5 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/n58_s0/F |
| 4.648 | 0.297 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_3_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | xgmii_tx_clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | xgmii_tx_clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1331 | xgmii_tx_clk_i_ibuf/O |
| 10.297 | 0.297 | tNET | RR | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_3_s0/CLK |
| 10.073 | -0.224 | tSu | 1 | u_xg_baser/u_xg_baser_data/u_tx_data/u_phase_fifo/u_uafifo_ctrl/wraddr_gray_reg_3_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
| Arrival Data Path Delay: | cell: 2.294, 52.720%; route: 1.782, 40.951%; tC2Q: 0.275, 6.329% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |