Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\IP_Release\10G_Serial_Ethernet_MAC\1.1\ref_design\Gowin_10G_Ethernet_MAC_RefDesign\fpga_project\src\Ten_Giga_Ethernet_MAC\Ten_Giga_Ethernet_MAC.v E:\IP_Release\10G_Serial_Ethernet_MAC\1.1\ref_design\Gowin_10G_Ethernet_MAC_RefDesign\fpga_project\src\serdes\serdes.v E:\IP_Release\10G_Serial_Ethernet_MAC\1.1\ref_design\Gowin_10G_Ethernet_MAC_RefDesign\fpga_project\src\serdes\ten_giga_serial_ethernet\ten_giga_serial_ethernet.v E:\IP_Release\10G_Serial_Ethernet_MAC\1.1\ref_design\Gowin_10G_Ethernet_MAC_RefDesign\fpga_project\src\top.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top_138.v D:\Gowin\Gowin_V1.9.12.02_x64\IDE\data\ipcores\gw_jtag.v E:\IP_Release\10G_Serial_Ethernet_MAC\1.1\ref_design\Gowin_10G_Ethernet_MAC_RefDesign\fpga_project\impl\gwsynthesis\RTL_GAO\gw_gao_top.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12.02 (64-bit) |
| Part Number | GW5AST-LV138FPG676AC2/I1 |
| Device | GW5AST-138 |
| Device Version | B |
| Created Time | Wed Mar 4 10:27:03 2026 |
| Legal Announcement | Copyright (C)2014-2026 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | top |
| Synthesis Process | Running parser: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 328.430MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 328.430MB Optimizing Phase 1: CPU time = 0h 0m 0.687s, Elapsed time = 0h 0m 0.669s, Peak memory usage = 328.430MB Optimizing Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 328.430MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.75s, Elapsed time = 0h 0m 0.751s, Peak memory usage = 328.430MB Inferring Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.04s, Peak memory usage = 328.430MB Inferring Phase 2: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.121s, Peak memory usage = 328.430MB Inferring Phase 3: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.073s, Peak memory usage = 328.430MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.781s, Elapsed time = 0h 0m 0.744s, Peak memory usage = 328.430MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.322s, Peak memory usage = 328.430MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.122s, Peak memory usage = 328.430MB Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 328.430MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.875s, Elapsed time = 0h 0m 0.849s, Peak memory usage = 328.430MB Generate output files: CPU time = 0h 0m 0.781s, Elapsed time = 0h 0m 0.816s, Peak memory usage = 348.328MB |
| Total Time and Memory Usage | CPU time = 0h 0m 10s, Elapsed time = 0h 0m 10s, Peak memory usage = 348.328MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 30 |
| I/O Buf | 27 |
| IBUF | 5 |
| OBUF | 18 |
| TBUF | 4 |
| Register | 8597 |
| DFFSE | 71 |
| DFFRE | 233 |
| DFFPE | 720 |
| DFFCE | 7573 |
| LUT | 6870 |
| LUT2 | 988 |
| LUT3 | 2433 |
| LUT4 | 3449 |
| MUX | 1 |
| MUX16 | 1 |
| ALU | 49 |
| ALU | 49 |
| INV | 54 |
| INV | 54 |
| BSRAM | 7 |
| SDPB | 3 |
| SDPX9B | 4 |
| Black Box | 2 |
| GW_JTAG | 1 |
| GTR12_QUAD | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 6981(6932 LUT, 49 ALU) / 138240 | 6% |
| Register | 8597 / 139140 | 7% |
| --Register as Latch | 0 / 139140 | 0% |
| --Register as FF | 8597 / 139140 | 7% |
| BSRAM | 7 / 340 | 3% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | tck_pad_i | Base | 50.000 | 20.000 | 0.000 | 25.000 | gw_gao_inst_0/tck_ibuf/I | ||
| 2 | gw_gao_inst_0/u_la0_top/n15_6 | Base | 10.000 | 100.000 | 0.000 | 5.000 | gw_gao_inst_0/u_la0_top/n15_s2/F |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | tck_pad_i | 20.000(MHz) | 117.635(MHz) | 6 | TOP |
| 2 | gw_gao_inst_0/u_la0_top/n15_6 | 100.000(MHz) | 1617.337(MHz) | 1 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 9.382 |
| Data Arrival Time | 0.869 |
| Data Required Time | 10.251 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_syn_s0 |
| To | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| Launch Clk | gw_gao_inst_0/u_la0_top/n15_6[R] |
| Latch Clk | gw_gao_inst_0/u_la0_top/n15_6[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | gw_gao_inst_0/u_la0_top/n15_6 | |||
| 0.000 | 0.000 | tCL | RR | 2 | gw_gao_inst_0/u_la0_top/n15_s2/F |
| 0.297 | 0.297 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/rst_ao_syn_s0/CLK |
| 0.572 | 0.275 | tC2Q | RR | 1 | gw_gao_inst_0/u_la0_top/rst_ao_syn_s0/Q |
| 0.869 | 0.297 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/rst_ao_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 10.000 | active clock edge time | |||
| 10.000 | 0.000 | gw_gao_inst_0/u_la0_top/n15_6 | |||
| 10.000 | 0.000 | tCL | RR | 2 | gw_gao_inst_0/u_la0_top/n15_s2/F |
| 10.297 | 0.297 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 10.251 | -0.046 | tSu | 1 | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.297, 51.887%; tC2Q: 0.275, 48.113% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.297, 100.000% |
Path 2
Path Summary:| Slack | 20.750 |
| Data Arrival Time | 5.152 |
| Data Required Time | 25.902 |
| From | gw_gao_inst_0/u_icon_top/module_id_reg_1_s0 |
| To | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1 |
| Launch Clk | tck_pad_i[R] |
| Latch Clk | tck_pad_i[F] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | tck_pad_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | gw_gao_inst_0/tck_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1 | gw_gao_inst_0/tck_ibuf/O |
| 0.297 | 0.297 | tNET | RR | 1 | gw_gao_inst_0/u_gw_jtag_s/tck_pad_i |
| 0.825 | 0.528 | tINS | RR | 353 | gw_gao_inst_0/u_gw_jtag_s/tck_o |
| 1.122 | 0.297 | tNET | RR | 1 | gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/CLK |
| 1.398 | 0.275 | tC2Q | RR | 2 | gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/Q |
| 1.695 | 0.297 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/n20_s1/I0 |
| 2.111 | 0.417 | tINS | RR | 9 | gw_gao_inst_0/u_la0_top/n20_s1/F |
| 2.408 | 0.297 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/regsel_ld_en_s8/I0 |
| 2.825 | 0.417 | tINS | RR | 4 | gw_gao_inst_0/u_la0_top/regsel_ld_en_s8/F |
| 3.122 | 0.297 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/trig_level_max_reg_wr_s3/I1 |
| 3.531 | 0.409 | tINS | RR | 3 | gw_gao_inst_0/u_la0_top/trig_level_max_reg_wr_s3/F |
| 3.828 | 0.297 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/internal_reg_start_s4/I2 |
| 4.193 | 0.365 | tINS | RR | 1 | gw_gao_inst_0/u_la0_top/internal_reg_start_s4/F |
| 4.490 | 0.297 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/internal_reg_start_s3/I2 |
| 4.855 | 0.365 | tINS | RR | 2 | gw_gao_inst_0/u_la0_top/internal_reg_start_s3/F |
| 5.152 | 0.297 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 25.000 | 25.000 | active clock edge time | |||
| 25.000 | 0.000 | tck_pad_i | |||
| 25.000 | 0.000 | tCL | FF | 1 | gw_gao_inst_0/tck_ibuf/I |
| 25.000 | 0.000 | tINS | FF | 1 | gw_gao_inst_0/tck_ibuf/O |
| 25.277 | 0.277 | tNET | FF | 1 | gw_gao_inst_0/u_gw_jtag_s/tck_pad_i |
| 25.809 | 0.532 | tINS | FF | 353 | gw_gao_inst_0/u_gw_jtag_s/tck_o |
| 26.087 | 0.277 | tNET | FF | 1 | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1/CLK |
| 25.902 | -0.184 | tSu | 1 | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1 |
| Clock Skew: | -0.036 |
| Setup Relationship: | 25.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.528, 47.071%; route: 0.594, 52.929% |
| Arrival Data Path Delay: | cell: 1.973, 48.951%; route: 1.782, 44.216%; tC2Q: 0.275, 6.833% |
| Required Clock Path Delay: | cell: 0.528, 47.071%; route: 0.594, 52.929% |
Path 3
Path Summary:| Slack | 20.750 |
| Data Arrival Time | 5.152 |
| Data Required Time | 25.902 |
| From | gw_gao_inst_0/u_icon_top/module_id_reg_1_s0 |
| To | gw_gao_inst_0/u_la0_top/internal_reg_start_s1 |
| Launch Clk | tck_pad_i[R] |
| Latch Clk | tck_pad_i[F] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | tck_pad_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | gw_gao_inst_0/tck_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1 | gw_gao_inst_0/tck_ibuf/O |
| 0.297 | 0.297 | tNET | RR | 1 | gw_gao_inst_0/u_gw_jtag_s/tck_pad_i |
| 0.825 | 0.528 | tINS | RR | 353 | gw_gao_inst_0/u_gw_jtag_s/tck_o |
| 1.122 | 0.297 | tNET | RR | 1 | gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/CLK |
| 1.398 | 0.275 | tC2Q | RR | 2 | gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/Q |
| 1.695 | 0.297 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/n20_s1/I0 |
| 2.111 | 0.417 | tINS | RR | 9 | gw_gao_inst_0/u_la0_top/n20_s1/F |
| 2.408 | 0.297 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/regsel_ld_en_s8/I0 |
| 2.825 | 0.417 | tINS | RR | 4 | gw_gao_inst_0/u_la0_top/regsel_ld_en_s8/F |
| 3.122 | 0.297 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/trig_level_max_reg_wr_s3/I1 |
| 3.531 | 0.409 | tINS | RR | 3 | gw_gao_inst_0/u_la0_top/trig_level_max_reg_wr_s3/F |
| 3.828 | 0.297 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/internal_reg_start_s4/I2 |
| 4.193 | 0.365 | tINS | RR | 1 | gw_gao_inst_0/u_la0_top/internal_reg_start_s4/F |
| 4.490 | 0.297 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/internal_reg_start_s3/I2 |
| 4.855 | 0.365 | tINS | RR | 2 | gw_gao_inst_0/u_la0_top/internal_reg_start_s3/F |
| 5.152 | 0.297 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/internal_reg_start_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 25.000 | 25.000 | active clock edge time | |||
| 25.000 | 0.000 | tck_pad_i | |||
| 25.000 | 0.000 | tCL | FF | 1 | gw_gao_inst_0/tck_ibuf/I |
| 25.000 | 0.000 | tINS | FF | 1 | gw_gao_inst_0/tck_ibuf/O |
| 25.277 | 0.277 | tNET | FF | 1 | gw_gao_inst_0/u_gw_jtag_s/tck_pad_i |
| 25.809 | 0.532 | tINS | FF | 353 | gw_gao_inst_0/u_gw_jtag_s/tck_o |
| 26.087 | 0.277 | tNET | FF | 1 | gw_gao_inst_0/u_la0_top/internal_reg_start_s1/CLK |
| 25.902 | -0.184 | tSu | 1 | gw_gao_inst_0/u_la0_top/internal_reg_start_s1 |
| Clock Skew: | -0.036 |
| Setup Relationship: | 25.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.528, 47.071%; route: 0.594, 52.929% |
| Arrival Data Path Delay: | cell: 1.973, 48.951%; route: 1.782, 44.216%; tC2Q: 0.275, 6.833% |
| Required Clock Path Delay: | cell: 0.528, 47.071%; route: 0.594, 52.929% |
Path 4
Path Summary:| Slack | 21.534 |
| Data Arrival Time | 29.543 |
| Data Required Time | 51.076 |
| From | gw_gao_inst_0/u_la0_top/internal_reg_start_s1 |
| To | gw_gao_inst_0/u_la0_top/data_out_shift_reg_0_s1 |
| Launch Clk | tck_pad_i[F] |
| Latch Clk | tck_pad_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 25.000 | 25.000 | active clock edge time | |||
| 25.000 | 0.000 | tck_pad_i | |||
| 25.000 | 0.000 | tCL | FF | 1 | gw_gao_inst_0/tck_ibuf/I |
| 25.000 | 0.000 | tINS | FF | 1 | gw_gao_inst_0/tck_ibuf/O |
| 25.277 | 0.277 | tNET | FF | 1 | gw_gao_inst_0/u_gw_jtag_s/tck_pad_i |
| 25.809 | 0.532 | tINS | FF | 353 | gw_gao_inst_0/u_gw_jtag_s/tck_o |
| 26.087 | 0.277 | tNET | FF | 1 | gw_gao_inst_0/u_la0_top/internal_reg_start_s1/CLK |
| 26.399 | 0.312 | tC2Q | FR | 2 | gw_gao_inst_0/u_la0_top/internal_reg_start_s1/Q |
| 26.696 | 0.297 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/n1048_s7/I0 |
| 27.113 | 0.417 | tINS | RR | 1 | gw_gao_inst_0/u_la0_top/n1048_s7/F |
| 27.410 | 0.297 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/n1048_s4/I0 |
| 27.826 | 0.417 | tINS | RR | 1 | gw_gao_inst_0/u_la0_top/n1048_s4/F |
| 28.123 | 0.297 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/n1048_s1/I1 |
| 28.532 | 0.409 | tINS | RR | 1 | gw_gao_inst_0/u_la0_top/n1048_s1/F |
| 28.829 | 0.297 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/n1048_s0/I0 |
| 29.246 | 0.417 | tINS | RR | 1 | gw_gao_inst_0/u_la0_top/n1048_s0/F |
| 29.543 | 0.297 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/data_out_shift_reg_0_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 50.000 | 50.000 | active clock edge time | |||
| 50.000 | 0.000 | tck_pad_i | |||
| 50.000 | 0.000 | tCL | RR | 1 | gw_gao_inst_0/tck_ibuf/I |
| 50.000 | 0.000 | tINS | RR | 1 | gw_gao_inst_0/tck_ibuf/O |
| 50.297 | 0.297 | tNET | RR | 1 | gw_gao_inst_0/u_gw_jtag_s/tck_pad_i |
| 50.825 | 0.528 | tINS | RR | 353 | gw_gao_inst_0/u_gw_jtag_s/tck_o |
| 51.122 | 0.297 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/data_out_shift_reg_0_s1/CLK |
| 51.076 | -0.046 | tSu | 1 | gw_gao_inst_0/u_la0_top/data_out_shift_reg_0_s1 |
| Clock Skew: | 0.036 |
| Setup Relationship: | 25.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.532, 48.975%; route: 0.554, 51.025% |
| Arrival Data Path Delay: | cell: 1.659, 47.995%; route: 1.485, 42.969%; tC2Q: 0.312, 9.036% |
| Required Clock Path Delay: | cell: 0.532, 48.975%; route: 0.554, 51.025% |
Path 5
Path Summary:| Slack | 21.748 |
| Data Arrival Time | 4.333 |
| Data Required Time | 26.080 |
| From | gw_gao_inst_0/u_icon_top/module_id_reg_1_s0 |
| To | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1 |
| Launch Clk | tck_pad_i[R] |
| Latch Clk | tck_pad_i[F] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | |||
| 0.000 | 0.000 | tck_pad_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | gw_gao_inst_0/tck_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1 | gw_gao_inst_0/tck_ibuf/O |
| 0.297 | 0.297 | tNET | RR | 1 | gw_gao_inst_0/u_gw_jtag_s/tck_pad_i |
| 0.825 | 0.528 | tINS | RR | 353 | gw_gao_inst_0/u_gw_jtag_s/tck_o |
| 1.122 | 0.297 | tNET | RR | 1 | gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/CLK |
| 1.398 | 0.275 | tC2Q | RR | 2 | gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/Q |
| 1.695 | 0.297 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/n20_s1/I0 |
| 2.111 | 0.417 | tINS | RR | 9 | gw_gao_inst_0/u_la0_top/n20_s1/F |
| 2.408 | 0.297 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/regsel_ld_en_s8/I0 |
| 2.825 | 0.417 | tINS | RR | 4 | gw_gao_inst_0/u_la0_top/regsel_ld_en_s8/F |
| 3.122 | 0.297 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/trig_level_max_reg_wr_s3/I1 |
| 3.531 | 0.409 | tINS | RR | 3 | gw_gao_inst_0/u_la0_top/trig_level_max_reg_wr_s3/F |
| 3.828 | 0.297 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/n580_s2/I3 |
| 4.036 | 0.208 | tINS | RR | 1 | gw_gao_inst_0/u_la0_top/n580_s2/F |
| 4.333 | 0.297 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 25.000 | 25.000 | active clock edge time | |||
| 25.000 | 0.000 | tck_pad_i | |||
| 25.000 | 0.000 | tCL | FF | 1 | gw_gao_inst_0/tck_ibuf/I |
| 25.000 | 0.000 | tINS | FF | 1 | gw_gao_inst_0/tck_ibuf/O |
| 25.277 | 0.277 | tNET | FF | 1 | gw_gao_inst_0/u_gw_jtag_s/tck_pad_i |
| 25.809 | 0.532 | tINS | FF | 353 | gw_gao_inst_0/u_gw_jtag_s/tck_o |
| 26.087 | 0.277 | tNET | FF | 1 | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1/CLK |
| 26.080 | -0.006 | tSu | 1 | gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s1 |
| Clock Skew: | -0.036 |
| Setup Relationship: | 25.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.528, 47.071%; route: 0.594, 52.929% |
| Arrival Data Path Delay: | cell: 1.450, 45.164%; route: 1.485, 46.257%; tC2Q: 0.275, 8.579% |
| Required Clock Path Delay: | cell: 0.528, 47.071%; route: 0.594, 52.929% |