Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\EDP_RX_DESTEER\data\edp_rx_desteer.v
D:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\EDP_RX_DESTEER\data\rx_desteer_wrapper.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.02
Part Number GW5AST-LV138FPG676AES
Device GW5AST-138
Device Version B
Created Time Fri Mar 1 10:30:08 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module EDP_RX_Desteer_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.349s, Peak memory usage = 80.551MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 80.551MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.037s, Peak memory usage = 80.551MB
    Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.029s, Peak memory usage = 80.551MB
    Optimizing Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.067s, Peak memory usage = 80.551MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 80.551MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 80.551MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 80.551MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 80.551MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.074s, Peak memory usage = 80.551MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 80.551MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 80.551MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 108.078MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.123s, Peak memory usage = 108.078MB
Generate output files:
    CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.153s, Peak memory usage = 108.078MB
Total Time and Memory Usage CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 108.078MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 336
I/O Buf 327
    IBUF 228
    OBUF 99
Register 554
    DFFPE 13
    DFFCE 541
LUT 1008
    LUT2 227
    LUT3 294
    LUT4 487
ALU 266
    ALU 266
INV 19
    INV 19
BSRAM 24
    SDPB 24

Resource Utilization Summary

Resource Usage Utilization
Logic 1293(1027 LUT, 266 ALU) / 138240 <1%
Register 554 / 139140 <1%
  --Register as Latch 0 / 139140 0%
  --Register as FF 554 / 139140 <1%
BSRAM 24 / 340 8%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
I_strm_clk Base 10.000 100.0 0.000 5.000 I_strm_clk_ibuf/I
I_ls_clk Base 10.000 100.0 0.000 5.000 I_ls_clk_ibuf/I
rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst0/n41_6 Base 10.000 100.0 0.000 5.000 rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst0/n41_s2/O
rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst0/n46_6 Base 10.000 100.0 0.000 5.000 rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst0/n46_s2/O

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_strm_clk 100.000(MHz) 128.185(MHz) 10 TOP
2 I_ls_clk 100.000(MHz) 149.226(MHz) 7 TOP
3 rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst0/n41_6 100.000(MHz) 1164.484(MHz) 1 TOP
4 rx_desteer_wrapper_inst/rx_fifo_lb_wrapper_inst/rx_fifo_lb_inst0/n46_6 100.000(MHz) 1164.484(MHz) 1 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 2.199
Data Arrival Time 8.833
Data Required Time 11.031
From rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_0_s1
To rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/Pout_de_dn_s0
Launch Clk I_strm_clk[R]
Latch Clk I_strm_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_strm_clk
0.000 0.000 tCL RR 1 I_strm_clk_ibuf/I
0.683 0.683 tINS RR 367 I_strm_clk_ibuf/O
1.095 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_0_s1/CLK
1.477 0.382 tC2Q RR 11 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_0_s1/Q
1.890 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/n300_s47/I0
2.469 0.579 tINS RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/n300_s47/F
2.881 0.413 tNET RR 2 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/n300_s33/I0
3.476 0.595 tINS RF 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/n300_s33/COUT
3.476 0.000 tNET FF 2 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/n300_s34/CIN
3.526 0.050 tINS FR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/n300_s34/COUT
3.526 0.000 tNET RR 2 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/n300_s35/CIN
3.576 0.050 tINS RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/n300_s35/COUT
3.576 0.000 tNET RR 2 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/n300_s36/CIN
3.626 0.050 tINS RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/n300_s36/COUT
3.626 0.000 tNET RR 2 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/n300_s37/CIN
3.676 0.050 tINS RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/n300_s37/COUT
3.676 0.000 tNET RR 2 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/n300_s38/CIN
3.726 0.050 tINS RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/n300_s38/COUT
3.726 0.000 tNET RR 2 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/n300_s39/CIN
3.776 0.050 tINS RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/n300_s39/COUT
3.776 0.000 tNET RR 2 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/n300_s40/CIN
3.826 0.050 tINS RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/n300_s40/COUT
3.826 0.000 tNET RR 2 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/n300_s41/CIN
3.876 0.050 tINS RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/n300_s41/COUT
3.876 0.000 tNET RR 2 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/n300_s42/CIN
3.926 0.050 tINS RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/n300_s42/COUT
3.926 0.000 tNET RR 2 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/n300_s43/CIN
3.976 0.050 tINS RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/n300_s43/COUT
3.976 0.000 tNET RR 2 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/n300_s44/CIN
4.026 0.050 tINS RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/n300_s44/COUT
4.026 0.000 tNET RR 2 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/n300_s45/CIN
4.076 0.050 tINS RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/n300_s45/COUT
4.076 0.000 tNET RR 2 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/n300_s46/CIN
4.126 0.050 tINS RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/n300_s46/COUT
4.539 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/Rden_w_s36/I0
5.117 0.579 tINS RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/Rden_w_s36/F
5.530 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/Rden_w_s14/I3
5.819 0.289 tINS RR 2 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/Rden_w_s14/F
6.231 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/Pout_de_w_s16/I2
6.739 0.507 tINS RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/Pout_de_w_s16/F
7.151 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/Pout_de_w_s4/I1
7.719 0.567 tINS RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/Pout_de_w_s4/F
8.131 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/Pout_de_w_s0/I3
8.420 0.289 tINS RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/Pout_de_w_s0/F
8.833 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/Pout_de_dn_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_strm_clk
10.000 0.000 tCL RR 1 I_strm_clk_ibuf/I
10.682 0.683 tINS RR 367 I_strm_clk_ibuf/O
11.095 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/Pout_de_dn_s0/CLK
11.031 -0.064 tSu 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/Pout_de_dn_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 10
Arrival Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%
Arrival Data Path Delay: cell: 4.055, 52.408%; route: 3.300, 42.649%; tC2Q: 0.382, 4.943%
Required Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%

Path 2

Path Summary:
Slack 2.285
Data Arrival Time 8.746
Data Required Time 11.031
From rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_0_s1
To rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/Rden_dn_s0
Launch Clk I_strm_clk[R]
Latch Clk I_strm_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_strm_clk
0.000 0.000 tCL RR 1 I_strm_clk_ibuf/I
0.683 0.683 tINS RR 367 I_strm_clk_ibuf/O
1.095 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_0_s1/CLK
1.477 0.382 tC2Q RR 11 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_0_s1/Q
1.890 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/Rden_w_s86/I0
2.469 0.579 tINS RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/Rden_w_s86/F
2.881 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/Rden_w_s64/I2
3.389 0.507 tINS RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/Rden_w_s64/F
3.801 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/Rden_w_s41/I0
4.380 0.579 tINS RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/Rden_w_s41/F
4.793 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/Rden_w_s17/I0
5.371 0.579 tINS RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/Rden_w_s17/F
5.784 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/Rden_w_s6/I0
6.363 0.579 tINS RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/Rden_w_s6/F
6.775 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/Rden_w_s2/I0
7.354 0.579 tINS RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/Rden_w_s2/F
7.766 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/Rden_w_s0/I1
8.334 0.567 tINS RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/Rden_w_s0/F
8.746 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/Rden_dn_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_strm_clk
10.000 0.000 tCL RR 1 I_strm_clk_ibuf/I
10.682 0.683 tINS RR 367 I_strm_clk_ibuf/O
11.095 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/Rden_dn_s0/CLK
11.031 -0.064 tSu 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/Rden_dn_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%
Arrival Data Path Delay: cell: 3.969, 51.871%; route: 3.300, 43.130%; tC2Q: 0.382, 4.999%
Required Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%

Path 3

Path Summary:
Slack 2.296
Data Arrival Time 8.735
Data Required Time 11.031
From rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/H_cnt_0_s0
To rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_1_s1
Launch Clk I_strm_clk[R]
Latch Clk I_strm_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_strm_clk
0.000 0.000 tCL RR 1 I_strm_clk_ibuf/I
0.683 0.683 tINS RR 367 I_strm_clk_ibuf/O
1.095 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/H_cnt_0_s0/CLK
1.477 0.382 tC2Q RR 10 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/H_cnt_0_s0/Q
1.890 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_15_s46/I0
2.469 0.579 tINS RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_15_s46/F
2.881 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_15_s32/I1
3.449 0.567 tINS RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_15_s32/F
3.861 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_15_s15/I2
4.369 0.507 tINS RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_15_s15/F
4.781 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_15_s7/I1
5.349 0.567 tINS RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_15_s7/F
5.761 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_15_s4/I0
6.340 0.579 tINS RR 2 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_15_s4/F
6.753 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/frame_clr_s4/I0
7.331 0.579 tINS RR 17 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/frame_clr_s4/F
7.744 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/n108_s2/I0
8.323 0.579 tINS RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/n108_s2/F
8.735 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_1_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_strm_clk
10.000 0.000 tCL RR 1 I_strm_clk_ibuf/I
10.682 0.683 tINS RR 367 I_strm_clk_ibuf/O
11.095 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_1_s1/CLK
11.031 -0.064 tSu 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%
Arrival Data Path Delay: cell: 3.958, 51.799%; route: 3.300, 43.194%; tC2Q: 0.382, 5.007%
Required Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%

Path 4

Path Summary:
Slack 2.296
Data Arrival Time 8.735
Data Required Time 11.031
From rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/H_cnt_0_s0
To rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_2_s1
Launch Clk I_strm_clk[R]
Latch Clk I_strm_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_strm_clk
0.000 0.000 tCL RR 1 I_strm_clk_ibuf/I
0.683 0.683 tINS RR 367 I_strm_clk_ibuf/O
1.095 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/H_cnt_0_s0/CLK
1.477 0.382 tC2Q RR 10 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/H_cnt_0_s0/Q
1.890 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_15_s46/I0
2.469 0.579 tINS RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_15_s46/F
2.881 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_15_s32/I1
3.449 0.567 tINS RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_15_s32/F
3.861 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_15_s15/I2
4.369 0.507 tINS RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_15_s15/F
4.781 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_15_s7/I1
5.349 0.567 tINS RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_15_s7/F
5.761 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_15_s4/I0
6.340 0.579 tINS RR 2 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_15_s4/F
6.753 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/frame_clr_s4/I0
7.331 0.579 tINS RR 17 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/frame_clr_s4/F
7.744 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/n107_s4/I0
8.323 0.579 tINS RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/n107_s4/F
8.735 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_2_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_strm_clk
10.000 0.000 tCL RR 1 I_strm_clk_ibuf/I
10.682 0.683 tINS RR 367 I_strm_clk_ibuf/O
11.095 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_2_s1/CLK
11.031 -0.064 tSu 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_2_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%
Arrival Data Path Delay: cell: 3.958, 51.799%; route: 3.300, 43.194%; tC2Q: 0.382, 5.007%
Required Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%

Path 5

Path Summary:
Slack 2.296
Data Arrival Time 8.735
Data Required Time 11.031
From rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/H_cnt_0_s0
To rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_4_s1
Launch Clk I_strm_clk[R]
Latch Clk I_strm_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_strm_clk
0.000 0.000 tCL RR 1 I_strm_clk_ibuf/I
0.683 0.683 tINS RR 367 I_strm_clk_ibuf/O
1.095 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/H_cnt_0_s0/CLK
1.477 0.382 tC2Q RR 10 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/H_cnt_0_s0/Q
1.890 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_15_s46/I0
2.469 0.579 tINS RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_15_s46/F
2.881 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_15_s32/I1
3.449 0.567 tINS RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_15_s32/F
3.861 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_15_s15/I2
4.369 0.507 tINS RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_15_s15/F
4.781 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_15_s7/I1
5.349 0.567 tINS RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_15_s7/F
5.761 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_15_s4/I0
6.340 0.579 tINS RR 2 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_15_s4/F
6.753 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/frame_clr_s4/I0
7.331 0.579 tINS RR 17 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/frame_clr_s4/F
7.744 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/n105_s2/I0
8.323 0.579 tINS RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/n105_s2/F
8.735 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_4_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_strm_clk
10.000 0.000 tCL RR 1 I_strm_clk_ibuf/I
10.682 0.683 tINS RR 367 I_strm_clk_ibuf/O
11.095 0.413 tNET RR 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_4_s1/CLK
11.031 -0.064 tSu 1 rx_desteer_wrapper_inst/rx_desteering_inst/rx_syn_gen_inst/V_cnt_4_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%
Arrival Data Path Delay: cell: 3.958, 51.799%; route: 3.300, 43.194%; tC2Q: 0.382, 5.007%
Required Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%