Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\EDP_DECODE\data\edp_decoder_top.v D:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\EDP_DECODE\data\edp_decoder_wrapper.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.9.02 |
| Part Number | GW5AST-LV138FPG676AES |
| Device | GW5AST-138 |
| Device Version | B |
| Created Time | Fri Mar 1 10:42:02 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | EDP_Decoder_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.437s, Elapsed time = 0h 0m 0.483s, Peak memory usage = 88.062MB Running netlist conversion: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.04s, Peak memory usage = 88.062MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.115s, Peak memory usage = 88.062MB Optimizing Phase 1: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.109s, Peak memory usage = 88.062MB Optimizing Phase 2: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.137s, Peak memory usage = 88.062MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.055s, Peak memory usage = 88.062MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 88.062MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 88.062MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 88.062MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.115s, Peak memory usage = 88.062MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.039s, Peak memory usage = 88.062MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 88.062MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 113.512MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.165s, Peak memory usage = 113.512MB Generate output files: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.214s, Peak memory usage = 113.512MB |
| Total Time and Memory Usage | CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 113.512MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 394 |
| I/O Buf | 394 |
| IBUF | 76 |
| OBUF | 318 |
| Register | 1717 |
| DFFSE | 92 |
| DFFRE | 28 |
| DFFPE | 46 |
| DFFCE | 1551 |
| LUT | 1285 |
| LUT2 | 147 |
| LUT3 | 306 |
| LUT4 | 832 |
| INV | 4 |
| INV | 4 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 1289(1289 LUT, 0 ALU) / 138240 | <1% |
| Register | 1717 / 139140 | 2% |
| --Register as Latch | 0 / 139140 | 0% |
| --Register as FF | 1717 / 139140 | 2% |
| BSRAM | 0 / 340 | 0% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| I_ls_clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | I_ls_clk_ibuf/I |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | I_ls_clk | 100.000(MHz) | 194.837(MHz) | 5 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 4.867 |
| Data Arrival Time | 5.855 |
| Data Required Time | 10.722 |
| From | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/I_data_d4_10_s1 |
| To | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/sr16_2_0_s0 |
| Launch Clk | I_ls_clk[R] |
| Latch Clk | I_ls_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_ls_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_ls_clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 1717 | I_ls_clk_ibuf/O |
| 1.095 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/I_data_d4_10_s1/CLK |
| 1.477 | 0.382 | tC2Q | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/I_data_d4_10_s1/Q |
| 1.890 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/n828_s14/I0 |
| 2.469 | 0.579 | tINS | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/n828_s14/F |
| 2.881 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/n828_s7/I0 |
| 3.460 | 0.579 | tINS | RR | 2 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/n828_s7/F |
| 3.872 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/n844_s2/I0 |
| 4.451 | 0.579 | tINS | RR | 2 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/n844_s2/F |
| 4.864 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/n844_s1/I0 |
| 5.443 | 0.579 | tINS | RR | 15 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/n844_s1/F |
| 5.855 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/sr16_2_0_s0/SET |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_ls_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_ls_clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 1717 | I_ls_clk_ibuf/O |
| 11.095 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/sr16_2_0_s0/CLK |
| 10.722 | -0.373 | tSu | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/sr16_2_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.683, 62.329%; route: 0.413, 37.671% |
| Arrival Data Path Delay: | cell: 2.315, 48.634%; route: 2.062, 43.330%; tC2Q: 0.382, 8.036% |
| Required Clock Path Delay: | cell: 0.683, 62.329%; route: 0.413, 37.671% |
Path 2
Path Summary:| Slack | 4.867 |
| Data Arrival Time | 5.855 |
| Data Required Time | 10.722 |
| From | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/I_data_d4_10_s1 |
| To | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/sr16_2_1_s0 |
| Launch Clk | I_ls_clk[R] |
| Latch Clk | I_ls_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_ls_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_ls_clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 1717 | I_ls_clk_ibuf/O |
| 1.095 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/I_data_d4_10_s1/CLK |
| 1.477 | 0.382 | tC2Q | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/I_data_d4_10_s1/Q |
| 1.890 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/n828_s14/I0 |
| 2.469 | 0.579 | tINS | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/n828_s14/F |
| 2.881 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/n828_s7/I0 |
| 3.460 | 0.579 | tINS | RR | 2 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/n828_s7/F |
| 3.872 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/n844_s2/I0 |
| 4.451 | 0.579 | tINS | RR | 2 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/n844_s2/F |
| 4.864 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/n844_s1/I0 |
| 5.443 | 0.579 | tINS | RR | 15 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/n844_s1/F |
| 5.855 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/sr16_2_1_s0/SET |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_ls_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_ls_clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 1717 | I_ls_clk_ibuf/O |
| 11.095 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/sr16_2_1_s0/CLK |
| 10.722 | -0.373 | tSu | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/sr16_2_1_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.683, 62.329%; route: 0.413, 37.671% |
| Arrival Data Path Delay: | cell: 2.315, 48.634%; route: 2.062, 43.330%; tC2Q: 0.382, 8.036% |
| Required Clock Path Delay: | cell: 0.683, 62.329%; route: 0.413, 37.671% |
Path 3
Path Summary:| Slack | 4.867 |
| Data Arrival Time | 5.855 |
| Data Required Time | 10.722 |
| From | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/I_data_d4_10_s1 |
| To | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/sr16_2_2_s0 |
| Launch Clk | I_ls_clk[R] |
| Latch Clk | I_ls_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_ls_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_ls_clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 1717 | I_ls_clk_ibuf/O |
| 1.095 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/I_data_d4_10_s1/CLK |
| 1.477 | 0.382 | tC2Q | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/I_data_d4_10_s1/Q |
| 1.890 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/n828_s14/I0 |
| 2.469 | 0.579 | tINS | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/n828_s14/F |
| 2.881 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/n828_s7/I0 |
| 3.460 | 0.579 | tINS | RR | 2 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/n828_s7/F |
| 3.872 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/n844_s2/I0 |
| 4.451 | 0.579 | tINS | RR | 2 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/n844_s2/F |
| 4.864 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/n844_s1/I0 |
| 5.443 | 0.579 | tINS | RR | 15 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/n844_s1/F |
| 5.855 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/sr16_2_2_s0/SET |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_ls_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_ls_clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 1717 | I_ls_clk_ibuf/O |
| 11.095 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/sr16_2_2_s0/CLK |
| 10.722 | -0.373 | tSu | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/sr16_2_2_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.683, 62.329%; route: 0.413, 37.671% |
| Arrival Data Path Delay: | cell: 2.315, 48.634%; route: 2.062, 43.330%; tC2Q: 0.382, 8.036% |
| Required Clock Path Delay: | cell: 0.683, 62.329%; route: 0.413, 37.671% |
Path 4
Path Summary:| Slack | 4.867 |
| Data Arrival Time | 5.855 |
| Data Required Time | 10.722 |
| From | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/I_data_d4_10_s1 |
| To | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/sr16_2_3_s0 |
| Launch Clk | I_ls_clk[R] |
| Latch Clk | I_ls_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_ls_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_ls_clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 1717 | I_ls_clk_ibuf/O |
| 1.095 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/I_data_d4_10_s1/CLK |
| 1.477 | 0.382 | tC2Q | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/I_data_d4_10_s1/Q |
| 1.890 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/n828_s14/I0 |
| 2.469 | 0.579 | tINS | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/n828_s14/F |
| 2.881 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/n828_s7/I0 |
| 3.460 | 0.579 | tINS | RR | 2 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/n828_s7/F |
| 3.872 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/n844_s2/I0 |
| 4.451 | 0.579 | tINS | RR | 2 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/n844_s2/F |
| 4.864 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/n844_s1/I0 |
| 5.443 | 0.579 | tINS | RR | 15 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/n844_s1/F |
| 5.855 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/sr16_2_3_s0/RESET |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_ls_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_ls_clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 1717 | I_ls_clk_ibuf/O |
| 11.095 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/sr16_2_3_s0/CLK |
| 10.722 | -0.373 | tSu | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/sr16_2_3_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.683, 62.329%; route: 0.413, 37.671% |
| Arrival Data Path Delay: | cell: 2.315, 48.634%; route: 2.062, 43.330%; tC2Q: 0.382, 8.036% |
| Required Clock Path Delay: | cell: 0.683, 62.329%; route: 0.413, 37.671% |
Path 5
Path Summary:| Slack | 4.867 |
| Data Arrival Time | 5.855 |
| Data Required Time | 10.722 |
| From | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/I_data_d4_10_s1 |
| To | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/sr16_2_4_s0 |
| Launch Clk | I_ls_clk[R] |
| Latch Clk | I_ls_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_ls_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_ls_clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 1717 | I_ls_clk_ibuf/O |
| 1.095 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/I_data_d4_10_s1/CLK |
| 1.477 | 0.382 | tC2Q | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/I_data_d4_10_s1/Q |
| 1.890 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/n828_s14/I0 |
| 2.469 | 0.579 | tINS | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/n828_s14/F |
| 2.881 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/n828_s7/I0 |
| 3.460 | 0.579 | tINS | RR | 2 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/n828_s7/F |
| 3.872 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/n844_s2/I0 |
| 4.451 | 0.579 | tINS | RR | 2 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/n844_s2/F |
| 4.864 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/n844_s1/I0 |
| 5.443 | 0.579 | tINS | RR | 15 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/n844_s1/F |
| 5.855 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/sr16_2_4_s0/SET |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_ls_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_ls_clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 1717 | I_ls_clk_ibuf/O |
| 11.095 | 0.413 | tNET | RR | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/sr16_2_4_s0/CLK |
| 10.722 | -0.373 | tSu | 1 | edp_decoder_wrapper_inst/rx_descramble_wrapper_inst/rx_descramble_inst3/rx_descramble20_inst/sr16_2_4_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.683, 62.329%; route: 0.413, 37.671% |
| Arrival Data Path Delay: | cell: 2.315, 48.634%; route: 2.062, 43.330%; tC2Q: 0.382, 8.036% |
| Required Clock Path Delay: | cell: 0.683, 62.329%; route: 0.413, 37.671% |