Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\UARTTOBUS\data\uart_bus_core_encryption.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\UARTTOBUS\data\uart_to_bus_top.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12.01 (64-bit) |
| Part Number | GW5AST-LV138FPG676AES |
| Device | GW5AST-138 |
| Device Version | B |
| Created Time | Tue Dec 30 10:56:39 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | Uart_to_Bus_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.358s, Peak memory usage = 83.445MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 83.445MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.074s, Peak memory usage = 83.445MB Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 83.445MB Optimizing Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.075s, Peak memory usage = 83.445MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.048s, Peak memory usage = 83.445MB Inferring Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.056s, Peak memory usage = 83.445MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 83.445MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 83.445MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.181s, Peak memory usage = 83.445MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.054s, Peak memory usage = 83.445MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.038s, Peak memory usage = 83.445MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 108.449MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.171s, Peak memory usage = 108.449MB Generate output files: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.167s, Peak memory usage = 108.449MB |
| Total Time and Memory Usage | CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 108.449MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 90 |
| I/O Buf | 90 |
| IBUF | 37 |
| OBUF | 53 |
| Register | 1438 |
| DFFRE | 839 |
| DFFPE | 9 |
| DFFCE | 590 |
| LUT | 937 |
| LUT2 | 57 |
| LUT3 | 596 |
| LUT4 | 284 |
| ALU | 40 |
| ALU | 40 |
| INV | 11 |
| INV | 11 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 988(948 LUT, 40 ALU) / 138240 | <1% |
| Register | 1438 / 139140 | 2% |
| --Register as Latch | 0 / 139140 | 0% |
| --Register as FF | 1438 / 139140 | 2% |
| BSRAM | 0 / 340 | 0% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk_i | Base | 10.000 | 100.000 | 0.000 | 5.000 | clk_i_ibuf/I |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk_i | 100.000(MHz) | 128.452(MHz) | 7 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 2.215 |
| Data Arrival Time | 8.134 |
| Data Required Time | 10.349 |
| From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_26_s0 |
| To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_6_s0 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1438 | clk_i_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_26_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_26_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s6/I0 |
| 1.786 | 0.579 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s6/F |
| 2.199 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s2/I1 |
| 2.349 | 0.150 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s2/O |
| 2.761 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s0/I1 |
| 2.848 | 0.086 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s0/O |
| 3.260 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s48/I2 |
| 3.768 | 0.507 | tINS | RR | 4 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s48/F |
| 4.180 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s47/I0 |
| 4.759 | 0.579 | tINS | RR | 5 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s47/F |
| 5.171 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s44/I1 |
| 5.739 | 0.567 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s44/F |
| 6.151 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s40/I0 |
| 6.730 | 0.579 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s40/F |
| 7.143 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s39/I0 |
| 7.721 | 0.579 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s39/F |
| 8.134 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_6_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1438 | clk_i_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_6_s0/CLK |
| 10.349 | -0.064 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_6_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 3.626, 46.965%; route: 3.712, 48.081%; tC2Q: 0.382, 4.954% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 2
Path Summary:| Slack | 2.275 |
| Data Arrival Time | 8.074 |
| Data Required Time | 10.349 |
| From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_27_s0 |
| To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s1 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1438 | clk_i_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_27_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_27_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s6/I0 |
| 1.786 | 0.579 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s6/F |
| 2.199 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s2/I1 |
| 2.349 | 0.150 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s2/O |
| 2.761 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s0/I1 |
| 2.848 | 0.086 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s0/O |
| 3.260 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s49/I2 |
| 3.768 | 0.507 | tINS | RR | 3 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s49/F |
| 4.180 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s43/I0 |
| 4.759 | 0.579 | tINS | RR | 2 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n742_s43/F |
| 5.171 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s51/I2 |
| 5.679 | 0.507 | tINS | RR | 2 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s51/F |
| 6.091 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s48/I0 |
| 6.670 | 0.579 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s48/F |
| 7.083 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s47/I0 |
| 7.661 | 0.579 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n743_s47/F |
| 8.074 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1438 | clk_i_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s1/CLK |
| 10.349 | -0.064 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_1_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 3.566, 46.549%; route: 3.712, 48.458%; tC2Q: 0.382, 4.993% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 3
Path Summary:| Slack | 2.357 |
| Data Arrival Time | 7.991 |
| Data Required Time | 10.349 |
| From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_26_s0 |
| To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s0 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1438 | clk_i_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_26_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_26_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s6/I0 |
| 1.786 | 0.579 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s6/F |
| 2.199 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s2/I1 |
| 2.349 | 0.150 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s2/O |
| 2.761 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s0/I1 |
| 2.848 | 0.086 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s0/O |
| 3.260 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s48/I2 |
| 3.768 | 0.507 | tINS | RR | 4 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s48/F |
| 4.180 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s47/I0 |
| 4.759 | 0.579 | tINS | RR | 5 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s47/F |
| 5.171 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s43/I1 |
| 5.739 | 0.567 | tINS | RR | 2 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s43/F |
| 6.151 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s42/I2 |
| 6.659 | 0.507 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s42/F |
| 7.071 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s39/I2 |
| 7.579 | 0.507 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n744_s39/F |
| 7.991 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1438 | clk_i_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s0/CLK |
| 10.349 | -0.064 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 3.484, 45.967%; route: 3.712, 48.986%; tC2Q: 0.382, 5.047% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 4
Path Summary:| Slack | 2.505 |
| Data Arrival Time | 7.844 |
| Data Required Time | 10.349 |
| From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_27_s0 |
| To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_3_s0 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1438 | clk_i_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_27_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_27_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s6/I0 |
| 1.786 | 0.579 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s6/F |
| 2.199 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s2/I1 |
| 2.349 | 0.150 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s2/O |
| 2.761 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s0/I1 |
| 2.848 | 0.086 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n196_s0/O |
| 3.260 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s49/I2 |
| 3.768 | 0.507 | tINS | RR | 3 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s49/F |
| 4.180 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s43/I0 |
| 4.759 | 0.579 | tINS | RR | 2 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s43/F |
| 5.171 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s44/I1 |
| 5.739 | 0.567 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s44/F |
| 6.151 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s42/I0 |
| 6.730 | 0.579 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s42/F |
| 7.143 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s39/I3 |
| 7.431 | 0.289 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n741_s39/F |
| 7.844 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_3_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1438 | clk_i_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_3_s0/CLK |
| 10.349 | -0.064 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_3_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 3.336, 44.895%; route: 3.712, 49.958%; tC2Q: 0.382, 5.147% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 5
Path Summary:| Slack | 3.195 |
| Data Arrival Time | 7.154 |
| Data Required Time | 10.349 |
| From | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_26_s0 |
| To | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s1 |
| Launch Clk | clk_i[R] |
| Latch Clk | clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 1438 | clk_i_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_26_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_fifo_rdata_reg_26_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s6/I0 |
| 1.786 | 0.579 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s6/F |
| 2.199 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s2/I1 |
| 2.349 | 0.150 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s2/O |
| 2.761 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s0/I1 |
| 2.848 | 0.086 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n195_s0/O |
| 3.260 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s48/I2 |
| 3.768 | 0.507 | tINS | RR | 4 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s48/F |
| 4.180 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s47/I0 |
| 4.759 | 0.579 | tINS | RR | 5 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n738_s47/F |
| 5.171 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s51/I0 |
| 5.750 | 0.579 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s51/F |
| 6.163 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s50/I0 |
| 6.741 | 0.579 | tINS | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/n740_s50/F |
| 7.154 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 1438 | clk_i_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s1/CLK |
| 10.349 | -0.064 | tSu | 1 | uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/tx_data_4_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 3.059, 45.374%; route: 3.300, 48.952%; tC2Q: 0.382, 5.674% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |