Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\SERDES_IP\IPlib\QSGMII\data\ge_pcs_qsgmii_wrap.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\SERDES_IP\IPlib\QSGMII\data\ge_pcs_qsgmii.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12.01 (64-bit) |
| Part Number | GW5AST-LV138FPG676AES |
| Device | GW5AST-138 |
| Device Version | B |
| Created Time | Tue Dec 30 10:25:31 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | QSGMII_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.75s, Elapsed time = 0h 0m 0.893s, Peak memory usage = 129.754MB Running netlist conversion: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.204s, Peak memory usage = 129.754MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 129.754MB Optimizing Phase 1: CPU time = 0h 0m 0.937s, Elapsed time = 0h 0m 0.936s, Peak memory usage = 129.754MB Optimizing Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 129.754MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.718s, Elapsed time = 0h 0m 0.723s, Peak memory usage = 129.754MB Inferring Phase 1: CPU time = 0h 0m 0.453s, Elapsed time = 0h 0m 0.453s, Peak memory usage = 129.754MB Inferring Phase 2: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.176s, Peak memory usage = 129.754MB Inferring Phase 3: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.063s, Peak memory usage = 129.754MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.937s, Elapsed time = 0h 0m 0.933s, Peak memory usage = 129.754MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.39s, Elapsed time = 0h 0m 0.385s, Peak memory usage = 129.754MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.184s, Peak memory usage = 129.754MB Tech-Mapping Phase 3: CPU time = 0h 0m 14s, Elapsed time = 0h 0m 14s, Peak memory usage = 153.223MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.984s, Elapsed time = 0h 0m 1s, Peak memory usage = 153.223MB Generate output files: CPU time = 0h 0m 0.843s, Elapsed time = 0h 0m 1s, Peak memory usage = 196.941MB |
| Total Time and Memory Usage | CPU time = 0h 0m 22s, Elapsed time = 0h 0m 22s, Peak memory usage = 196.941MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 1323 |
| I/O Buf | 1309 |
| IBUF | 624 |
| OBUF | 685 |
| Register | 6209 |
| DFFRE | 141 |
| DFFPE | 328 |
| DFFCE | 5740 |
| LUT | 6623 |
| LUT2 | 905 |
| LUT3 | 1239 |
| LUT4 | 4479 |
| ALU | 168 |
| ALU | 168 |
| INV | 37 |
| INV | 37 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 6828(6660 LUT, 168 ALU) / 138240 | 5% |
| Register | 6209 / 139140 | 5% |
| --Register as Latch | 0 / 139140 | 0% |
| --Register as FF | 6209 / 139140 | 5% |
| BSRAM | 0 / 340 | 0% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | serdes_pcs_rx_clk_i | Base | 10.000 | 100.000 | 0.000 | 5.000 | serdes_pcs_rx_clk_i_ibuf/I | ||
| 2 | serdes_pcs_tx_clk_i | Base | 10.000 | 100.000 | 0.000 | 5.000 | serdes_pcs_tx_clk_i_ibuf/I | ||
| 3 | clk_in_i | Base | 10.000 | 100.000 | 0.000 | 5.000 | clk_in_i_ibuf/I | ||
| 4 | miim_hs_clk_ch0_i | Base | 10.000 | 100.000 | 0.000 | 5.000 | miim_hs_clk_ch0_i_ibuf/I | ||
| 5 | miim_hs_clk_ch1_i | Base | 10.000 | 100.000 | 0.000 | 5.000 | miim_hs_clk_ch1_i_ibuf/I | ||
| 6 | miim_hs_clk_ch2_i | Base | 10.000 | 100.000 | 0.000 | 5.000 | miim_hs_clk_ch2_i_ibuf/I | ||
| 7 | miim_hs_clk_ch3_i | Base | 10.000 | 100.000 | 0.000 | 5.000 | miim_hs_clk_ch3_i_ibuf/I |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | serdes_pcs_rx_clk_i | 100.000(MHz) | 172.637(MHz) | 6 | TOP |
| 2 | serdes_pcs_tx_clk_i | 100.000(MHz) | 144.928(MHz) | 7 | TOP |
| 3 | clk_in_i | 100.000(MHz) | 856.531(MHz) | 1 | TOP |
| 4 | miim_hs_clk_ch0_i | 100.000(MHz) | 171.306(MHz) | 6 | TOP |
| 5 | miim_hs_clk_ch1_i | 100.000(MHz) | 171.306(MHz) | 6 | TOP |
| 6 | miim_hs_clk_ch2_i | 100.000(MHz) | 179.897(MHz) | 6 | TOP |
| 7 | miim_hs_clk_ch3_i | 100.000(MHz) | 179.897(MHz) | 6 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 3.100 |
| Data Arrival Time | 7.001 |
| Data Required Time | 10.101 |
| From | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/frm_byte_cnt_9_s3 |
| To | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/back_cnt_0_s1 |
| Launch Clk | serdes_pcs_tx_clk_i[R] |
| Latch Clk | serdes_pcs_tx_clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | serdes_pcs_tx_clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | serdes_pcs_tx_clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 2528 | serdes_pcs_tx_clk_i_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/frm_byte_cnt_9_s3/CLK |
| 0.795 | 0.382 | tC2Q | RR | 4 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/frm_byte_cnt_9_s3/Q |
| 1.207 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n2116_s6/I0 |
| 1.786 | 0.579 | tINS | RR | 3 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n2116_s6/F |
| 2.199 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_idle_s25/I1 |
| 2.766 | 0.567 | tINS | RR | 2 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_idle_s25/F |
| 3.179 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_idle_s20/I0 |
| 3.758 | 0.579 | tINS | RR | 2 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_idle_s20/F |
| 4.170 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n_state.s_back_off_s11/I0 |
| 4.749 | 0.579 | tINS | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n_state.s_back_off_s11/F |
| 5.161 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n_state.s_back_off_s10/I2 |
| 5.669 | 0.507 | tINS | RR | 2 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n_state.s_back_off_s10/F |
| 6.081 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n1088_s0/I2 |
| 6.589 | 0.507 | tINS | RR | 16 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n1088_s0/F |
| 7.001 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/back_cnt_0_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | serdes_pcs_tx_clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | serdes_pcs_tx_clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 2528 | serdes_pcs_tx_clk_i_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/back_cnt_0_s1/CLK |
| 10.101 | -0.311 | tSu | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/back_cnt_0_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 3.319, 50.370%; route: 2.887, 43.825%; tC2Q: 0.382, 5.805% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 2
Path Summary:| Slack | 3.100 |
| Data Arrival Time | 7.001 |
| Data Required Time | 10.101 |
| From | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/frm_byte_cnt_9_s3 |
| To | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/back_cnt_1_s1 |
| Launch Clk | serdes_pcs_tx_clk_i[R] |
| Latch Clk | serdes_pcs_tx_clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | serdes_pcs_tx_clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | serdes_pcs_tx_clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 2528 | serdes_pcs_tx_clk_i_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/frm_byte_cnt_9_s3/CLK |
| 0.795 | 0.382 | tC2Q | RR | 4 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/frm_byte_cnt_9_s3/Q |
| 1.207 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n2116_s6/I0 |
| 1.786 | 0.579 | tINS | RR | 3 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n2116_s6/F |
| 2.199 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_idle_s25/I1 |
| 2.766 | 0.567 | tINS | RR | 2 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_idle_s25/F |
| 3.179 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_idle_s20/I0 |
| 3.758 | 0.579 | tINS | RR | 2 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_idle_s20/F |
| 4.170 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n_state.s_back_off_s11/I0 |
| 4.749 | 0.579 | tINS | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n_state.s_back_off_s11/F |
| 5.161 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n_state.s_back_off_s10/I2 |
| 5.669 | 0.507 | tINS | RR | 2 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n_state.s_back_off_s10/F |
| 6.081 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n1088_s0/I2 |
| 6.589 | 0.507 | tINS | RR | 16 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n1088_s0/F |
| 7.001 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/back_cnt_1_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | serdes_pcs_tx_clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | serdes_pcs_tx_clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 2528 | serdes_pcs_tx_clk_i_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/back_cnt_1_s1/CLK |
| 10.101 | -0.311 | tSu | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/back_cnt_1_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 3.319, 50.370%; route: 2.887, 43.825%; tC2Q: 0.382, 5.805% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 3
Path Summary:| Slack | 3.100 |
| Data Arrival Time | 7.001 |
| Data Required Time | 10.101 |
| From | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/frm_byte_cnt_9_s3 |
| To | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/back_cnt_2_s1 |
| Launch Clk | serdes_pcs_tx_clk_i[R] |
| Latch Clk | serdes_pcs_tx_clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | serdes_pcs_tx_clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | serdes_pcs_tx_clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 2528 | serdes_pcs_tx_clk_i_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/frm_byte_cnt_9_s3/CLK |
| 0.795 | 0.382 | tC2Q | RR | 4 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/frm_byte_cnt_9_s3/Q |
| 1.207 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n2116_s6/I0 |
| 1.786 | 0.579 | tINS | RR | 3 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n2116_s6/F |
| 2.199 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_idle_s25/I1 |
| 2.766 | 0.567 | tINS | RR | 2 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_idle_s25/F |
| 3.179 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_idle_s20/I0 |
| 3.758 | 0.579 | tINS | RR | 2 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_idle_s20/F |
| 4.170 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n_state.s_back_off_s11/I0 |
| 4.749 | 0.579 | tINS | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n_state.s_back_off_s11/F |
| 5.161 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n_state.s_back_off_s10/I2 |
| 5.669 | 0.507 | tINS | RR | 2 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n_state.s_back_off_s10/F |
| 6.081 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n1088_s0/I2 |
| 6.589 | 0.507 | tINS | RR | 16 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n1088_s0/F |
| 7.001 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/back_cnt_2_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | serdes_pcs_tx_clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | serdes_pcs_tx_clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 2528 | serdes_pcs_tx_clk_i_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/back_cnt_2_s1/CLK |
| 10.101 | -0.311 | tSu | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/back_cnt_2_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 3.319, 50.370%; route: 2.887, 43.825%; tC2Q: 0.382, 5.805% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 4
Path Summary:| Slack | 3.100 |
| Data Arrival Time | 7.001 |
| Data Required Time | 10.101 |
| From | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/frm_byte_cnt_9_s3 |
| To | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/back_cnt_3_s1 |
| Launch Clk | serdes_pcs_tx_clk_i[R] |
| Latch Clk | serdes_pcs_tx_clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | serdes_pcs_tx_clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | serdes_pcs_tx_clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 2528 | serdes_pcs_tx_clk_i_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/frm_byte_cnt_9_s3/CLK |
| 0.795 | 0.382 | tC2Q | RR | 4 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/frm_byte_cnt_9_s3/Q |
| 1.207 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n2116_s6/I0 |
| 1.786 | 0.579 | tINS | RR | 3 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n2116_s6/F |
| 2.199 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_idle_s25/I1 |
| 2.766 | 0.567 | tINS | RR | 2 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_idle_s25/F |
| 3.179 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_idle_s20/I0 |
| 3.758 | 0.579 | tINS | RR | 2 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_idle_s20/F |
| 4.170 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n_state.s_back_off_s11/I0 |
| 4.749 | 0.579 | tINS | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n_state.s_back_off_s11/F |
| 5.161 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n_state.s_back_off_s10/I2 |
| 5.669 | 0.507 | tINS | RR | 2 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n_state.s_back_off_s10/F |
| 6.081 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n1088_s0/I2 |
| 6.589 | 0.507 | tINS | RR | 16 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n1088_s0/F |
| 7.001 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/back_cnt_3_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | serdes_pcs_tx_clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | serdes_pcs_tx_clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 2528 | serdes_pcs_tx_clk_i_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/back_cnt_3_s1/CLK |
| 10.101 | -0.311 | tSu | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/back_cnt_3_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 3.319, 50.370%; route: 2.887, 43.825%; tC2Q: 0.382, 5.805% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 5
Path Summary:| Slack | 3.100 |
| Data Arrival Time | 7.001 |
| Data Required Time | 10.101 |
| From | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/frm_byte_cnt_9_s3 |
| To | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/back_cnt_4_s1 |
| Launch Clk | serdes_pcs_tx_clk_i[R] |
| Latch Clk | serdes_pcs_tx_clk_i[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | serdes_pcs_tx_clk_i | |||
| 0.000 | 0.000 | tCL | RR | 1 | serdes_pcs_tx_clk_i_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 2528 | serdes_pcs_tx_clk_i_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/frm_byte_cnt_9_s3/CLK |
| 0.795 | 0.382 | tC2Q | RR | 4 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/frm_byte_cnt_9_s3/Q |
| 1.207 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n2116_s6/I0 |
| 1.786 | 0.579 | tINS | RR | 3 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n2116_s6/F |
| 2.199 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_idle_s25/I1 |
| 2.766 | 0.567 | tINS | RR | 2 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_idle_s25/F |
| 3.179 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_idle_s20/I0 |
| 3.758 | 0.579 | tINS | RR | 2 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/c_state.s_idle_s20/F |
| 4.170 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n_state.s_back_off_s11/I0 |
| 4.749 | 0.579 | tINS | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n_state.s_back_off_s11/F |
| 5.161 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n_state.s_back_off_s10/I2 |
| 5.669 | 0.507 | tINS | RR | 2 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n_state.s_back_off_s10/F |
| 6.081 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n1088_s0/I2 |
| 6.589 | 0.507 | tINS | RR | 16 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/n1088_s0/F |
| 7.001 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/back_cnt_4_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | serdes_pcs_tx_clk_i | |||
| 10.000 | 0.000 | tCL | RR | 1 | serdes_pcs_tx_clk_i_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 2528 | serdes_pcs_tx_clk_i_ibuf/O |
| 10.413 | 0.413 | tNET | RR | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/back_cnt_4_s1/CLK |
| 10.101 | -0.311 | tSu | 1 | u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/back_cnt_4_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 3.319, 50.370%; route: 2.887, 43.825%; tC2Q: 0.382, 5.805% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |