Timing Messages

Report Title	Timing Analysis Report
Design File	E:\IP_Release\QSGMII\191201\Gowin_QSGMII_IP_RefDesign\project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File	E:\IP_Release\QSGMII\191201\Gowin_QSGMII_IP_RefDesign\project\src\fpga_project.cst
Timing Constraint File	E:\IP_Release\QSGMII\191201\Gowin_QSGMII_IP_RefDesign\project\src\fpga_project.sdc
Tool Version	V1.9.12.01 (64-bit)
Part Number	GW5AST-LV138FPG676AES
Device	GW5AST-138
Device Version	B
Created Time	Tue Dec 30 11:03:41 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.855V 0C ES
Hold Delay Model	Fast 0.945V 85C ES
Numbers of Paths Analyzed	35232
Numbers of Endpoints Analyzed	38096
Numbers of Falling Endpoints	3
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	tck_pad	Base	50.000	20.000	0.000	25.000			gw_gao_inst_0/tck_ibuf/I
2	clk_in	Base	20.000	50.000	0.000	10.000			clk_in_ibuf/I
3	tx_mac_clk	Base	8.000	125.000	0.000	4.000			tx_mac_clk[3]
4	rx_mac_clk	Base	8.000	125.000	0.000	4.000			rx_mac_clk[3]
5	clk_uart	Generated	100.000	10.000	0.000	50.000	clk_in_ibuf/I	clk_in	u_pll_uart/u_pll/PLL_inst/CLKOUT0

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	tck_pad	20.000(MHz)	140.141(MHz)	6	TOP
2	tx_mac_clk	125.000(MHz)	128.964(MHz)	7	TOP
3	rx_mac_clk	125.000(MHz)	153.374(MHz)	3	TOP
4	clk_uart	10.000(MHz)	70.954(MHz)	9	TOP

No timing paths to get frequency of clk_in!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
tck_pad	Setup	0.000	0
tck_pad	Hold	0.000	0
clk_in	Setup	0.000	0
clk_in	Hold	0.000	0
tx_mac_clk	Setup	0.000	0
tx_mac_clk	Hold	0.000	0
rx_mac_clk	Setup	0.000	0
rx_mac_clk	Hold	0.000	0
clk_uart	Setup	0.000	0
clk_uart	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.246	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/Q	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_0_s1/CE	tx_mac_clk:[R]	tx_mac_clk:[R]	8.000	0.000	7.443
2	0.246	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/Q	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_1_s1/CE	tx_mac_clk:[R]	tx_mac_clk:[R]	8.000	0.000	7.443
3	0.246	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/Q	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_2_s1/CE	tx_mac_clk:[R]	tx_mac_clk:[R]	8.000	0.000	7.443
4	0.246	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/Q	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_3_s1/CE	tx_mac_clk:[R]	tx_mac_clk:[R]	8.000	0.000	7.443
5	0.246	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/Q	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_4_s1/CE	tx_mac_clk:[R]	tx_mac_clk:[R]	8.000	0.000	7.443
6	0.584	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/c_state_0_s0/Q	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/encode_txd_1_s1/D	tx_mac_clk:[R]	tx_mac_clk:[R]	8.000	0.039	7.314
7	0.685	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/Q	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_7_s1/CE	tx_mac_clk:[R]	tx_mac_clk:[R]	8.000	-0.016	7.020
8	0.685	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/Q	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_8_s1/CE	tx_mac_clk:[R]	tx_mac_clk:[R]	8.000	-0.016	7.020
9	0.685	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/Q	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_14_s1/CE	tx_mac_clk:[R]	tx_mac_clk:[R]	8.000	-0.016	7.020
10	0.768	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_pad_s8/Q	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/back_cnt_10_s1/CE	tx_mac_clk:[R]	tx_mac_clk:[R]	8.000	0.019	6.901
11	0.768	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_pad_s8/Q	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/back_cnt_11_s1/CE	tx_mac_clk:[R]	tx_mac_clk:[R]	8.000	0.019	6.901
12	0.774	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_pad_s8/Q	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/back_cnt_5_s1/CE	tx_mac_clk:[R]	tx_mac_clk:[R]	8.000	0.013	6.901
13	0.774	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_pad_s8/Q	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/back_cnt_9_s1/CE	tx_mac_clk:[R]	tx_mac_clk:[R]	8.000	0.013	6.901
14	0.881	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/c_state_0_s0/Q	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/encode_txd_2_s1/D	tx_mac_clk:[R]	tx_mac_clk:[R]	8.000	0.039	7.016
15	0.885	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/Q	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_9_s1/CE	tx_mac_clk:[R]	tx_mac_clk:[R]	8.000	0.000	6.804
16	0.885	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/Q	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_10_s1/CE	tx_mac_clk:[R]	tx_mac_clk:[R]	8.000	0.000	6.804
17	0.885	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/Q	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_11_s1/CE	tx_mac_clk:[R]	tx_mac_clk:[R]	8.000	0.000	6.804
18	0.885	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/Q	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_12_s1/CE	tx_mac_clk:[R]	tx_mac_clk:[R]	8.000	0.000	6.804
19	0.885	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/Q	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_15_s1/CE	tx_mac_clk:[R]	tx_mac_clk:[R]	8.000	0.000	6.804
20	0.894	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/Q	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_5_s1/CE	tx_mac_clk:[R]	tx_mac_clk:[R]	8.000	-0.009	6.804
21	0.894	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/Q	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_6_s1/CE	tx_mac_clk:[R]	tx_mac_clk:[R]	8.000	-0.009	6.804
22	0.902	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/Q	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_13_s1/CE	tx_mac_clk:[R]	tx_mac_clk:[R]	8.000	-0.007	6.794
23	0.956	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/c_state_3_s0/Q	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/encode_txd_3_s1/D	tx_mac_clk:[R]	tx_mac_clk:[R]	8.000	-0.041	7.021
24	1.002	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_pad_s8/Q	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/back_cnt_7_s1/CE	tx_mac_clk:[R]	tx_mac_clk:[R]	8.000	0.031	6.656
25	1.002	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_pad_s8/Q	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/back_cnt_8_s1/CE	tx_mac_clk:[R]	tx_mac_clk:[R]	8.000	0.031	6.656

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.198	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[4]	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	-0.009	0.244
2	0.205	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_2_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[2]	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.005	0.237
3	0.209	gw_gao_inst_0/u_la0_top/expression0_data_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/DI[0]	tck_pad:[R]	tck_pad:[R]	0.000	0.015	0.231
4	0.213	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[11]	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	-0.014	0.264
5	0.216	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[10]	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	-0.014	0.267
6	0.243	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[3]	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.001	0.279
7	0.253	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[0]	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	-0.009	0.299
8	0.270	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[3]	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	-0.014	0.321
9	0.275	test[3].u_mac_rx_model/rx_data_cnt_last_s4/Q	test[3].u_mac_rx_model/rx_data_cnt_last_s4/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300
10	0.275	test[3].u_mac_rx_model/shift_reg_pause_3_s1/Q	test[3].u_mac_rx_model/shift_reg_pause_3_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300
11	0.275	test[3].u_mac_rx_model/pause_address_32_s1/Q	test[3].u_mac_rx_model/pause_address_32_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300
12	0.275	test[3].u_mac_rx_model/shift_reg_1_s1/Q	test[3].u_mac_rx_model/shift_reg_1_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300
13	0.275	test[3].u_mac_rx_model/shift_reg_2_s1/Q	test[3].u_mac_rx_model/shift_reg_2_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300
14	0.275	test[3].u_mac_rx_model/shift_reg_5_s1/Q	test[3].u_mac_rx_model/shift_reg_5_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300
15	0.275	test[3].u_mac_rx_model/shift_reg_7_s1/Q	test[3].u_mac_rx_model/shift_reg_7_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300
16	0.275	test[3].u_mac_rx_model/shift_reg_12_s1/Q	test[3].u_mac_rx_model/shift_reg_12_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300
17	0.275	test[3].u_mac_rx_model/shift_reg_18_s1/Q	test[3].u_mac_rx_model/shift_reg_18_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300
18	0.275	test[3].u_mac_rx_model/shift_reg_19_s1/Q	test[3].u_mac_rx_model/shift_reg_19_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300
19	0.275	test[3].u_mac_rx_model/shift_reg_20_s1/Q	test[3].u_mac_rx_model/shift_reg_20_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300
20	0.275	test[3].u_mac_rx_model/shift_reg_24_s1/Q	test[3].u_mac_rx_model/shift_reg_24_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300
21	0.275	test[3].u_mac_rx_model/shift_reg_42_s1/Q	test[3].u_mac_rx_model/shift_reg_42_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300
22	0.275	test[3].u_mac_rx_model/shift_reg_49_s1/Q	test[3].u_mac_rx_model/shift_reg_49_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300
23	0.275	test[3].u_mac_rx_model/shift_reg_51_s1/Q	test[3].u_mac_rx_model/shift_reg_51_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300
24	0.275	test[3].u_mac_rx_model/shift_reg_53_s1/Q	test[3].u_mac_rx_model/shift_reg_53_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300
25	0.275	test[3].u_mac_rx_model/shift_reg_60_s1/Q	test[3].u_mac_rx_model/shift_reg_60_s1/D	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.300

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.945	rx_mac_rst_n_3_s0/Q	test[3].u_mac_rx_model/rx_error_all_pause_check_s4/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	8.000	0.031	6.676
2	1.194	rx_mac_rst_n_3_s0/Q	test[3].u_mac_rx_model/rx_error_all_data_check_s4/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	8.000	0.038	6.420
3	1.225	rx_mac_rst_n_3_s0/Q	test[3].u_mac_rx_model/pause_address_35_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	8.000	-0.010	6.438
4	1.225	rx_mac_rst_n_3_s0/Q	test[3].u_mac_rx_model/pause_address_42_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	8.000	-0.010	6.438
5	1.225	rx_mac_rst_n_3_s0/Q	test[3].u_mac_rx_model/pause_address_43_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	8.000	-0.010	6.438
6	1.225	rx_mac_rst_n_3_s0/Q	test[3].u_mac_rx_model/pause_address_44_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	8.000	-0.010	6.438
7	1.234	rx_mac_rst_n_3_s0/Q	test[3].u_mac_rx_model/shift_reg_pause_57_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	8.000	-0.019	6.438
8	1.234	rx_mac_rst_n_3_s0/Q	test[3].u_mac_rx_model/pause_data_2_5_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	8.000	-0.019	6.438
9	1.234	rx_mac_rst_n_3_s0/Q	test[3].u_mac_rx_model/pause_data_2_9_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	8.000	-0.019	6.438
10	1.234	rx_mac_rst_n_3_s0/Q	test[3].u_mac_rx_model/pause_data_2_12_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	8.000	-0.019	6.438
11	1.234	rx_mac_rst_n_3_s0/Q	test[3].u_mac_rx_model/pause_data_2_13_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	8.000	-0.019	6.438
12	1.298	rx_mac_rst_n_3_s0/Q	test[3].u_mac_rx_model/shift_reg_pause_31_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	8.000	-0.027	6.381
13	1.298	rx_mac_rst_n_3_s0/Q	test[3].u_mac_rx_model/shift_reg_pause_39_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	8.000	-0.027	6.381
14	1.298	rx_mac_rst_n_3_s0/Q	test[3].u_mac_rx_model/shift_reg_pause_47_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	8.000	-0.027	6.381
15	1.298	rx_mac_rst_n_3_s0/Q	test[3].u_mac_rx_model/pause_data_3_47_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	8.000	-0.027	6.381
16	1.300	rx_mac_rst_n_3_s0/Q	cycle_one_time_3_s0/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	8.000	-0.029	6.381
17	1.302	rx_mac_rst_n_3_s0/Q	test[3].u_mac_rx_model/pause_data_2_0_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	8.000	-0.022	6.373
18	1.302	rx_mac_rst_n_3_s0/Q	test[3].u_mac_rx_model/pause_data_2_4_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	8.000	-0.022	6.373
19	1.302	rx_mac_rst_n_3_s0/Q	test[3].u_mac_rx_model/rx_running_s0/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	8.000	-0.022	6.373
20	1.430	rx_mac_rst_n_3_s0/Q	test[3].u_mac_rx_model/shift_reg_pause_51_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	8.000	-0.012	6.235
21	1.430	rx_mac_rst_n_3_s0/Q	test[3].u_mac_rx_model/shift_reg_pause_53_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	8.000	-0.012	6.235
22	1.430	rx_mac_rst_n_3_s0/Q	test[3].u_mac_rx_model/shift_reg_pause_61_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	8.000	-0.012	6.235
23	1.430	rx_mac_rst_n_3_s0/Q	test[3].u_mac_rx_model/pause_data_2_3_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	8.000	-0.012	6.235
24	1.442	rx_mac_rst_n_3_s0/Q	test[3].u_mac_rx_model/pause_data_2_14_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	8.000	-0.007	6.218
25	1.467	rx_mac_rst_n_3_s0/Q	test[3].u_mac_rx_model/pause_data_2_7_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	8.000	0.000	6.185

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.386	rx_mac_rst_n_3_s0/Q	cycle_all_time_3_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	-0.005	0.338
2	0.386	rx_mac_rst_n_3_s0/Q	rx_running_d1_3_s0/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	-0.005	0.338
3	0.393	rx_mac_rst_n_1_s0/Q	test[1].u_mac_rx_model/rx_running_s0/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.340
4	0.393	rx_mac_rst_n_1_s0/Q	cycle_all_time_1_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.340
5	0.393	rx_mac_rst_n_1_s0/Q	rx_running_d1_1_s0/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.340
6	0.425	rx_mac_rst_n_0_s0/Q	test[0].u_mac_rx_model/rx_running_s0/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	-0.006	0.378
7	0.425	rx_mac_rst_n_0_s0/Q	rx_running_d1_0_s0/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	-0.006	0.378
8	0.548	rx_mac_rst_n_3_s0/Q	test[3].u_mac_rx_model/rx_data_cnt_pause_3_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	-0.011	0.506
9	0.548	rx_mac_rst_n_3_s0/Q	test[3].u_mac_rx_model/rx_data_cnt_pause_4_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	-0.011	0.506
10	0.548	rx_mac_rst_n_3_s0/Q	test[3].u_mac_rx_model/rx_data_cnt_pause_6_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	-0.011	0.506
11	0.548	rx_mac_rst_n_3_s0/Q	test[3].u_mac_rx_model/rx_data_cnt_pause_7_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	-0.011	0.506
12	0.548	rx_mac_rst_n_3_s0/Q	test[3].u_mac_rx_model/rx_data_cnt_pause_8_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	-0.011	0.506
13	0.548	rx_mac_rst_n_3_s0/Q	test[3].u_mac_rx_model/pause_address_36_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	-0.011	0.506
14	0.576	rx_mac_rst_n_2_s0/Q	test[2].u_mac_rx_model/rx_running_s0/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	-0.042	0.565
15	0.588	rx_mac_rst_n_0_s0/Q	cycle_all_time_0_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.018	0.517
16	0.591	rstn_uart_s0/Q	u_sysreg/reg0x0032_7_s0/CLEAR	clk_uart:[R]	clk_uart:[R]	0.000	0.006	0.532
17	0.591	rstn_uart_s0/Q	u_sysreg/reg0x0010_2_s0/CLEAR	clk_uart:[R]	clk_uart:[R]	0.000	0.006	0.532
18	0.595	rstn_uart_s0/Q	u_sysreg/reg0x0022_15_s0/CLEAR	clk_uart:[R]	clk_uart:[R]	0.000	0.010	0.532
19	0.595	rstn_uart_s0/Q	u_sysreg/reg0x0012_13_s0/CLEAR	clk_uart:[R]	clk_uart:[R]	0.000	0.010	0.532
20	0.595	rstn_uart_s0/Q	u_sysreg/reg0x0000_2_s0/CLEAR	clk_uart:[R]	clk_uart:[R]	0.000	0.010	0.532
21	0.623	rx_mac_rst_n_2_s0/Q	cycle_one_time_2_s0/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	-0.013	0.583
22	0.624	rx_mac_rst_n_3_s0/Q	test[3].u_mac_rx_model/rx_frm_cnt_6_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	-0.004	0.575
23	0.624	rx_mac_rst_n_3_s0/Q	test[3].u_mac_rx_model/rx_frm_cnt_7_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	-0.004	0.575
24	0.628	rx_mac_rst_n_3_s0/Q	test[3].u_mac_rx_model/latch_data_end_s2/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.575
25	0.628	rx_mac_rst_n_3_s0/Q	test[3].u_mac_rx_model/pause_data_3_5_s1/CLEAR	rx_mac_clk:[R]	rx_mac_clk:[R]	0.000	0.000	0.575

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	0.902	1.902	1.000	High Pulse Width	rx_mac_clk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
2	0.902	1.902	1.000	High Pulse Width	rx_mac_clk	gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s
3	1.041	2.041	1.000	Low Pulse Width	rx_mac_clk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
4	1.041	2.041	1.000	Low Pulse Width	rx_mac_clk	gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s
5	1.591	1.841	0.250	High Pulse Width	rx_mac_clk	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_an/an_sync_status_fail_cnt_12_s1
6	1.591	1.841	0.250	High Pulse Width	rx_mac_clk	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_an/an_sync_status_fail_cnt_11_s1
7	1.591	1.841	0.250	High Pulse Width	rx_mac_clk	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/serdes_rxdata_i_d1_43_s0
8	1.591	1.841	0.250	High Pulse Width	rx_mac_clk	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_rx_ctrl/u_crc_chk/crc_reg_0_s1
9	1.591	1.841	0.250	High Pulse Width	rx_mac_clk	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_an/an_sync_status_fail_cnt_15_s1
10	1.591	1.841	0.250	High Pulse Width	rx_mac_clk	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_an/an_sync_status_fail_cnt_14_s1

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.246
Data Arrival Time	11.350
Data Required Time	11.596
From	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5
To	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_0_s1
Launch Clk	tx_mac_clk:[R]
Latch Clk	tx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tx_mac_clk
0.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.908	3.908	tNET	RR	1	R60C128[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/CLK
4.290	0.382	tC2Q	RR	9	R60C128[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/Q
5.354	1.064	tNET	RR	1	R59C130[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_preamble_s28/I1
5.933	0.579	tINS	RR	2	R59C130[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_preamble_s28/F
5.938	0.005	tNET	RR	1	R59C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s28/I0
6.516	0.579	tINS	RR	1	R59C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s28/F
6.898	0.381	tNET	RR	1	R58C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s22/I1
7.465	0.567	tINS	RR	2	R58C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s22/F
7.828	0.363	tNET	RR	1	R60C130[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s11/I1
8.406	0.579	tINS	RR	1	R60C130[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s11/F
8.579	0.172	tNET	RR	1	R61C130[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s10/I2
9.035	0.456	tINS	RR	2	R61C130[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s10/F
9.744	0.709	tNET	RR	1	R61C135[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n1088_s0/I2
10.318	0.574	tINS	RR	16	R61C135[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n1088_s0/F
11.350	1.033	tNET	RR	1	R62C135[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_0_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					tx_mac_clk
8.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.907	3.907	tNET	RR	1	R62C135[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_0_s1/CLK
11.596	-0.311	tSu		1	R62C135[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_0_s1

Path Statistics:

Clock Skew	-0.000
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.908, 100.000%
Arrival Data Path Delay	cell: 3.334, 44.793%; route: 3.726, 50.067%; tC2Q: 0.382, 5.139%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.907, 100.000%

Path2

Path Summary:

Slack	0.246
Data Arrival Time	11.350
Data Required Time	11.596
From	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5
To	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_1_s1
Launch Clk	tx_mac_clk:[R]
Latch Clk	tx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tx_mac_clk
0.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.908	3.908	tNET	RR	1	R60C128[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/CLK
4.290	0.382	tC2Q	RR	9	R60C128[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/Q
5.354	1.064	tNET	RR	1	R59C130[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_preamble_s28/I1
5.933	0.579	tINS	RR	2	R59C130[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_preamble_s28/F
5.938	0.005	tNET	RR	1	R59C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s28/I0
6.516	0.579	tINS	RR	1	R59C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s28/F
6.898	0.381	tNET	RR	1	R58C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s22/I1
7.465	0.567	tINS	RR	2	R58C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s22/F
7.828	0.363	tNET	RR	1	R60C130[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s11/I1
8.406	0.579	tINS	RR	1	R60C130[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s11/F
8.579	0.172	tNET	RR	1	R61C130[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s10/I2
9.035	0.456	tINS	RR	2	R61C130[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s10/F
9.744	0.709	tNET	RR	1	R61C135[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n1088_s0/I2
10.318	0.574	tINS	RR	16	R61C135[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n1088_s0/F
11.350	1.033	tNET	RR	1	R62C135[2][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_1_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					tx_mac_clk
8.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.907	3.907	tNET	RR	1	R62C135[2][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_1_s1/CLK
11.596	-0.311	tSu		1	R62C135[2][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_1_s1

Path Statistics:

Clock Skew	-0.000
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.908, 100.000%
Arrival Data Path Delay	cell: 3.334, 44.793%; route: 3.726, 50.067%; tC2Q: 0.382, 5.139%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.907, 100.000%

Path3

Path Summary:

Slack	0.246
Data Arrival Time	11.350
Data Required Time	11.596
From	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5
To	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_2_s1
Launch Clk	tx_mac_clk:[R]
Latch Clk	tx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tx_mac_clk
0.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.908	3.908	tNET	RR	1	R60C128[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/CLK
4.290	0.382	tC2Q	RR	9	R60C128[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/Q
5.354	1.064	tNET	RR	1	R59C130[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_preamble_s28/I1
5.933	0.579	tINS	RR	2	R59C130[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_preamble_s28/F
5.938	0.005	tNET	RR	1	R59C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s28/I0
6.516	0.579	tINS	RR	1	R59C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s28/F
6.898	0.381	tNET	RR	1	R58C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s22/I1
7.465	0.567	tINS	RR	2	R58C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s22/F
7.828	0.363	tNET	RR	1	R60C130[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s11/I1
8.406	0.579	tINS	RR	1	R60C130[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s11/F
8.579	0.172	tNET	RR	1	R61C130[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s10/I2
9.035	0.456	tINS	RR	2	R61C130[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s10/F
9.744	0.709	tNET	RR	1	R61C135[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n1088_s0/I2
10.318	0.574	tINS	RR	16	R61C135[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n1088_s0/F
11.350	1.033	tNET	RR	1	R62C135[1][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_2_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					tx_mac_clk
8.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.907	3.907	tNET	RR	1	R62C135[1][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_2_s1/CLK
11.596	-0.311	tSu		1	R62C135[1][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_2_s1

Path Statistics:

Clock Skew	-0.000
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.908, 100.000%
Arrival Data Path Delay	cell: 3.334, 44.793%; route: 3.726, 50.067%; tC2Q: 0.382, 5.139%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.907, 100.000%

Path4

Path Summary:

Slack	0.246
Data Arrival Time	11.350
Data Required Time	11.596
From	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5
To	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_3_s1
Launch Clk	tx_mac_clk:[R]
Latch Clk	tx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tx_mac_clk
0.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.908	3.908	tNET	RR	1	R60C128[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/CLK
4.290	0.382	tC2Q	RR	9	R60C128[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/Q
5.354	1.064	tNET	RR	1	R59C130[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_preamble_s28/I1
5.933	0.579	tINS	RR	2	R59C130[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_preamble_s28/F
5.938	0.005	tNET	RR	1	R59C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s28/I0
6.516	0.579	tINS	RR	1	R59C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s28/F
6.898	0.381	tNET	RR	1	R58C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s22/I1
7.465	0.567	tINS	RR	2	R58C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s22/F
7.828	0.363	tNET	RR	1	R60C130[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s11/I1
8.406	0.579	tINS	RR	1	R60C130[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s11/F
8.579	0.172	tNET	RR	1	R61C130[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s10/I2
9.035	0.456	tINS	RR	2	R61C130[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s10/F
9.744	0.709	tNET	RR	1	R61C135[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n1088_s0/I2
10.318	0.574	tINS	RR	16	R61C135[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n1088_s0/F
11.350	1.033	tNET	RR	1	R62C135[0][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_3_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					tx_mac_clk
8.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.907	3.907	tNET	RR	1	R62C135[0][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_3_s1/CLK
11.596	-0.311	tSu		1	R62C135[0][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_3_s1

Path Statistics:

Clock Skew	-0.000
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.908, 100.000%
Arrival Data Path Delay	cell: 3.334, 44.793%; route: 3.726, 50.067%; tC2Q: 0.382, 5.139%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.907, 100.000%

Path5

Path Summary:

Slack	0.246
Data Arrival Time	11.350
Data Required Time	11.596
From	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5
To	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_4_s1
Launch Clk	tx_mac_clk:[R]
Latch Clk	tx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tx_mac_clk
0.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.908	3.908	tNET	RR	1	R60C128[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/CLK
4.290	0.382	tC2Q	RR	9	R60C128[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/Q
5.354	1.064	tNET	RR	1	R59C130[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_preamble_s28/I1
5.933	0.579	tINS	RR	2	R59C130[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_preamble_s28/F
5.938	0.005	tNET	RR	1	R59C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s28/I0
6.516	0.579	tINS	RR	1	R59C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s28/F
6.898	0.381	tNET	RR	1	R58C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s22/I1
7.465	0.567	tINS	RR	2	R58C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s22/F
7.828	0.363	tNET	RR	1	R60C130[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s11/I1
8.406	0.579	tINS	RR	1	R60C130[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s11/F
8.579	0.172	tNET	RR	1	R61C130[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s10/I2
9.035	0.456	tINS	RR	2	R61C130[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s10/F
9.744	0.709	tNET	RR	1	R61C135[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n1088_s0/I2
10.318	0.574	tINS	RR	16	R61C135[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n1088_s0/F
11.350	1.033	tNET	RR	1	R62C135[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_4_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					tx_mac_clk
8.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.907	3.907	tNET	RR	1	R62C135[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_4_s1/CLK
11.596	-0.311	tSu		1	R62C135[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_4_s1

Path Statistics:

Clock Skew	-0.000
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.908, 100.000%
Arrival Data Path Delay	cell: 3.334, 44.793%; route: 3.726, 50.067%; tC2Q: 0.382, 5.139%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.907, 100.000%

Path6

Path Summary:

Slack	0.584
Data Arrival Time	11.248
Data Required Time	11.831
From	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/c_state_0_s0
To	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/encode_txd_1_s1
Launch Clk	tx_mac_clk:[R]
Latch Clk	tx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tx_mac_clk
0.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.934	3.934	tNET	RR	1	R57C146[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/c_state_0_s0/CLK
4.301	0.368	tC2Q	RF	20	R57C146[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/c_state_0_s0/Q
5.160	0.859	tNET	FF	1	R58C149[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/config_cnt_3_s4/I1
5.616	0.456	tINS	FR	12	R58C149[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/config_cnt_3_s4/F
6.601	0.985	tNET	RR	1	R58C145[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/n256_s10/I3
7.109	0.507	tINS	RR	3	R58C145[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/n256_s10/F
7.116	0.008	tNET	RR	1	R58C145[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/n250_s4/I2
7.695	0.579	tINS	RR	2	R58C145[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/n250_s4/F
8.365	0.670	tNET	RR	1	R54C148[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/n255_s2/I2
8.821	0.456	tINS	RR	1	R54C148[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/n255_s2/F
9.240	0.419	tNET	RR	1	R54C145[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/n255_s1/I1
9.819	0.579	tINS	RR	1	R54C145[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/n255_s1/F
11.248	1.429	tNET	RR	1	R47C130[0][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/encode_txd_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					tx_mac_clk
8.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.895	3.895	tNET	RR	1	R47C130[0][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/encode_txd_1_s1/CLK
11.831	-0.064	tSu		1	R47C130[0][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/encode_txd_1_s1

Path Statistics:

Clock Skew	-0.039
Setup Relationship	8.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.934, 100.000%
Arrival Data Path Delay	cell: 2.577, 35.242%; route: 4.369, 59.733%; tC2Q: 0.368, 5.025%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.895, 100.000%

Path7

Path Summary:

Slack	0.685
Data Arrival Time	10.927
Data Required Time	11.613
From	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5
To	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_7_s1
Launch Clk	tx_mac_clk:[R]
Latch Clk	tx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tx_mac_clk
0.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.908	3.908	tNET	RR	1	R60C128[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/CLK
4.290	0.382	tC2Q	RR	9	R60C128[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/Q
5.354	1.064	tNET	RR	1	R59C130[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_preamble_s28/I1
5.933	0.579	tINS	RR	2	R59C130[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_preamble_s28/F
5.938	0.005	tNET	RR	1	R59C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s28/I0
6.516	0.579	tINS	RR	1	R59C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s28/F
6.898	0.381	tNET	RR	1	R58C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s22/I1
7.465	0.567	tINS	RR	2	R58C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s22/F
7.828	0.363	tNET	RR	1	R60C130[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s11/I1
8.406	0.579	tINS	RR	1	R60C130[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s11/F
8.579	0.172	tNET	RR	1	R61C130[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s10/I2
9.035	0.456	tINS	RR	2	R61C130[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s10/F
9.744	0.709	tNET	RR	1	R61C135[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n1088_s0/I2
10.318	0.574	tINS	RR	16	R61C135[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n1088_s0/F
10.928	0.610	tNET	RR	1	R61C134[0][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_7_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					tx_mac_clk
8.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.924	3.924	tNET	RR	1	R61C134[0][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_7_s1/CLK
11.613	-0.311	tSu		1	R61C134[0][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_7_s1

Path Statistics:

Clock Skew	0.016
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.908, 100.000%
Arrival Data Path Delay	cell: 3.334, 47.489%; route: 3.304, 47.062%; tC2Q: 0.382, 5.449%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.924, 100.000%

Path8

Path Summary:

Slack	0.685
Data Arrival Time	10.927
Data Required Time	11.613
From	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5
To	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_8_s1
Launch Clk	tx_mac_clk:[R]
Latch Clk	tx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tx_mac_clk
0.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.908	3.908	tNET	RR	1	R60C128[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/CLK
4.290	0.382	tC2Q	RR	9	R60C128[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/Q
5.354	1.064	tNET	RR	1	R59C130[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_preamble_s28/I1
5.933	0.579	tINS	RR	2	R59C130[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_preamble_s28/F
5.938	0.005	tNET	RR	1	R59C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s28/I0
6.516	0.579	tINS	RR	1	R59C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s28/F
6.898	0.381	tNET	RR	1	R58C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s22/I1
7.465	0.567	tINS	RR	2	R58C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s22/F
7.828	0.363	tNET	RR	1	R60C130[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s11/I1
8.406	0.579	tINS	RR	1	R60C130[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s11/F
8.579	0.172	tNET	RR	1	R61C130[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s10/I2
9.035	0.456	tINS	RR	2	R61C130[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s10/F
9.744	0.709	tNET	RR	1	R61C135[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n1088_s0/I2
10.318	0.574	tINS	RR	16	R61C135[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n1088_s0/F
10.928	0.610	tNET	RR	1	R61C134[2][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_8_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					tx_mac_clk
8.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.924	3.924	tNET	RR	1	R61C134[2][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_8_s1/CLK
11.613	-0.311	tSu		1	R61C134[2][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_8_s1

Path Statistics:

Clock Skew	0.016
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.908, 100.000%
Arrival Data Path Delay	cell: 3.334, 47.489%; route: 3.304, 47.062%; tC2Q: 0.382, 5.449%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.924, 100.000%

Path9

Path Summary:

Slack	0.685
Data Arrival Time	10.927
Data Required Time	11.613
From	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5
To	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_14_s1
Launch Clk	tx_mac_clk:[R]
Latch Clk	tx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tx_mac_clk
0.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.908	3.908	tNET	RR	1	R60C128[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/CLK
4.290	0.382	tC2Q	RR	9	R60C128[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/Q
5.354	1.064	tNET	RR	1	R59C130[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_preamble_s28/I1
5.933	0.579	tINS	RR	2	R59C130[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_preamble_s28/F
5.938	0.005	tNET	RR	1	R59C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s28/I0
6.516	0.579	tINS	RR	1	R59C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s28/F
6.898	0.381	tNET	RR	1	R58C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s22/I1
7.465	0.567	tINS	RR	2	R58C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s22/F
7.828	0.363	tNET	RR	1	R60C130[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s11/I1
8.406	0.579	tINS	RR	1	R60C130[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s11/F
8.579	0.172	tNET	RR	1	R61C130[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s10/I2
9.035	0.456	tINS	RR	2	R61C130[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s10/F
9.744	0.709	tNET	RR	1	R61C135[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n1088_s0/I2
10.318	0.574	tINS	RR	16	R61C135[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n1088_s0/F
10.928	0.610	tNET	RR	1	R61C134[1][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_14_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					tx_mac_clk
8.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.924	3.924	tNET	RR	1	R61C134[1][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_14_s1/CLK
11.613	-0.311	tSu		1	R61C134[1][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_14_s1

Path Statistics:

Clock Skew	0.016
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.908, 100.000%
Arrival Data Path Delay	cell: 3.334, 47.489%; route: 3.304, 47.062%; tC2Q: 0.382, 5.449%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.924, 100.000%

Path10

Path Summary:

Slack	0.768
Data Arrival Time	10.801
Data Required Time	11.570
From	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_pad_s8
To	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/back_cnt_10_s1
Launch Clk	tx_mac_clk:[R]
Latch Clk	tx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tx_mac_clk
0.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.900	3.900	tNET	RR	1	R27C133[0][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_pad_s8/CLK
4.283	0.382	tC2Q	RR	6	R27C133[0][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_pad_s8/Q
5.034	0.751	tNET	RR	1	R25C132[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n_state.s_jam_s45/I1
5.608	0.574	tINS	RR	9	R25C132[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n_state.s_jam_s45/F
6.213	0.605	tNET	RR	1	R26C131[1][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_idle_s28/I0
6.720	0.507	tINS	RR	1	R26C131[1][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_idle_s28/F
7.101	0.381	tNET	RR	1	R26C133[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_idle_s22/I2
7.680	0.579	tINS	RR	2	R26C133[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_idle_s22/F
8.213	0.533	tNET	RR	1	R27C134[2][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n_state.s_back_off_s11/I1
8.720	0.507	tINS	RR	1	R27C134[2][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n_state.s_back_off_s11/F
8.722	0.003	tNET	RR	1	R27C134[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n_state.s_back_off_s10/I2
9.230	0.507	tINS	RR	2	R27C134[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n_state.s_back_off_s10/F
9.589	0.359	tNET	RR	1	R29C134[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n1088_s0/I2
10.163	0.574	tINS	RR	16	R29C134[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n1088_s0/F
10.801	0.639	tNET	RR	1	R32C135[1][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/back_cnt_10_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					tx_mac_clk
8.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.881	3.881	tNET	RR	1	R32C135[1][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/back_cnt_10_s1/CLK
11.570	-0.311	tSu		1	R32C135[1][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/back_cnt_10_s1

Path Statistics:

Clock Skew	-0.019
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.900, 100.000%
Arrival Data Path Delay	cell: 3.249, 47.075%; route: 3.270, 47.383%; tC2Q: 0.382, 5.542%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.881, 100.000%

Path11

Path Summary:

Slack	0.768
Data Arrival Time	10.801
Data Required Time	11.570
From	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_pad_s8
To	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/back_cnt_11_s1
Launch Clk	tx_mac_clk:[R]
Latch Clk	tx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tx_mac_clk
0.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.900	3.900	tNET	RR	1	R27C133[0][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_pad_s8/CLK
4.283	0.382	tC2Q	RR	6	R27C133[0][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_pad_s8/Q
5.034	0.751	tNET	RR	1	R25C132[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n_state.s_jam_s45/I1
5.608	0.574	tINS	RR	9	R25C132[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n_state.s_jam_s45/F
6.213	0.605	tNET	RR	1	R26C131[1][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_idle_s28/I0
6.720	0.507	tINS	RR	1	R26C131[1][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_idle_s28/F
7.101	0.381	tNET	RR	1	R26C133[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_idle_s22/I2
7.680	0.579	tINS	RR	2	R26C133[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_idle_s22/F
8.213	0.533	tNET	RR	1	R27C134[2][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n_state.s_back_off_s11/I1
8.720	0.507	tINS	RR	1	R27C134[2][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n_state.s_back_off_s11/F
8.722	0.003	tNET	RR	1	R27C134[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n_state.s_back_off_s10/I2
9.230	0.507	tINS	RR	2	R27C134[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n_state.s_back_off_s10/F
9.589	0.359	tNET	RR	1	R29C134[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n1088_s0/I2
10.163	0.574	tINS	RR	16	R29C134[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n1088_s0/F
10.801	0.639	tNET	RR	1	R32C135[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/back_cnt_11_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					tx_mac_clk
8.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.881	3.881	tNET	RR	1	R32C135[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/back_cnt_11_s1/CLK
11.570	-0.311	tSu		1	R32C135[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/back_cnt_11_s1

Path Statistics:

Clock Skew	-0.019
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.900, 100.000%
Arrival Data Path Delay	cell: 3.249, 47.075%; route: 3.270, 47.383%; tC2Q: 0.382, 5.542%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.881, 100.000%

Path12

Path Summary:

Slack	0.774
Data Arrival Time	10.801
Data Required Time	11.576
From	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_pad_s8
To	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/back_cnt_5_s1
Launch Clk	tx_mac_clk:[R]
Latch Clk	tx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tx_mac_clk
0.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.900	3.900	tNET	RR	1	R27C133[0][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_pad_s8/CLK
4.283	0.382	tC2Q	RR	6	R27C133[0][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_pad_s8/Q
5.034	0.751	tNET	RR	1	R25C132[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n_state.s_jam_s45/I1
5.608	0.574	tINS	RR	9	R25C132[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n_state.s_jam_s45/F
6.213	0.605	tNET	RR	1	R26C131[1][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_idle_s28/I0
6.720	0.507	tINS	RR	1	R26C131[1][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_idle_s28/F
7.101	0.381	tNET	RR	1	R26C133[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_idle_s22/I2
7.680	0.579	tINS	RR	2	R26C133[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_idle_s22/F
8.213	0.533	tNET	RR	1	R27C134[2][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n_state.s_back_off_s11/I1
8.720	0.507	tINS	RR	1	R27C134[2][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n_state.s_back_off_s11/F
8.722	0.003	tNET	RR	1	R27C134[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n_state.s_back_off_s10/I2
9.230	0.507	tINS	RR	2	R27C134[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n_state.s_back_off_s10/F
9.589	0.359	tNET	RR	1	R29C134[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n1088_s0/I2
10.163	0.574	tINS	RR	16	R29C134[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n1088_s0/F
10.801	0.639	tNET	RR	1	R33C135[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/back_cnt_5_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					tx_mac_clk
8.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.887	3.887	tNET	RR	1	R33C135[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/back_cnt_5_s1/CLK
11.576	-0.311	tSu		1	R33C135[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/back_cnt_5_s1

Path Statistics:

Clock Skew	-0.013
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.900, 100.000%
Arrival Data Path Delay	cell: 3.249, 47.075%; route: 3.270, 47.383%; tC2Q: 0.382, 5.542%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.887, 100.000%

Path13

Path Summary:

Slack	0.774
Data Arrival Time	10.801
Data Required Time	11.576
From	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_pad_s8
To	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/back_cnt_9_s1
Launch Clk	tx_mac_clk:[R]
Latch Clk	tx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tx_mac_clk
0.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.900	3.900	tNET	RR	1	R27C133[0][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_pad_s8/CLK
4.283	0.382	tC2Q	RR	6	R27C133[0][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_pad_s8/Q
5.034	0.751	tNET	RR	1	R25C132[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n_state.s_jam_s45/I1
5.608	0.574	tINS	RR	9	R25C132[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n_state.s_jam_s45/F
6.213	0.605	tNET	RR	1	R26C131[1][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_idle_s28/I0
6.720	0.507	tINS	RR	1	R26C131[1][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_idle_s28/F
7.101	0.381	tNET	RR	1	R26C133[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_idle_s22/I2
7.680	0.579	tINS	RR	2	R26C133[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_idle_s22/F
8.213	0.533	tNET	RR	1	R27C134[2][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n_state.s_back_off_s11/I1
8.720	0.507	tINS	RR	1	R27C134[2][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n_state.s_back_off_s11/F
8.722	0.003	tNET	RR	1	R27C134[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n_state.s_back_off_s10/I2
9.230	0.507	tINS	RR	2	R27C134[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n_state.s_back_off_s10/F
9.589	0.359	tNET	RR	1	R29C134[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n1088_s0/I2
10.163	0.574	tINS	RR	16	R29C134[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n1088_s0/F
10.801	0.639	tNET	RR	1	R33C135[1][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/back_cnt_9_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					tx_mac_clk
8.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.887	3.887	tNET	RR	1	R33C135[1][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/back_cnt_9_s1/CLK
11.576	-0.311	tSu		1	R33C135[1][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/back_cnt_9_s1

Path Statistics:

Clock Skew	-0.013
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.900, 100.000%
Arrival Data Path Delay	cell: 3.249, 47.075%; route: 3.270, 47.383%; tC2Q: 0.382, 5.542%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.887, 100.000%

Path14

Path Summary:

Slack	0.881
Data Arrival Time	10.950
Data Required Time	11.831
From	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/c_state_0_s0
To	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/encode_txd_2_s1
Launch Clk	tx_mac_clk:[R]
Latch Clk	tx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tx_mac_clk
0.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.934	3.934	tNET	RR	1	R57C146[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/c_state_0_s0/CLK
4.301	0.368	tC2Q	RF	20	R57C146[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/c_state_0_s0/Q
5.160	0.859	tNET	FF	1	R58C149[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/config_cnt_3_s4/I1
5.616	0.456	tINS	FR	12	R58C149[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/config_cnt_3_s4/F
6.601	0.985	tNET	RR	1	R58C145[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/n256_s10/I3
7.109	0.507	tINS	RR	3	R58C145[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/n256_s10/F
7.116	0.008	tNET	RR	1	R58C145[0][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/n254_s4/I2
7.695	0.579	tINS	RR	1	R58C145[0][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/n254_s4/F
8.175	0.480	tNET	RR	1	R54C146[2][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/n254_s2/I3
8.683	0.507	tINS	RR	1	R54C146[2][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/n254_s2/F
8.893	0.210	tNET	RR	1	R54C145[2][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/n254_s1/I2
9.460	0.567	tINS	RR	1	R54C145[2][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/n254_s1/F
10.950	1.490	tNET	RR	1	R47C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/encode_txd_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					tx_mac_clk
8.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.895	3.895	tNET	RR	1	R47C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/encode_txd_2_s1/CLK
11.831	-0.064	tSu		1	R47C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/encode_txd_2_s1

Path Statistics:

Clock Skew	-0.039
Setup Relationship	8.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.934, 100.000%
Arrival Data Path Delay	cell: 2.617, 37.306%; route: 4.031, 57.456%; tC2Q: 0.368, 5.238%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.895, 100.000%

Path15

Path Summary:

Slack	0.885
Data Arrival Time	10.711
Data Required Time	11.596
From	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5
To	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_9_s1
Launch Clk	tx_mac_clk:[R]
Latch Clk	tx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tx_mac_clk
0.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.908	3.908	tNET	RR	1	R60C128[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/CLK
4.290	0.382	tC2Q	RR	9	R60C128[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/Q
5.354	1.064	tNET	RR	1	R59C130[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_preamble_s28/I1
5.933	0.579	tINS	RR	2	R59C130[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_preamble_s28/F
5.938	0.005	tNET	RR	1	R59C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s28/I0
6.516	0.579	tINS	RR	1	R59C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s28/F
6.898	0.381	tNET	RR	1	R58C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s22/I1
7.465	0.567	tINS	RR	2	R58C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s22/F
7.828	0.363	tNET	RR	1	R60C130[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s11/I1
8.406	0.579	tINS	RR	1	R60C130[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s11/F
8.579	0.172	tNET	RR	1	R61C130[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s10/I2
9.035	0.456	tINS	RR	2	R61C130[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s10/F
9.744	0.709	tNET	RR	1	R61C135[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n1088_s0/I2
10.318	0.574	tINS	RR	16	R61C135[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n1088_s0/F
10.711	0.394	tNET	RR	1	R62C133[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_9_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					tx_mac_clk
8.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.907	3.907	tNET	RR	1	R62C133[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_9_s1/CLK
11.596	-0.311	tSu		1	R62C133[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_9_s1

Path Statistics:

Clock Skew	-0.000
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.908, 100.000%
Arrival Data Path Delay	cell: 3.334, 48.999%; route: 3.088, 45.379%; tC2Q: 0.382, 5.622%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.907, 100.000%

Path16

Path Summary:

Slack	0.885
Data Arrival Time	10.711
Data Required Time	11.596
From	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5
To	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_10_s1
Launch Clk	tx_mac_clk:[R]
Latch Clk	tx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tx_mac_clk
0.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.908	3.908	tNET	RR	1	R60C128[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/CLK
4.290	0.382	tC2Q	RR	9	R60C128[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/Q
5.354	1.064	tNET	RR	1	R59C130[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_preamble_s28/I1
5.933	0.579	tINS	RR	2	R59C130[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_preamble_s28/F
5.938	0.005	tNET	RR	1	R59C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s28/I0
6.516	0.579	tINS	RR	1	R59C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s28/F
6.898	0.381	tNET	RR	1	R58C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s22/I1
7.465	0.567	tINS	RR	2	R58C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s22/F
7.828	0.363	tNET	RR	1	R60C130[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s11/I1
8.406	0.579	tINS	RR	1	R60C130[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s11/F
8.579	0.172	tNET	RR	1	R61C130[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s10/I2
9.035	0.456	tINS	RR	2	R61C130[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s10/F
9.744	0.709	tNET	RR	1	R61C135[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n1088_s0/I2
10.318	0.574	tINS	RR	16	R61C135[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n1088_s0/F
10.711	0.394	tNET	RR	1	R62C133[1][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_10_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					tx_mac_clk
8.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.907	3.907	tNET	RR	1	R62C133[1][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_10_s1/CLK
11.596	-0.311	tSu		1	R62C133[1][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_10_s1

Path Statistics:

Clock Skew	-0.000
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.908, 100.000%
Arrival Data Path Delay	cell: 3.334, 48.999%; route: 3.088, 45.379%; tC2Q: 0.382, 5.622%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.907, 100.000%

Path17

Path Summary:

Slack	0.885
Data Arrival Time	10.711
Data Required Time	11.596
From	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5
To	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_11_s1
Launch Clk	tx_mac_clk:[R]
Latch Clk	tx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tx_mac_clk
0.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.908	3.908	tNET	RR	1	R60C128[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/CLK
4.290	0.382	tC2Q	RR	9	R60C128[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/Q
5.354	1.064	tNET	RR	1	R59C130[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_preamble_s28/I1
5.933	0.579	tINS	RR	2	R59C130[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_preamble_s28/F
5.938	0.005	tNET	RR	1	R59C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s28/I0
6.516	0.579	tINS	RR	1	R59C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s28/F
6.898	0.381	tNET	RR	1	R58C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s22/I1
7.465	0.567	tINS	RR	2	R58C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s22/F
7.828	0.363	tNET	RR	1	R60C130[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s11/I1
8.406	0.579	tINS	RR	1	R60C130[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s11/F
8.579	0.172	tNET	RR	1	R61C130[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s10/I2
9.035	0.456	tINS	RR	2	R61C130[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s10/F
9.744	0.709	tNET	RR	1	R61C135[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n1088_s0/I2
10.318	0.574	tINS	RR	16	R61C135[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n1088_s0/F
10.711	0.394	tNET	RR	1	R62C133[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_11_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					tx_mac_clk
8.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.907	3.907	tNET	RR	1	R62C133[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_11_s1/CLK
11.596	-0.311	tSu		1	R62C133[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_11_s1

Path Statistics:

Clock Skew	-0.000
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.908, 100.000%
Arrival Data Path Delay	cell: 3.334, 48.999%; route: 3.088, 45.379%; tC2Q: 0.382, 5.622%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.907, 100.000%

Path18

Path Summary:

Slack	0.885
Data Arrival Time	10.711
Data Required Time	11.596
From	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5
To	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_12_s1
Launch Clk	tx_mac_clk:[R]
Latch Clk	tx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tx_mac_clk
0.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.908	3.908	tNET	RR	1	R60C128[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/CLK
4.290	0.382	tC2Q	RR	9	R60C128[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/Q
5.354	1.064	tNET	RR	1	R59C130[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_preamble_s28/I1
5.933	0.579	tINS	RR	2	R59C130[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_preamble_s28/F
5.938	0.005	tNET	RR	1	R59C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s28/I0
6.516	0.579	tINS	RR	1	R59C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s28/F
6.898	0.381	tNET	RR	1	R58C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s22/I1
7.465	0.567	tINS	RR	2	R58C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s22/F
7.828	0.363	tNET	RR	1	R60C130[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s11/I1
8.406	0.579	tINS	RR	1	R60C130[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s11/F
8.579	0.172	tNET	RR	1	R61C130[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s10/I2
9.035	0.456	tINS	RR	2	R61C130[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s10/F
9.744	0.709	tNET	RR	1	R61C135[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n1088_s0/I2
10.318	0.574	tINS	RR	16	R61C135[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n1088_s0/F
10.711	0.394	tNET	RR	1	R62C133[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_12_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					tx_mac_clk
8.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.907	3.907	tNET	RR	1	R62C133[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_12_s1/CLK
11.596	-0.311	tSu		1	R62C133[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_12_s1

Path Statistics:

Clock Skew	-0.000
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.908, 100.000%
Arrival Data Path Delay	cell: 3.334, 48.999%; route: 3.088, 45.379%; tC2Q: 0.382, 5.622%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.907, 100.000%

Path19

Path Summary:

Slack	0.885
Data Arrival Time	10.711
Data Required Time	11.596
From	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5
To	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_15_s1
Launch Clk	tx_mac_clk:[R]
Latch Clk	tx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tx_mac_clk
0.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.908	3.908	tNET	RR	1	R60C128[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/CLK
4.290	0.382	tC2Q	RR	9	R60C128[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/Q
5.354	1.064	tNET	RR	1	R59C130[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_preamble_s28/I1
5.933	0.579	tINS	RR	2	R59C130[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_preamble_s28/F
5.938	0.005	tNET	RR	1	R59C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s28/I0
6.516	0.579	tINS	RR	1	R59C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s28/F
6.898	0.381	tNET	RR	1	R58C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s22/I1
7.465	0.567	tINS	RR	2	R58C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s22/F
7.828	0.363	tNET	RR	1	R60C130[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s11/I1
8.406	0.579	tINS	RR	1	R60C130[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s11/F
8.579	0.172	tNET	RR	1	R61C130[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s10/I2
9.035	0.456	tINS	RR	2	R61C130[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s10/F
9.744	0.709	tNET	RR	1	R61C135[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n1088_s0/I2
10.318	0.574	tINS	RR	16	R61C135[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n1088_s0/F
10.711	0.394	tNET	RR	1	R62C133[2][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_15_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					tx_mac_clk
8.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.907	3.907	tNET	RR	1	R62C133[2][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_15_s1/CLK
11.596	-0.311	tSu		1	R62C133[2][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_15_s1

Path Statistics:

Clock Skew	-0.000
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.908, 100.000%
Arrival Data Path Delay	cell: 3.334, 48.999%; route: 3.088, 45.379%; tC2Q: 0.382, 5.622%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.907, 100.000%

Path20

Path Summary:

Slack	0.894
Data Arrival Time	10.711
Data Required Time	11.605
From	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5
To	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_5_s1
Launch Clk	tx_mac_clk:[R]
Latch Clk	tx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tx_mac_clk
0.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.908	3.908	tNET	RR	1	R60C128[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/CLK
4.290	0.382	tC2Q	RR	9	R60C128[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/Q
5.354	1.064	tNET	RR	1	R59C130[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_preamble_s28/I1
5.933	0.579	tINS	RR	2	R59C130[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_preamble_s28/F
5.938	0.005	tNET	RR	1	R59C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s28/I0
6.516	0.579	tINS	RR	1	R59C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s28/F
6.898	0.381	tNET	RR	1	R58C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s22/I1
7.465	0.567	tINS	RR	2	R58C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s22/F
7.828	0.363	tNET	RR	1	R60C130[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s11/I1
8.406	0.579	tINS	RR	1	R60C130[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s11/F
8.579	0.172	tNET	RR	1	R61C130[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s10/I2
9.035	0.456	tINS	RR	2	R61C130[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s10/F
9.744	0.709	tNET	RR	1	R61C135[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n1088_s0/I2
10.318	0.574	tINS	RR	16	R61C135[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n1088_s0/F
10.711	0.394	tNET	RR	1	R62C134[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_5_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					tx_mac_clk
8.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.917	3.917	tNET	RR	1	R62C134[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_5_s1/CLK
11.605	-0.311	tSu		1	R62C134[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_5_s1

Path Statistics:

Clock Skew	0.009
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.908, 100.000%
Arrival Data Path Delay	cell: 3.334, 48.999%; route: 3.088, 45.379%; tC2Q: 0.382, 5.622%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.917, 100.000%

Path21

Path Summary:

Slack	0.894
Data Arrival Time	10.711
Data Required Time	11.605
From	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5
To	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_6_s1
Launch Clk	tx_mac_clk:[R]
Latch Clk	tx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tx_mac_clk
0.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.908	3.908	tNET	RR	1	R60C128[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/CLK
4.290	0.382	tC2Q	RR	9	R60C128[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/Q
5.354	1.064	tNET	RR	1	R59C130[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_preamble_s28/I1
5.933	0.579	tINS	RR	2	R59C130[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_preamble_s28/F
5.938	0.005	tNET	RR	1	R59C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s28/I0
6.516	0.579	tINS	RR	1	R59C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s28/F
6.898	0.381	tNET	RR	1	R58C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s22/I1
7.465	0.567	tINS	RR	2	R58C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s22/F
7.828	0.363	tNET	RR	1	R60C130[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s11/I1
8.406	0.579	tINS	RR	1	R60C130[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s11/F
8.579	0.172	tNET	RR	1	R61C130[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s10/I2
9.035	0.456	tINS	RR	2	R61C130[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s10/F
9.744	0.709	tNET	RR	1	R61C135[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n1088_s0/I2
10.318	0.574	tINS	RR	16	R61C135[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n1088_s0/F
10.711	0.394	tNET	RR	1	R62C134[0][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_6_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					tx_mac_clk
8.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.917	3.917	tNET	RR	1	R62C134[0][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_6_s1/CLK
11.605	-0.311	tSu		1	R62C134[0][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_6_s1

Path Statistics:

Clock Skew	0.009
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.908, 100.000%
Arrival Data Path Delay	cell: 3.334, 48.999%; route: 3.088, 45.379%; tC2Q: 0.382, 5.622%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.917, 100.000%

Path22

Path Summary:

Slack	0.902
Data Arrival Time	10.701
Data Required Time	11.603
From	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5
To	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_13_s1
Launch Clk	tx_mac_clk:[R]
Latch Clk	tx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tx_mac_clk
0.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.908	3.908	tNET	RR	1	R60C128[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/CLK
4.290	0.382	tC2Q	RR	9	R60C128[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/tx_pause_req_latch_s5/Q
5.354	1.064	tNET	RR	1	R59C130[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_preamble_s28/I1
5.933	0.579	tINS	RR	2	R59C130[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_preamble_s28/F
5.938	0.005	tNET	RR	1	R59C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s28/I0
6.516	0.579	tINS	RR	1	R59C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s28/F
6.898	0.381	tNET	RR	1	R58C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s22/I1
7.465	0.567	tINS	RR	2	R58C130[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/c_state.s_idle_s22/F
7.828	0.363	tNET	RR	1	R60C130[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s11/I1
8.406	0.579	tINS	RR	1	R60C130[1][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s11/F
8.579	0.172	tNET	RR	1	R61C130[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s10/I2
9.035	0.456	tINS	RR	2	R61C130[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n_state.s_back_off_s10/F
9.744	0.709	tNET	RR	1	R61C135[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n1088_s0/I2
10.318	0.574	tINS	RR	16	R61C135[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/n1088_s0/F
10.701	0.384	tNET	RR	1	R61C133[2][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_13_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					tx_mac_clk
8.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.914	3.914	tNET	RR	1	R61C133[2][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_13_s1/CLK
11.603	-0.311	tSu		1	R61C133[2][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/back_cnt_13_s1

Path Statistics:

Clock Skew	0.007
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.908, 100.000%
Arrival Data Path Delay	cell: 3.334, 49.071%; route: 3.078, 45.299%; tC2Q: 0.382, 5.630%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.914, 100.000%

Path23

Path Summary:

Slack	0.956
Data Arrival Time	10.878
Data Required Time	11.834
From	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/c_state_3_s0
To	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/encode_txd_3_s1
Launch Clk	tx_mac_clk:[R]
Latch Clk	tx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tx_mac_clk
0.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.857	3.857	tNET	RR	1	R57C147[1][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/c_state_3_s0/CLK
4.239	0.382	tC2Q	RR	21	R57C147[1][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/c_state_3_s0/Q
4.894	0.655	tNET	RR	1	R57C145[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/n152_s5/I1
5.462	0.567	tINS	RR	9	R57C145[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/n152_s5/F
5.898	0.436	tNET	RR	1	R56C146[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/encoder_tx_even_s7/I1
6.354	0.456	tINS	RR	9	R56C146[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/encoder_tx_even_s7/F
7.201	0.846	tNET	RR	1	R54C147[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/n253_s4/I0
7.768	0.567	tINS	RR	1	R54C147[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/n253_s4/F
8.333	0.565	tNET	RR	1	R58C147[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/n253_s2/I3
8.907	0.574	tINS	RR	1	R58C147[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/n253_s2/F
9.217	0.310	tNET	RR	1	R54C145[1][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/n253_s6/I3
9.724	0.507	tINS	RR	1	R54C145[1][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/n253_s6/F
10.878	1.154	tNET	RR	1	R44C136[0][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/encode_txd_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					tx_mac_clk
8.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.898	3.898	tNET	RR	1	R44C136[0][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/encode_txd_3_s1/CLK
11.834	-0.064	tSu		1	R44C136[0][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/encode_txd_3_s1

Path Statistics:

Clock Skew	0.041
Setup Relationship	8.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.857, 100.000%
Arrival Data Path Delay	cell: 2.672, 38.063%; route: 3.966, 56.489%; tC2Q: 0.382, 5.448%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.898, 100.000%

Path24

Path Summary:

Slack	1.002
Data Arrival Time	10.556
Data Required Time	11.558
From	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_pad_s8
To	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/back_cnt_7_s1
Launch Clk	tx_mac_clk:[R]
Latch Clk	tx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tx_mac_clk
0.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.900	3.900	tNET	RR	1	R27C133[0][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_pad_s8/CLK
4.283	0.382	tC2Q	RR	6	R27C133[0][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_pad_s8/Q
5.034	0.751	tNET	RR	1	R25C132[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n_state.s_jam_s45/I1
5.608	0.574	tINS	RR	9	R25C132[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n_state.s_jam_s45/F
6.213	0.605	tNET	RR	1	R26C131[1][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_idle_s28/I0
6.720	0.507	tINS	RR	1	R26C131[1][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_idle_s28/F
7.101	0.381	tNET	RR	1	R26C133[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_idle_s22/I2
7.680	0.579	tINS	RR	2	R26C133[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_idle_s22/F
8.213	0.533	tNET	RR	1	R27C134[2][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n_state.s_back_off_s11/I1
8.720	0.507	tINS	RR	1	R27C134[2][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n_state.s_back_off_s11/F
8.722	0.003	tNET	RR	1	R27C134[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n_state.s_back_off_s10/I2
9.230	0.507	tINS	RR	2	R27C134[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n_state.s_back_off_s10/F
9.589	0.359	tNET	RR	1	R29C134[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n1088_s0/I2
10.163	0.574	tINS	RR	16	R29C134[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n1088_s0/F
10.556	0.394	tNET	RR	1	R30C135[2][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/back_cnt_7_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					tx_mac_clk
8.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.869	3.869	tNET	RR	1	R30C135[2][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/back_cnt_7_s1/CLK
11.558	-0.311	tSu		1	R30C135[2][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/back_cnt_7_s1

Path Statistics:

Clock Skew	-0.031
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.900, 100.000%
Arrival Data Path Delay	cell: 3.249, 48.808%; route: 3.025, 45.446%; tC2Q: 0.382, 5.746%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.869, 100.000%

Path25

Path Summary:

Slack	1.002
Data Arrival Time	10.556
Data Required Time	11.558
From	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_pad_s8
To	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/back_cnt_8_s1
Launch Clk	tx_mac_clk:[R]
Latch Clk	tx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tx_mac_clk
0.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
3.900	3.900	tNET	RR	1	R27C133[0][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_pad_s8/CLK
4.283	0.382	tC2Q	RR	6	R27C133[0][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_pad_s8/Q
5.034	0.751	tNET	RR	1	R25C132[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n_state.s_jam_s45/I1
5.608	0.574	tINS	RR	9	R25C132[3][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n_state.s_jam_s45/F
6.213	0.605	tNET	RR	1	R26C131[1][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_idle_s28/I0
6.720	0.507	tINS	RR	1	R26C131[1][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_idle_s28/F
7.101	0.381	tNET	RR	1	R26C133[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_idle_s22/I2
7.680	0.579	tINS	RR	2	R26C133[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/c_state.s_idle_s22/F
8.213	0.533	tNET	RR	1	R27C134[2][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n_state.s_back_off_s11/I1
8.720	0.507	tINS	RR	1	R27C134[2][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n_state.s_back_off_s11/F
8.722	0.003	tNET	RR	1	R27C134[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n_state.s_back_off_s10/I2
9.230	0.507	tINS	RR	2	R27C134[0][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n_state.s_back_off_s10/F
9.589	0.359	tNET	RR	1	R29C134[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n1088_s0/I2
10.163	0.574	tINS	RR	16	R29C134[3][A]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/n1088_s0/F
10.556	0.394	tNET	RR	1	R30C135[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/back_cnt_8_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					tx_mac_clk
8.000	0.000	tCL	RR	3633	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_TX_O_FABRIC_CLK
11.869	3.869	tNET	RR	1	R30C135[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/back_cnt_8_s1/CLK
11.558	-0.311	tSu		1	R30C135[2][B]	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/back_cnt_8_s1

Path Statistics:

Clock Skew	-0.031
Setup Relationship	8.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.900, 100.000%
Arrival Data Path Delay	cell: 3.249, 48.808%; route: 3.025, 45.446%; tC2Q: 0.382, 5.746%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.869, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.198
Data Arrival Time	1.673
Data Required Time	1.475
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.429	1.429	tNET	RR	1	R47C153[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
1.570	0.141	tC2Q	RF	5	R47C153[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/Q
1.673	0.103	tNET	FF	1	BSRAM_R46[32]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[4]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.438	1.438	tNET	RR	1	BSRAM_R46[32]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.475	0.037	tHld		1	BSRAM_R46[32]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.009
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.429, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.103, 42.213%; tC2Q: 0.141, 57.787%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.438, 100.000%

Path2

Path Summary:

Slack	0.205
Data Arrival Time	1.680
Data Required Time	1.475
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_2_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.443	1.443	tNET	RR	1	R45C152[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_2_s0/CLK
1.587	0.144	tC2Q	RR	1	R45C152[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_2_s0/Q
1.680	0.093	tNET	RR	1	BSRAM_R46[32]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.438	1.438	tNET	RR	1	BSRAM_R46[32]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.475	0.037	tHld		1	BSRAM_R46[32]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	-0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.443, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.093, 39.241%; tC2Q: 0.144, 60.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.438, 100.000%

Path3

Path Summary:

Slack	0.209
Data Arrival Time	3.880
Data Required Time	3.671
From	gw_gao_inst_0/u_la0_top/expression0_data_s0
To	gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s
Launch Clk	tck_pad:[R]
Latch Clk	tck_pad:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad
0.000	0.000	tCL	RR	1	IOB173[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOB173[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R109C166	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	214	R109C166	gw_gao_inst_0/u_gw_jtag/tck_o
3.649	2.298	tNET	RR	1	R61C155[1][A]	gw_gao_inst_0/u_la0_top/expression0_data_s0/CLK
3.790	0.141	tC2Q	RF	1	R61C155[1][A]	gw_gao_inst_0/u_la0_top/expression0_data_s0/Q
3.880	0.090	tNET	FF	1	BSRAM_R46[33][A]	gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad
0.000	0.000	tCL	RR	1	IOB173[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOB173[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R109C166	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	214	R109C166	gw_gao_inst_0/u_gw_jtag/tck_o
3.634	2.283	tNET	RR	1	BSRAM_R46[33][A]	gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/CLKA
3.671	0.037	tHld		1	BSRAM_R46[33][A]	gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s

Path Statistics:

Clock Skew	-0.015
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.351, 37.024%; route: 2.298, 62.976%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.090, 38.961%; tC2Q: 0.141, 61.039%
Required Clock Path Delay	cell: 1.351, 37.177%; route: 2.283, 62.823%

Path4

Path Summary:

Slack	0.213
Data Arrival Time	1.688
Data Required Time	1.475
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.424	1.424	tNET	RR	1	R48C152[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
1.565	0.141	tC2Q	RF	4	R48C152[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/Q
1.688	0.123	tNET	FF	1	BSRAM_R46[32]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[11]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.438	1.438	tNET	RR	1	BSRAM_R46[32]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.475	0.037	tHld		1	BSRAM_R46[32]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.014
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.424, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.123, 46.591%; tC2Q: 0.141, 53.409%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.438, 100.000%

Path5

Path Summary:

Slack	0.216
Data Arrival Time	1.691
Data Required Time	1.475
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.424	1.424	tNET	RR	1	R48C152[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
1.565	0.141	tC2Q	RF	5	R48C152[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/Q
1.691	0.126	tNET	FF	1	BSRAM_R46[32]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[10]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.438	1.438	tNET	RR	1	BSRAM_R46[32]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.475	0.037	tHld		1	BSRAM_R46[32]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.014
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.424, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.126, 47.191%; tC2Q: 0.141, 52.809%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.438, 100.000%

Path6

Path Summary:

Slack	0.243
Data Arrival Time	1.718
Data Required Time	1.475
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.439	1.439	tNET	RR	1	R45C151[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_3_s0/CLK
1.583	0.144	tC2Q	RR	1	R45C151[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_3_s0/Q
1.718	0.135	tNET	RR	1	BSRAM_R46[32]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.438	1.438	tNET	RR	1	BSRAM_R46[32]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.475	0.037	tHld		1	BSRAM_R46[32]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	-0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.439, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.135, 48.387%; tC2Q: 0.144, 51.613%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.438, 100.000%

Path7

Path Summary:

Slack	0.253
Data Arrival Time	1.728
Data Required Time	1.475
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_0_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.429	1.429	tNET	RR	1	R47C151[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/CLK
1.570	0.141	tC2Q	RF	1	R47C151[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_0_s0/Q
1.728	0.158	tNET	FF	1	BSRAM_R46[32]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.438	1.438	tNET	RR	1	BSRAM_R46[32]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.475	0.037	tHld		1	BSRAM_R46[32]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.009
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.429, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.158, 52.843%; tC2Q: 0.141, 47.157%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.438, 100.000%

Path8

Path Summary:

Slack	0.270
Data Arrival Time	1.745
Data Required Time	1.475
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.424	1.424	tNET	RR	1	R48C152[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
1.565	0.141	tC2Q	RF	6	R48C152[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/Q
1.745	0.180	tNET	FF	1	BSRAM_R46[32]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.438	1.438	tNET	RR	1	BSRAM_R46[32]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.475	0.037	tHld		1	BSRAM_R46[32]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.014
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.424, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.180, 56.075%; tC2Q: 0.141, 43.925%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.438, 100.000%

Path9

Path Summary:

Slack	0.275
Data Arrival Time	1.763
Data Required Time	1.488
From	test[3].u_mac_rx_model/rx_data_cnt_last_s4
To	test[3].u_mac_rx_model/rx_data_cnt_last_s4
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.463	1.463	tNET	RR	1	R41C141[0][A]	test[3].u_mac_rx_model/rx_data_cnt_last_s4/CLK
1.604	0.141	tC2Q	RF	2	R41C141[0][A]	test[3].u_mac_rx_model/rx_data_cnt_last_s4/Q
1.610	0.006	tNET	FF	1	R41C141[0][A]	test[3].u_mac_rx_model/n1153_s4/I1
1.763	0.153	tINS	FF	1	R41C141[0][A]	test[3].u_mac_rx_model/n1153_s4/F
1.763	0.000	tNET	FF	1	R41C141[0][A]	test[3].u_mac_rx_model/rx_data_cnt_last_s4/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.463	1.463	tNET	RR	1	R41C141[0][A]	test[3].u_mac_rx_model/rx_data_cnt_last_s4/CLK
1.488	0.025	tHld		1	R41C141[0][A]	test[3].u_mac_rx_model/rx_data_cnt_last_s4

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.463, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.463, 100.000%

Path10

Path Summary:

Slack	0.275
Data Arrival Time	1.751
Data Required Time	1.476
From	test[3].u_mac_rx_model/shift_reg_pause_3_s1
To	test[3].u_mac_rx_model/shift_reg_pause_3_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.451	1.451	tNET	RR	1	R42C153[1][A]	test[3].u_mac_rx_model/shift_reg_pause_3_s1/CLK
1.592	0.141	tC2Q	RF	2	R42C153[1][A]	test[3].u_mac_rx_model/shift_reg_pause_3_s1/Q
1.598	0.006	tNET	FF	1	R42C153[1][A]	test[3].u_mac_rx_model/n1946_s0/I1
1.751	0.153	tINS	FF	1	R42C153[1][A]	test[3].u_mac_rx_model/n1946_s0/F
1.751	0.000	tNET	FF	1	R42C153[1][A]	test[3].u_mac_rx_model/shift_reg_pause_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.451	1.451	tNET	RR	1	R42C153[1][A]	test[3].u_mac_rx_model/shift_reg_pause_3_s1/CLK
1.476	0.025	tHld		1	R42C153[1][A]	test[3].u_mac_rx_model/shift_reg_pause_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.451, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.451, 100.000%

Path11

Path Summary:

Slack	0.275
Data Arrival Time	1.748
Data Required Time	1.473
From	test[3].u_mac_rx_model/pause_address_32_s1
To	test[3].u_mac_rx_model/pause_address_32_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.448	1.448	tNET	RR	1	R44C160[0][A]	test[3].u_mac_rx_model/pause_address_32_s1/CLK
1.589	0.141	tC2Q	RF	4	R44C160[0][A]	test[3].u_mac_rx_model/pause_address_32_s1/Q
1.595	0.006	tNET	FF	1	R44C160[0][A]	test[3].u_mac_rx_model/n1425_s0/I3
1.748	0.153	tINS	FF	1	R44C160[0][A]	test[3].u_mac_rx_model/n1425_s0/F
1.748	0.000	tNET	FF	1	R44C160[0][A]	test[3].u_mac_rx_model/pause_address_32_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.448	1.448	tNET	RR	1	R44C160[0][A]	test[3].u_mac_rx_model/pause_address_32_s1/CLK
1.473	0.025	tHld		1	R44C160[0][A]	test[3].u_mac_rx_model/pause_address_32_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.448, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.448, 100.000%

Path12

Path Summary:

Slack	0.275
Data Arrival Time	1.751
Data Required Time	1.476
From	test[3].u_mac_rx_model/shift_reg_1_s1
To	test[3].u_mac_rx_model/shift_reg_1_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.451	1.451	tNET	RR	1	R42C145[1][A]	test[3].u_mac_rx_model/shift_reg_1_s1/CLK
1.592	0.141	tC2Q	RF	2	R42C145[1][A]	test[3].u_mac_rx_model/shift_reg_1_s1/Q
1.598	0.006	tNET	FF	1	R42C145[1][A]	test[3].u_mac_rx_model/n886_s3/I0
1.751	0.153	tINS	FF	1	R42C145[1][A]	test[3].u_mac_rx_model/n886_s3/F
1.751	0.000	tNET	FF	1	R42C145[1][A]	test[3].u_mac_rx_model/shift_reg_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.451	1.451	tNET	RR	1	R42C145[1][A]	test[3].u_mac_rx_model/shift_reg_1_s1/CLK
1.476	0.025	tHld		1	R42C145[1][A]	test[3].u_mac_rx_model/shift_reg_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.451, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.451, 100.000%

Path13

Path Summary:

Slack	0.275
Data Arrival Time	1.744
Data Required Time	1.469
From	test[3].u_mac_rx_model/shift_reg_2_s1
To	test[3].u_mac_rx_model/shift_reg_2_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.444	1.444	tNET	RR	1	R44C147[1][A]	test[3].u_mac_rx_model/shift_reg_2_s1/CLK
1.585	0.141	tC2Q	RF	2	R44C147[1][A]	test[3].u_mac_rx_model/shift_reg_2_s1/Q
1.591	0.006	tNET	FF	1	R44C147[1][A]	test[3].u_mac_rx_model/n885_s3/I0
1.744	0.153	tINS	FF	1	R44C147[1][A]	test[3].u_mac_rx_model/n885_s3/F
1.744	0.000	tNET	FF	1	R44C147[1][A]	test[3].u_mac_rx_model/shift_reg_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.444	1.444	tNET	RR	1	R44C147[1][A]	test[3].u_mac_rx_model/shift_reg_2_s1/CLK
1.469	0.025	tHld		1	R44C147[1][A]	test[3].u_mac_rx_model/shift_reg_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.444, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.444, 100.000%

Path14

Path Summary:

Slack	0.275
Data Arrival Time	1.749
Data Required Time	1.474
From	test[3].u_mac_rx_model/shift_reg_5_s1
To	test[3].u_mac_rx_model/shift_reg_5_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.449	1.449	tNET	RR	1	R45C143[1][A]	test[3].u_mac_rx_model/shift_reg_5_s1/CLK
1.590	0.141	tC2Q	RF	2	R45C143[1][A]	test[3].u_mac_rx_model/shift_reg_5_s1/Q
1.596	0.006	tNET	FF	1	R45C143[1][A]	test[3].u_mac_rx_model/n882_s3/I0
1.749	0.153	tINS	FF	1	R45C143[1][A]	test[3].u_mac_rx_model/n882_s3/F
1.749	0.000	tNET	FF	1	R45C143[1][A]	test[3].u_mac_rx_model/shift_reg_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.449	1.449	tNET	RR	1	R45C143[1][A]	test[3].u_mac_rx_model/shift_reg_5_s1/CLK
1.474	0.025	tHld		1	R45C143[1][A]	test[3].u_mac_rx_model/shift_reg_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.449, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.449, 100.000%

Path15

Path Summary:

Slack	0.275
Data Arrival Time	1.740
Data Required Time	1.465
From	test[3].u_mac_rx_model/shift_reg_7_s1
To	test[3].u_mac_rx_model/shift_reg_7_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.440	1.440	tNET	RR	1	R44C146[1][A]	test[3].u_mac_rx_model/shift_reg_7_s1/CLK
1.581	0.141	tC2Q	RF	2	R44C146[1][A]	test[3].u_mac_rx_model/shift_reg_7_s1/Q
1.587	0.006	tNET	FF	1	R44C146[1][A]	test[3].u_mac_rx_model/n880_s3/I0
1.740	0.153	tINS	FF	1	R44C146[1][A]	test[3].u_mac_rx_model/n880_s3/F
1.740	0.000	tNET	FF	1	R44C146[1][A]	test[3].u_mac_rx_model/shift_reg_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.440	1.440	tNET	RR	1	R44C146[1][A]	test[3].u_mac_rx_model/shift_reg_7_s1/CLK
1.465	0.025	tHld		1	R44C146[1][A]	test[3].u_mac_rx_model/shift_reg_7_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.440, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.440, 100.000%

Path16

Path Summary:

Slack	0.275
Data Arrival Time	1.749
Data Required Time	1.474
From	test[3].u_mac_rx_model/shift_reg_12_s1
To	test[3].u_mac_rx_model/shift_reg_12_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.449	1.449	tNET	RR	1	R43C147[1][A]	test[3].u_mac_rx_model/shift_reg_12_s1/CLK
1.590	0.141	tC2Q	RF	2	R43C147[1][A]	test[3].u_mac_rx_model/shift_reg_12_s1/Q
1.596	0.006	tNET	FF	1	R43C147[1][A]	test[3].u_mac_rx_model/n875_s2/I0
1.749	0.153	tINS	FF	1	R43C147[1][A]	test[3].u_mac_rx_model/n875_s2/F
1.749	0.000	tNET	FF	1	R43C147[1][A]	test[3].u_mac_rx_model/shift_reg_12_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.449	1.449	tNET	RR	1	R43C147[1][A]	test[3].u_mac_rx_model/shift_reg_12_s1/CLK
1.474	0.025	tHld		1	R43C147[1][A]	test[3].u_mac_rx_model/shift_reg_12_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.449, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.449, 100.000%

Path17

Path Summary:

Slack	0.275
Data Arrival Time	1.739
Data Required Time	1.464
From	test[3].u_mac_rx_model/shift_reg_18_s1
To	test[3].u_mac_rx_model/shift_reg_18_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.439	1.439	tNET	RR	1	R45C145[1][A]	test[3].u_mac_rx_model/shift_reg_18_s1/CLK
1.580	0.141	tC2Q	RF	2	R45C145[1][A]	test[3].u_mac_rx_model/shift_reg_18_s1/Q
1.586	0.006	tNET	FF	1	R45C145[1][A]	test[3].u_mac_rx_model/n869_s1/I0
1.739	0.153	tINS	FF	1	R45C145[1][A]	test[3].u_mac_rx_model/n869_s1/F
1.739	0.000	tNET	FF	1	R45C145[1][A]	test[3].u_mac_rx_model/shift_reg_18_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.439	1.439	tNET	RR	1	R45C145[1][A]	test[3].u_mac_rx_model/shift_reg_18_s1/CLK
1.464	0.025	tHld		1	R45C145[1][A]	test[3].u_mac_rx_model/shift_reg_18_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.439, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.439, 100.000%

Path18

Path Summary:

Slack	0.275
Data Arrival Time	1.764
Data Required Time	1.489
From	test[3].u_mac_rx_model/shift_reg_19_s1
To	test[3].u_mac_rx_model/shift_reg_19_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.464	1.464	tNET	RR	1	R40C143[1][A]	test[3].u_mac_rx_model/shift_reg_19_s1/CLK
1.605	0.141	tC2Q	RF	2	R40C143[1][A]	test[3].u_mac_rx_model/shift_reg_19_s1/Q
1.611	0.006	tNET	FF	1	R40C143[1][A]	test[3].u_mac_rx_model/n868_s2/I0
1.764	0.153	tINS	FF	1	R40C143[1][A]	test[3].u_mac_rx_model/n868_s2/F
1.764	0.000	tNET	FF	1	R40C143[1][A]	test[3].u_mac_rx_model/shift_reg_19_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.464	1.464	tNET	RR	1	R40C143[1][A]	test[3].u_mac_rx_model/shift_reg_19_s1/CLK
1.489	0.025	tHld		1	R40C143[1][A]	test[3].u_mac_rx_model/shift_reg_19_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.464, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.464, 100.000%

Path19

Path Summary:

Slack	0.275
Data Arrival Time	1.749
Data Required Time	1.474
From	test[3].u_mac_rx_model/shift_reg_20_s1
To	test[3].u_mac_rx_model/shift_reg_20_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.449	1.449	tNET	RR	1	R43C147[0][A]	test[3].u_mac_rx_model/shift_reg_20_s1/CLK
1.590	0.141	tC2Q	RF	2	R43C147[0][A]	test[3].u_mac_rx_model/shift_reg_20_s1/Q
1.596	0.006	tNET	FF	1	R43C147[0][A]	test[3].u_mac_rx_model/n867_s2/I0
1.749	0.153	tINS	FF	1	R43C147[0][A]	test[3].u_mac_rx_model/n867_s2/F
1.749	0.000	tNET	FF	1	R43C147[0][A]	test[3].u_mac_rx_model/shift_reg_20_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.449	1.449	tNET	RR	1	R43C147[0][A]	test[3].u_mac_rx_model/shift_reg_20_s1/CLK
1.474	0.025	tHld		1	R43C147[0][A]	test[3].u_mac_rx_model/shift_reg_20_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.449, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.449, 100.000%

Path20

Path Summary:

Slack	0.275
Data Arrival Time	1.754
Data Required Time	1.479
From	test[3].u_mac_rx_model/shift_reg_24_s1
To	test[3].u_mac_rx_model/shift_reg_24_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.454	1.454	tNET	RR	1	R44C143[1][A]	test[3].u_mac_rx_model/shift_reg_24_s1/CLK
1.595	0.141	tC2Q	RF	2	R44C143[1][A]	test[3].u_mac_rx_model/shift_reg_24_s1/Q
1.601	0.006	tNET	FF	1	R44C143[1][A]	test[3].u_mac_rx_model/n863_s1/I0
1.754	0.153	tINS	FF	1	R44C143[1][A]	test[3].u_mac_rx_model/n863_s1/F
1.754	0.000	tNET	FF	1	R44C143[1][A]	test[3].u_mac_rx_model/shift_reg_24_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.454	1.454	tNET	RR	1	R44C143[1][A]	test[3].u_mac_rx_model/shift_reg_24_s1/CLK
1.479	0.025	tHld		1	R44C143[1][A]	test[3].u_mac_rx_model/shift_reg_24_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.454, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.454, 100.000%

Path21

Path Summary:

Slack	0.275
Data Arrival Time	1.735
Data Required Time	1.460
From	test[3].u_mac_rx_model/shift_reg_42_s1
To	test[3].u_mac_rx_model/shift_reg_42_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.435	1.435	tNET	RR	1	R45C146[0][A]	test[3].u_mac_rx_model/shift_reg_42_s1/CLK
1.576	0.141	tC2Q	RF	2	R45C146[0][A]	test[3].u_mac_rx_model/shift_reg_42_s1/Q
1.582	0.006	tNET	FF	1	R45C146[0][A]	test[3].u_mac_rx_model/n845_s1/I0
1.735	0.153	tINS	FF	1	R45C146[0][A]	test[3].u_mac_rx_model/n845_s1/F
1.735	0.000	tNET	FF	1	R45C146[0][A]	test[3].u_mac_rx_model/shift_reg_42_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.435	1.435	tNET	RR	1	R45C146[0][A]	test[3].u_mac_rx_model/shift_reg_42_s1/CLK
1.460	0.025	tHld		1	R45C146[0][A]	test[3].u_mac_rx_model/shift_reg_42_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.435, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.435, 100.000%

Path22

Path Summary:

Slack	0.275
Data Arrival Time	1.749
Data Required Time	1.474
From	test[3].u_mac_rx_model/shift_reg_49_s1
To	test[3].u_mac_rx_model/shift_reg_49_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.449	1.449	tNET	RR	1	R43C145[1][A]	test[3].u_mac_rx_model/shift_reg_49_s1/CLK
1.590	0.141	tC2Q	RF	2	R43C145[1][A]	test[3].u_mac_rx_model/shift_reg_49_s1/Q
1.596	0.006	tNET	FF	1	R43C145[1][A]	test[3].u_mac_rx_model/n838_s2/I0
1.749	0.153	tINS	FF	1	R43C145[1][A]	test[3].u_mac_rx_model/n838_s2/F
1.749	0.000	tNET	FF	1	R43C145[1][A]	test[3].u_mac_rx_model/shift_reg_49_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.449	1.449	tNET	RR	1	R43C145[1][A]	test[3].u_mac_rx_model/shift_reg_49_s1/CLK
1.474	0.025	tHld		1	R43C145[1][A]	test[3].u_mac_rx_model/shift_reg_49_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.449, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.449, 100.000%

Path23

Path Summary:

Slack	0.275
Data Arrival Time	1.766
Data Required Time	1.491
From	test[3].u_mac_rx_model/shift_reg_51_s1
To	test[3].u_mac_rx_model/shift_reg_51_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.466	1.466	tNET	RR	1	R39C143[0][A]	test[3].u_mac_rx_model/shift_reg_51_s1/CLK
1.607	0.141	tC2Q	RF	2	R39C143[0][A]	test[3].u_mac_rx_model/shift_reg_51_s1/Q
1.613	0.006	tNET	FF	1	R39C143[0][A]	test[3].u_mac_rx_model/n836_s1/I0
1.766	0.153	tINS	FF	1	R39C143[0][A]	test[3].u_mac_rx_model/n836_s1/F
1.766	0.000	tNET	FF	1	R39C143[0][A]	test[3].u_mac_rx_model/shift_reg_51_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.466	1.466	tNET	RR	1	R39C143[0][A]	test[3].u_mac_rx_model/shift_reg_51_s1/CLK
1.491	0.025	tHld		1	R39C143[0][A]	test[3].u_mac_rx_model/shift_reg_51_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.466, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.466, 100.000%

Path24

Path Summary:

Slack	0.275
Data Arrival Time	1.745
Data Required Time	1.470
From	test[3].u_mac_rx_model/shift_reg_53_s1
To	test[3].u_mac_rx_model/shift_reg_53_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.445	1.445	tNET	RR	1	R45C142[1][A]	test[3].u_mac_rx_model/shift_reg_53_s1/CLK
1.586	0.141	tC2Q	RF	2	R45C142[1][A]	test[3].u_mac_rx_model/shift_reg_53_s1/Q
1.592	0.006	tNET	FF	1	R45C142[1][A]	test[3].u_mac_rx_model/n834_s2/I0
1.745	0.153	tINS	FF	1	R45C142[1][A]	test[3].u_mac_rx_model/n834_s2/F
1.745	0.000	tNET	FF	1	R45C142[1][A]	test[3].u_mac_rx_model/shift_reg_53_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.445	1.445	tNET	RR	1	R45C142[1][A]	test[3].u_mac_rx_model/shift_reg_53_s1/CLK
1.470	0.025	tHld		1	R45C142[1][A]	test[3].u_mac_rx_model/shift_reg_53_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.445, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.445, 100.000%

Path25

Path Summary:

Slack	0.275
Data Arrival Time	1.745
Data Required Time	1.470
From	test[3].u_mac_rx_model/shift_reg_60_s1
To	test[3].u_mac_rx_model/shift_reg_60_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.445	1.445	tNET	RR	1	R43C146[1][A]	test[3].u_mac_rx_model/shift_reg_60_s1/CLK
1.586	0.141	tC2Q	RF	2	R43C146[1][A]	test[3].u_mac_rx_model/shift_reg_60_s1/Q
1.592	0.006	tNET	FF	1	R43C146[1][A]	test[3].u_mac_rx_model/n827_s2/I0
1.745	0.153	tINS	FF	1	R43C146[1][A]	test[3].u_mac_rx_model/n827_s2/F
1.745	0.000	tNET	FF	1	R43C146[1][A]	test[3].u_mac_rx_model/shift_reg_60_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.445	1.445	tNET	RR	1	R43C146[1][A]	test[3].u_mac_rx_model/shift_reg_60_s1/CLK
1.470	0.025	tHld		1	R43C146[1][A]	test[3].u_mac_rx_model/shift_reg_60_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.445, 100.000%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.445, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.945
Data Arrival Time	10.516
Data Required Time	11.461
From	rx_mac_rst_n_3_s0
To	test[3].u_mac_rx_model/rx_error_all_pause_check_s4
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.840	3.840	tNET	RR	1	R44C169[0][A]	rx_mac_rst_n_3_s0/CLK
4.207	0.368	tC2Q	RF	790	R44C169[0][A]	rx_mac_rst_n_3_s0/Q
10.516	6.309	tNET	FF	1	R29C158[1][B]	test[3].u_mac_rx_model/rx_error_all_pause_check_s4/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rx_mac_clk
8.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.809	3.809	tNET	RR	1	R29C158[1][B]	test[3].u_mac_rx_model/rx_error_all_pause_check_s4/CLK
11.461	-0.347	tSu		1	R29C158[1][B]	test[3].u_mac_rx_model/rx_error_all_pause_check_s4

Path Statistics:

Clock Skew	-0.031
Setup Relationship	8.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.840, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 6.309, 94.495%; tC2Q: 0.368, 5.505%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.809, 100.000%

Path2

Path Summary:

Slack	1.194
Data Arrival Time	10.260
Data Required Time	11.454
From	rx_mac_rst_n_3_s0
To	test[3].u_mac_rx_model/rx_error_all_data_check_s4
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.840	3.840	tNET	RR	1	R44C169[0][A]	rx_mac_rst_n_3_s0/CLK
4.207	0.368	tC2Q	RF	790	R44C169[0][A]	rx_mac_rst_n_3_s0/Q
10.260	6.053	tNET	FF	1	R30C159[2][B]	test[3].u_mac_rx_model/rx_error_all_data_check_s4/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rx_mac_clk
8.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.802	3.802	tNET	RR	1	R30C159[2][B]	test[3].u_mac_rx_model/rx_error_all_data_check_s4/CLK
11.454	-0.347	tSu		1	R30C159[2][B]	test[3].u_mac_rx_model/rx_error_all_data_check_s4

Path Statistics:

Clock Skew	-0.038
Setup Relationship	8.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.840, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 6.053, 94.276%; tC2Q: 0.368, 5.724%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.802, 100.000%

Path3

Path Summary:

Slack	1.225
Data Arrival Time	10.277
Data Required Time	11.502
From	rx_mac_rst_n_3_s0
To	test[3].u_mac_rx_model/pause_address_35_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.840	3.840	tNET	RR	1	R44C169[0][A]	rx_mac_rst_n_3_s0/CLK
4.207	0.368	tC2Q	RF	790	R44C169[0][A]	rx_mac_rst_n_3_s0/Q
10.277	6.070	tNET	FF	1	R42C165[1][B]	test[3].u_mac_rx_model/pause_address_35_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rx_mac_clk
8.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.849	3.849	tNET	RR	1	R42C165[1][B]	test[3].u_mac_rx_model/pause_address_35_s1/CLK
11.502	-0.347	tSu		1	R42C165[1][B]	test[3].u_mac_rx_model/pause_address_35_s1

Path Statistics:

Clock Skew	0.010
Setup Relationship	8.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.840, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 6.070, 94.291%; tC2Q: 0.368, 5.709%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.849, 100.000%

Path4

Path Summary:

Slack	1.225
Data Arrival Time	10.277
Data Required Time	11.502
From	rx_mac_rst_n_3_s0
To	test[3].u_mac_rx_model/pause_address_42_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.840	3.840	tNET	RR	1	R44C169[0][A]	rx_mac_rst_n_3_s0/CLK
4.207	0.368	tC2Q	RF	790	R44C169[0][A]	rx_mac_rst_n_3_s0/Q
10.277	6.070	tNET	FF	1	R42C165[2][A]	test[3].u_mac_rx_model/pause_address_42_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rx_mac_clk
8.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.849	3.849	tNET	RR	1	R42C165[2][A]	test[3].u_mac_rx_model/pause_address_42_s1/CLK
11.502	-0.347	tSu		1	R42C165[2][A]	test[3].u_mac_rx_model/pause_address_42_s1

Path Statistics:

Clock Skew	0.010
Setup Relationship	8.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.840, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 6.070, 94.291%; tC2Q: 0.368, 5.709%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.849, 100.000%

Path5

Path Summary:

Slack	1.225
Data Arrival Time	10.277
Data Required Time	11.502
From	rx_mac_rst_n_3_s0
To	test[3].u_mac_rx_model/pause_address_43_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.840	3.840	tNET	RR	1	R44C169[0][A]	rx_mac_rst_n_3_s0/CLK
4.207	0.368	tC2Q	RF	790	R44C169[0][A]	rx_mac_rst_n_3_s0/Q
10.277	6.070	tNET	FF	1	R42C165[1][A]	test[3].u_mac_rx_model/pause_address_43_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rx_mac_clk
8.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.849	3.849	tNET	RR	1	R42C165[1][A]	test[3].u_mac_rx_model/pause_address_43_s1/CLK
11.502	-0.347	tSu		1	R42C165[1][A]	test[3].u_mac_rx_model/pause_address_43_s1

Path Statistics:

Clock Skew	0.010
Setup Relationship	8.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.840, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 6.070, 94.291%; tC2Q: 0.368, 5.709%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.849, 100.000%

Path6

Path Summary:

Slack	1.225
Data Arrival Time	10.277
Data Required Time	11.502
From	rx_mac_rst_n_3_s0
To	test[3].u_mac_rx_model/pause_address_44_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.840	3.840	tNET	RR	1	R44C169[0][A]	rx_mac_rst_n_3_s0/CLK
4.207	0.368	tC2Q	RF	790	R44C169[0][A]	rx_mac_rst_n_3_s0/Q
10.277	6.070	tNET	FF	1	R42C165[0][B]	test[3].u_mac_rx_model/pause_address_44_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rx_mac_clk
8.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.849	3.849	tNET	RR	1	R42C165[0][B]	test[3].u_mac_rx_model/pause_address_44_s1/CLK
11.502	-0.347	tSu		1	R42C165[0][B]	test[3].u_mac_rx_model/pause_address_44_s1

Path Statistics:

Clock Skew	0.010
Setup Relationship	8.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.840, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 6.070, 94.291%; tC2Q: 0.368, 5.709%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.849, 100.000%

Path7

Path Summary:

Slack	1.234
Data Arrival Time	10.277
Data Required Time	11.511
From	rx_mac_rst_n_3_s0
To	test[3].u_mac_rx_model/shift_reg_pause_57_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.840	3.840	tNET	RR	1	R44C169[0][A]	rx_mac_rst_n_3_s0/CLK
4.207	0.368	tC2Q	RF	790	R44C169[0][A]	rx_mac_rst_n_3_s0/Q
10.277	6.070	tNET	FF	1	R42C164[0][A]	test[3].u_mac_rx_model/shift_reg_pause_57_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rx_mac_clk
8.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.859	3.859	tNET	RR	1	R42C164[0][A]	test[3].u_mac_rx_model/shift_reg_pause_57_s1/CLK
11.511	-0.347	tSu		1	R42C164[0][A]	test[3].u_mac_rx_model/shift_reg_pause_57_s1

Path Statistics:

Clock Skew	0.019
Setup Relationship	8.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.840, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 6.070, 94.291%; tC2Q: 0.368, 5.709%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.859, 100.000%

Path8

Path Summary:

Slack	1.234
Data Arrival Time	10.277
Data Required Time	11.511
From	rx_mac_rst_n_3_s0
To	test[3].u_mac_rx_model/pause_data_2_5_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.840	3.840	tNET	RR	1	R44C169[0][A]	rx_mac_rst_n_3_s0/CLK
4.207	0.368	tC2Q	RF	790	R44C169[0][A]	rx_mac_rst_n_3_s0/Q
10.277	6.070	tNET	FF	1	R42C164[3][A]	test[3].u_mac_rx_model/pause_data_2_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rx_mac_clk
8.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.859	3.859	tNET	RR	1	R42C164[3][A]	test[3].u_mac_rx_model/pause_data_2_5_s1/CLK
11.511	-0.347	tSu		1	R42C164[3][A]	test[3].u_mac_rx_model/pause_data_2_5_s1

Path Statistics:

Clock Skew	0.019
Setup Relationship	8.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.840, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 6.070, 94.291%; tC2Q: 0.368, 5.709%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.859, 100.000%

Path9

Path Summary:

Slack	1.234
Data Arrival Time	10.277
Data Required Time	11.511
From	rx_mac_rst_n_3_s0
To	test[3].u_mac_rx_model/pause_data_2_9_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.840	3.840	tNET	RR	1	R44C169[0][A]	rx_mac_rst_n_3_s0/CLK
4.207	0.368	tC2Q	RF	790	R44C169[0][A]	rx_mac_rst_n_3_s0/Q
10.277	6.070	tNET	FF	1	R42C164[1][A]	test[3].u_mac_rx_model/pause_data_2_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rx_mac_clk
8.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.859	3.859	tNET	RR	1	R42C164[1][A]	test[3].u_mac_rx_model/pause_data_2_9_s1/CLK
11.511	-0.347	tSu		1	R42C164[1][A]	test[3].u_mac_rx_model/pause_data_2_9_s1

Path Statistics:

Clock Skew	0.019
Setup Relationship	8.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.840, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 6.070, 94.291%; tC2Q: 0.368, 5.709%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.859, 100.000%

Path10

Path Summary:

Slack	1.234
Data Arrival Time	10.277
Data Required Time	11.511
From	rx_mac_rst_n_3_s0
To	test[3].u_mac_rx_model/pause_data_2_12_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.840	3.840	tNET	RR	1	R44C169[0][A]	rx_mac_rst_n_3_s0/CLK
4.207	0.368	tC2Q	RF	790	R44C169[0][A]	rx_mac_rst_n_3_s0/Q
10.277	6.070	tNET	FF	1	R42C164[0][B]	test[3].u_mac_rx_model/pause_data_2_12_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rx_mac_clk
8.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.859	3.859	tNET	RR	1	R42C164[0][B]	test[3].u_mac_rx_model/pause_data_2_12_s1/CLK
11.511	-0.347	tSu		1	R42C164[0][B]	test[3].u_mac_rx_model/pause_data_2_12_s1

Path Statistics:

Clock Skew	0.019
Setup Relationship	8.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.840, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 6.070, 94.291%; tC2Q: 0.368, 5.709%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.859, 100.000%

Path11

Path Summary:

Slack	1.234
Data Arrival Time	10.277
Data Required Time	11.511
From	rx_mac_rst_n_3_s0
To	test[3].u_mac_rx_model/pause_data_2_13_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.840	3.840	tNET	RR	1	R44C169[0][A]	rx_mac_rst_n_3_s0/CLK
4.207	0.368	tC2Q	RF	790	R44C169[0][A]	rx_mac_rst_n_3_s0/Q
10.277	6.070	tNET	FF	1	R42C164[3][B]	test[3].u_mac_rx_model/pause_data_2_13_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rx_mac_clk
8.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.859	3.859	tNET	RR	1	R42C164[3][B]	test[3].u_mac_rx_model/pause_data_2_13_s1/CLK
11.511	-0.347	tSu		1	R42C164[3][B]	test[3].u_mac_rx_model/pause_data_2_13_s1

Path Statistics:

Clock Skew	0.019
Setup Relationship	8.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.840, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 6.070, 94.291%; tC2Q: 0.368, 5.709%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.859, 100.000%

Path12

Path Summary:

Slack	1.298
Data Arrival Time	10.221
Data Required Time	11.519
From	rx_mac_rst_n_3_s0
To	test[3].u_mac_rx_model/shift_reg_pause_31_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.840	3.840	tNET	RR	1	R44C169[0][A]	rx_mac_rst_n_3_s0/CLK
4.207	0.368	tC2Q	RF	790	R44C169[0][A]	rx_mac_rst_n_3_s0/Q
10.221	6.014	tNET	FF	1	R39C164[1][B]	test[3].u_mac_rx_model/shift_reg_pause_31_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rx_mac_clk
8.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.866	3.866	tNET	RR	1	R39C164[1][B]	test[3].u_mac_rx_model/shift_reg_pause_31_s1/CLK
11.519	-0.347	tSu		1	R39C164[1][B]	test[3].u_mac_rx_model/shift_reg_pause_31_s1

Path Statistics:

Clock Skew	0.027
Setup Relationship	8.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.840, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 6.014, 94.241%; tC2Q: 0.368, 5.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.866, 100.000%

Path13

Path Summary:

Slack	1.298
Data Arrival Time	10.221
Data Required Time	11.519
From	rx_mac_rst_n_3_s0
To	test[3].u_mac_rx_model/shift_reg_pause_39_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.840	3.840	tNET	RR	1	R44C169[0][A]	rx_mac_rst_n_3_s0/CLK
4.207	0.368	tC2Q	RF	790	R44C169[0][A]	rx_mac_rst_n_3_s0/Q
10.221	6.014	tNET	FF	1	R39C164[1][A]	test[3].u_mac_rx_model/shift_reg_pause_39_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rx_mac_clk
8.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.866	3.866	tNET	RR	1	R39C164[1][A]	test[3].u_mac_rx_model/shift_reg_pause_39_s1/CLK
11.519	-0.347	tSu		1	R39C164[1][A]	test[3].u_mac_rx_model/shift_reg_pause_39_s1

Path Statistics:

Clock Skew	0.027
Setup Relationship	8.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.840, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 6.014, 94.241%; tC2Q: 0.368, 5.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.866, 100.000%

Path14

Path Summary:

Slack	1.298
Data Arrival Time	10.221
Data Required Time	11.519
From	rx_mac_rst_n_3_s0
To	test[3].u_mac_rx_model/shift_reg_pause_47_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.840	3.840	tNET	RR	1	R44C169[0][A]	rx_mac_rst_n_3_s0/CLK
4.207	0.368	tC2Q	RF	790	R44C169[0][A]	rx_mac_rst_n_3_s0/Q
10.221	6.014	tNET	FF	1	R39C164[0][B]	test[3].u_mac_rx_model/shift_reg_pause_47_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rx_mac_clk
8.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.866	3.866	tNET	RR	1	R39C164[0][B]	test[3].u_mac_rx_model/shift_reg_pause_47_s1/CLK
11.519	-0.347	tSu		1	R39C164[0][B]	test[3].u_mac_rx_model/shift_reg_pause_47_s1

Path Statistics:

Clock Skew	0.027
Setup Relationship	8.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.840, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 6.014, 94.241%; tC2Q: 0.368, 5.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.866, 100.000%

Path15

Path Summary:

Slack	1.298
Data Arrival Time	10.221
Data Required Time	11.519
From	rx_mac_rst_n_3_s0
To	test[3].u_mac_rx_model/pause_data_3_47_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.840	3.840	tNET	RR	1	R44C169[0][A]	rx_mac_rst_n_3_s0/CLK
4.207	0.368	tC2Q	RF	790	R44C169[0][A]	rx_mac_rst_n_3_s0/Q
10.221	6.014	tNET	FF	1	R39C164[0][A]	test[3].u_mac_rx_model/pause_data_3_47_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rx_mac_clk
8.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.866	3.866	tNET	RR	1	R39C164[0][A]	test[3].u_mac_rx_model/pause_data_3_47_s1/CLK
11.519	-0.347	tSu		1	R39C164[0][A]	test[3].u_mac_rx_model/pause_data_3_47_s1

Path Statistics:

Clock Skew	0.027
Setup Relationship	8.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.840, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 6.014, 94.241%; tC2Q: 0.368, 5.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.866, 100.000%

Path16

Path Summary:

Slack	1.300
Data Arrival Time	10.221
Data Required Time	11.521
From	rx_mac_rst_n_3_s0
To	cycle_one_time_3_s0
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.840	3.840	tNET	RR	1	R44C169[0][A]	rx_mac_rst_n_3_s0/CLK
4.207	0.368	tC2Q	RF	790	R44C169[0][A]	rx_mac_rst_n_3_s0/Q
10.221	6.014	tNET	FF	1	R38C164[0][B]	cycle_one_time_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rx_mac_clk
8.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.869	3.869	tNET	RR	1	R38C164[0][B]	cycle_one_time_3_s0/CLK
11.521	-0.347	tSu		1	R38C164[0][B]	cycle_one_time_3_s0

Path Statistics:

Clock Skew	0.029
Setup Relationship	8.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.840, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 6.014, 94.241%; tC2Q: 0.368, 5.759%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.869, 100.000%

Path17

Path Summary:

Slack	1.302
Data Arrival Time	10.212
Data Required Time	11.514
From	rx_mac_rst_n_3_s0
To	test[3].u_mac_rx_model/pause_data_2_0_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.840	3.840	tNET	RR	1	R44C169[0][A]	rx_mac_rst_n_3_s0/CLK
4.207	0.368	tC2Q	RF	790	R44C169[0][A]	rx_mac_rst_n_3_s0/Q
10.212	6.005	tNET	FF	1	R41C164[1][A]	test[3].u_mac_rx_model/pause_data_2_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rx_mac_clk
8.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.861	3.861	tNET	RR	1	R41C164[1][A]	test[3].u_mac_rx_model/pause_data_2_0_s1/CLK
11.514	-0.347	tSu		1	R41C164[1][A]	test[3].u_mac_rx_model/pause_data_2_0_s1

Path Statistics:

Clock Skew	0.022
Setup Relationship	8.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.840, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 6.005, 94.233%; tC2Q: 0.368, 5.767%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.861, 100.000%

Path18

Path Summary:

Slack	1.302
Data Arrival Time	10.212
Data Required Time	11.514
From	rx_mac_rst_n_3_s0
To	test[3].u_mac_rx_model/pause_data_2_4_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.840	3.840	tNET	RR	1	R44C169[0][A]	rx_mac_rst_n_3_s0/CLK
4.207	0.368	tC2Q	RF	790	R44C169[0][A]	rx_mac_rst_n_3_s0/Q
10.212	6.005	tNET	FF	1	R41C164[1][B]	test[3].u_mac_rx_model/pause_data_2_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rx_mac_clk
8.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.861	3.861	tNET	RR	1	R41C164[1][B]	test[3].u_mac_rx_model/pause_data_2_4_s1/CLK
11.514	-0.347	tSu		1	R41C164[1][B]	test[3].u_mac_rx_model/pause_data_2_4_s1

Path Statistics:

Clock Skew	0.022
Setup Relationship	8.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.840, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 6.005, 94.233%; tC2Q: 0.368, 5.767%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.861, 100.000%

Path19

Path Summary:

Slack	1.302
Data Arrival Time	10.212
Data Required Time	11.514
From	rx_mac_rst_n_3_s0
To	test[3].u_mac_rx_model/rx_running_s0
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.840	3.840	tNET	RR	1	R44C169[0][A]	rx_mac_rst_n_3_s0/CLK
4.207	0.368	tC2Q	RF	790	R44C169[0][A]	rx_mac_rst_n_3_s0/Q
10.212	6.005	tNET	FF	1	R41C164[0][A]	test[3].u_mac_rx_model/rx_running_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rx_mac_clk
8.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.861	3.861	tNET	RR	1	R41C164[0][A]	test[3].u_mac_rx_model/rx_running_s0/CLK
11.514	-0.347	tSu		1	R41C164[0][A]	test[3].u_mac_rx_model/rx_running_s0

Path Statistics:

Clock Skew	0.022
Setup Relationship	8.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.840, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 6.005, 94.233%; tC2Q: 0.368, 5.767%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.861, 100.000%

Path20

Path Summary:

Slack	1.430
Data Arrival Time	10.075
Data Required Time	11.504
From	rx_mac_rst_n_3_s0
To	test[3].u_mac_rx_model/shift_reg_pause_51_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.840	3.840	tNET	RR	1	R44C169[0][A]	rx_mac_rst_n_3_s0/CLK
4.207	0.368	tC2Q	RF	790	R44C169[0][A]	rx_mac_rst_n_3_s0/Q
10.075	5.868	tNET	FF	1	R41C163[0][A]	test[3].u_mac_rx_model/shift_reg_pause_51_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rx_mac_clk
8.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.852	3.852	tNET	RR	1	R41C163[0][A]	test[3].u_mac_rx_model/shift_reg_pause_51_s1/CLK
11.504	-0.347	tSu		1	R41C163[0][A]	test[3].u_mac_rx_model/shift_reg_pause_51_s1

Path Statistics:

Clock Skew	0.012
Setup Relationship	8.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.840, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 5.868, 94.106%; tC2Q: 0.368, 5.894%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.852, 100.000%

Path21

Path Summary:

Slack	1.430
Data Arrival Time	10.075
Data Required Time	11.504
From	rx_mac_rst_n_3_s0
To	test[3].u_mac_rx_model/shift_reg_pause_53_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.840	3.840	tNET	RR	1	R44C169[0][A]	rx_mac_rst_n_3_s0/CLK
4.207	0.368	tC2Q	RF	790	R44C169[0][A]	rx_mac_rst_n_3_s0/Q
10.075	5.868	tNET	FF	1	R41C163[0][B]	test[3].u_mac_rx_model/shift_reg_pause_53_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rx_mac_clk
8.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.852	3.852	tNET	RR	1	R41C163[0][B]	test[3].u_mac_rx_model/shift_reg_pause_53_s1/CLK
11.504	-0.347	tSu		1	R41C163[0][B]	test[3].u_mac_rx_model/shift_reg_pause_53_s1

Path Statistics:

Clock Skew	0.012
Setup Relationship	8.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.840, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 5.868, 94.106%; tC2Q: 0.368, 5.894%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.852, 100.000%

Path22

Path Summary:

Slack	1.430
Data Arrival Time	10.075
Data Required Time	11.504
From	rx_mac_rst_n_3_s0
To	test[3].u_mac_rx_model/shift_reg_pause_61_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.840	3.840	tNET	RR	1	R44C169[0][A]	rx_mac_rst_n_3_s0/CLK
4.207	0.368	tC2Q	RF	790	R44C169[0][A]	rx_mac_rst_n_3_s0/Q
10.075	5.868	tNET	FF	1	R41C163[1][B]	test[3].u_mac_rx_model/shift_reg_pause_61_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rx_mac_clk
8.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.852	3.852	tNET	RR	1	R41C163[1][B]	test[3].u_mac_rx_model/shift_reg_pause_61_s1/CLK
11.504	-0.347	tSu		1	R41C163[1][B]	test[3].u_mac_rx_model/shift_reg_pause_61_s1

Path Statistics:

Clock Skew	0.012
Setup Relationship	8.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.840, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 5.868, 94.106%; tC2Q: 0.368, 5.894%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.852, 100.000%

Path23

Path Summary:

Slack	1.430
Data Arrival Time	10.075
Data Required Time	11.504
From	rx_mac_rst_n_3_s0
To	test[3].u_mac_rx_model/pause_data_2_3_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.840	3.840	tNET	RR	1	R44C169[0][A]	rx_mac_rst_n_3_s0/CLK
4.207	0.368	tC2Q	RF	790	R44C169[0][A]	rx_mac_rst_n_3_s0/Q
10.075	5.868	tNET	FF	1	R41C163[2][B]	test[3].u_mac_rx_model/pause_data_2_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rx_mac_clk
8.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.852	3.852	tNET	RR	1	R41C163[2][B]	test[3].u_mac_rx_model/pause_data_2_3_s1/CLK
11.504	-0.347	tSu		1	R41C163[2][B]	test[3].u_mac_rx_model/pause_data_2_3_s1

Path Statistics:

Clock Skew	0.012
Setup Relationship	8.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.840, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 5.868, 94.106%; tC2Q: 0.368, 5.894%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.852, 100.000%

Path24

Path Summary:

Slack	1.442
Data Arrival Time	10.057
Data Required Time	11.499
From	rx_mac_rst_n_3_s0
To	test[3].u_mac_rx_model/pause_data_2_14_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.840	3.840	tNET	RR	1	R44C169[0][A]	rx_mac_rst_n_3_s0/CLK
4.207	0.368	tC2Q	RF	790	R44C169[0][A]	rx_mac_rst_n_3_s0/Q
10.057	5.850	tNET	FF	1	R43C165[0][B]	test[3].u_mac_rx_model/pause_data_2_14_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rx_mac_clk
8.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.847	3.847	tNET	RR	1	R43C165[0][B]	test[3].u_mac_rx_model/pause_data_2_14_s1/CLK
11.499	-0.347	tSu		1	R43C165[0][B]	test[3].u_mac_rx_model/pause_data_2_14_s1

Path Statistics:

Clock Skew	0.007
Setup Relationship	8.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.840, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 5.850, 94.089%; tC2Q: 0.368, 5.911%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.847, 100.000%

Path25

Path Summary:

Slack	1.467
Data Arrival Time	10.025
Data Required Time	11.492
From	rx_mac_rst_n_3_s0
To	test[3].u_mac_rx_model/pause_data_2_7_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.840	3.840	tNET	RR	1	R44C169[0][A]	rx_mac_rst_n_3_s0/CLK
4.207	0.368	tC2Q	RF	790	R44C169[0][A]	rx_mac_rst_n_3_s0/Q
10.025	5.818	tNET	FF	1	R44C165[0][A]	test[3].u_mac_rx_model/pause_data_2_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
8.000	8.000					active clock edge time
8.000	0.000					rx_mac_clk
8.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
11.840	3.840	tNET	RR	1	R44C165[0][A]	test[3].u_mac_rx_model/pause_data_2_7_s1/CLK
11.492	-0.347	tSu		1	R44C165[0][A]	test[3].u_mac_rx_model/pause_data_2_7_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	8.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 3.840, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 5.818, 94.058%; tC2Q: 0.368, 5.942%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 3.840, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.386
Data Arrival Time	1.782
Data Required Time	1.396
From	rx_mac_rst_n_3_s0
To	cycle_all_time_3_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.444	1.444	tNET	RR	1	R44C169[0][A]	rx_mac_rst_n_3_s0/CLK
1.588	0.144	tC2Q	RR	790	R44C169[0][A]	rx_mac_rst_n_3_s0/Q
1.782	0.194	tNET	RR	1	R43C169[2][A]	cycle_all_time_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.449	1.449	tNET	RR	1	R43C169[2][A]	cycle_all_time_3_s1/CLK
1.396	-0.053	tHld		1	R43C169[2][A]	cycle_all_time_3_s1

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.444, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.194, 57.396%; tC2Q: 0.144, 42.604%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.449, 100.000%

Path2

Path Summary:

Slack	0.386
Data Arrival Time	1.782
Data Required Time	1.396
From	rx_mac_rst_n_3_s0
To	rx_running_d1_3_s0
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.444	1.444	tNET	RR	1	R44C169[0][A]	rx_mac_rst_n_3_s0/CLK
1.588	0.144	tC2Q	RR	790	R44C169[0][A]	rx_mac_rst_n_3_s0/Q
1.782	0.194	tNET	RR	1	R43C169[1][B]	rx_running_d1_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.449	1.449	tNET	RR	1	R43C169[1][B]	rx_running_d1_3_s0/CLK
1.396	-0.053	tHld		1	R43C169[1][B]	rx_running_d1_3_s0

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.444, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.194, 57.396%; tC2Q: 0.144, 42.604%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.449, 100.000%

Path3

Path Summary:

Slack	0.393
Data Arrival Time	1.794
Data Required Time	1.401
From	rx_mac_rst_n_1_s0
To	test[1].u_mac_rx_model/rx_running_s0
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.454	1.454	tNET	RR	1	R40C169[0][A]	rx_mac_rst_n_1_s0/CLK
1.598	0.144	tC2Q	RR	790	R40C169[0][A]	rx_mac_rst_n_1_s0/Q
1.794	0.196	tNET	RR	1	R40C167[1][A]	test[1].u_mac_rx_model/rx_running_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.454	1.454	tNET	RR	1	R40C167[1][A]	test[1].u_mac_rx_model/rx_running_s0/CLK
1.401	-0.053	tHld		1	R40C167[1][A]	test[1].u_mac_rx_model/rx_running_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.454, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.196, 57.647%; tC2Q: 0.144, 42.353%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.454, 100.000%

Path4

Path Summary:

Slack	0.393
Data Arrival Time	1.794
Data Required Time	1.401
From	rx_mac_rst_n_1_s0
To	cycle_all_time_1_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.454	1.454	tNET	RR	1	R40C169[0][A]	rx_mac_rst_n_1_s0/CLK
1.598	0.144	tC2Q	RR	790	R40C169[0][A]	rx_mac_rst_n_1_s0/Q
1.794	0.196	tNET	RR	1	R40C167[2][A]	cycle_all_time_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.454	1.454	tNET	RR	1	R40C167[2][A]	cycle_all_time_1_s1/CLK
1.401	-0.053	tHld		1	R40C167[2][A]	cycle_all_time_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.454, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.196, 57.647%; tC2Q: 0.144, 42.353%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.454, 100.000%

Path5

Path Summary:

Slack	0.393
Data Arrival Time	1.794
Data Required Time	1.401
From	rx_mac_rst_n_1_s0
To	rx_running_d1_1_s0
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.454	1.454	tNET	RR	1	R40C169[0][A]	rx_mac_rst_n_1_s0/CLK
1.598	0.144	tC2Q	RR	790	R40C169[0][A]	rx_mac_rst_n_1_s0/Q
1.794	0.196	tNET	RR	1	R40C167[0][B]	rx_running_d1_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.454	1.454	tNET	RR	1	R40C167[0][B]	rx_running_d1_1_s0/CLK
1.401	-0.053	tHld		1	R40C167[0][B]	rx_running_d1_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.454, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.196, 57.647%; tC2Q: 0.144, 42.353%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.454, 100.000%

Path6

Path Summary:

Slack	0.425
Data Arrival Time	1.834
Data Required Time	1.409
From	rx_mac_rst_n_0_s0
To	test[0].u_mac_rx_model/rx_running_s0
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.456	1.456	tNET	RR	1	R39C167[0][A]	rx_mac_rst_n_0_s0/CLK
1.600	0.144	tC2Q	RR	790	R39C167[0][A]	rx_mac_rst_n_0_s0/Q
1.834	0.234	tNET	RR	1	R38C164[1][B]	test[0].u_mac_rx_model/rx_running_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.462	1.462	tNET	RR	1	R38C164[1][B]	test[0].u_mac_rx_model/rx_running_s0/CLK
1.409	-0.053	tHld		1	R38C164[1][B]	test[0].u_mac_rx_model/rx_running_s0

Path Statistics:

Clock Skew	0.006
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.456, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.234, 61.905%; tC2Q: 0.144, 38.095%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.462, 100.000%

Path7

Path Summary:

Slack	0.425
Data Arrival Time	1.834
Data Required Time	1.409
From	rx_mac_rst_n_0_s0
To	rx_running_d1_0_s0
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.456	1.456	tNET	RR	1	R39C167[0][A]	rx_mac_rst_n_0_s0/CLK
1.600	0.144	tC2Q	RR	790	R39C167[0][A]	rx_mac_rst_n_0_s0/Q
1.834	0.234	tNET	RR	1	R38C164[1][A]	rx_running_d1_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.462	1.462	tNET	RR	1	R38C164[1][A]	rx_running_d1_0_s0/CLK
1.409	-0.053	tHld		1	R38C164[1][A]	rx_running_d1_0_s0

Path Statistics:

Clock Skew	0.006
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.456, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.234, 61.905%; tC2Q: 0.144, 38.095%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.462, 100.000%

Path8

Path Summary:

Slack	0.548
Data Arrival Time	1.950
Data Required Time	1.402
From	rx_mac_rst_n_3_s0
To	test[3].u_mac_rx_model/rx_data_cnt_pause_3_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.444	1.444	tNET	RR	1	R44C169[0][A]	rx_mac_rst_n_3_s0/CLK
1.588	0.144	tC2Q	RR	790	R44C169[0][A]	rx_mac_rst_n_3_s0/Q
1.950	0.362	tNET	RR	1	R42C160[1][A]	test[3].u_mac_rx_model/rx_data_cnt_pause_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.455	1.455	tNET	RR	1	R42C160[1][A]	test[3].u_mac_rx_model/rx_data_cnt_pause_3_s1/CLK
1.402	-0.053	tHld		1	R42C160[1][A]	test[3].u_mac_rx_model/rx_data_cnt_pause_3_s1

Path Statistics:

Clock Skew	0.011
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.444, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.362, 71.542%; tC2Q: 0.144, 28.458%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.455, 100.000%

Path9

Path Summary:

Slack	0.548
Data Arrival Time	1.950
Data Required Time	1.402
From	rx_mac_rst_n_3_s0
To	test[3].u_mac_rx_model/rx_data_cnt_pause_4_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.444	1.444	tNET	RR	1	R44C169[0][A]	rx_mac_rst_n_3_s0/CLK
1.588	0.144	tC2Q	RR	790	R44C169[0][A]	rx_mac_rst_n_3_s0/Q
1.950	0.362	tNET	RR	1	R42C160[1][B]	test[3].u_mac_rx_model/rx_data_cnt_pause_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.455	1.455	tNET	RR	1	R42C160[1][B]	test[3].u_mac_rx_model/rx_data_cnt_pause_4_s1/CLK
1.402	-0.053	tHld		1	R42C160[1][B]	test[3].u_mac_rx_model/rx_data_cnt_pause_4_s1

Path Statistics:

Clock Skew	0.011
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.444, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.362, 71.542%; tC2Q: 0.144, 28.458%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.455, 100.000%

Path10

Path Summary:

Slack	0.548
Data Arrival Time	1.950
Data Required Time	1.402
From	rx_mac_rst_n_3_s0
To	test[3].u_mac_rx_model/rx_data_cnt_pause_6_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.444	1.444	tNET	RR	1	R44C169[0][A]	rx_mac_rst_n_3_s0/CLK
1.588	0.144	tC2Q	RR	790	R44C169[0][A]	rx_mac_rst_n_3_s0/Q
1.950	0.362	tNET	RR	1	R42C160[2][A]	test[3].u_mac_rx_model/rx_data_cnt_pause_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.455	1.455	tNET	RR	1	R42C160[2][A]	test[3].u_mac_rx_model/rx_data_cnt_pause_6_s1/CLK
1.402	-0.053	tHld		1	R42C160[2][A]	test[3].u_mac_rx_model/rx_data_cnt_pause_6_s1

Path Statistics:

Clock Skew	0.011
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.444, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.362, 71.542%; tC2Q: 0.144, 28.458%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.455, 100.000%

Path11

Path Summary:

Slack	0.548
Data Arrival Time	1.950
Data Required Time	1.402
From	rx_mac_rst_n_3_s0
To	test[3].u_mac_rx_model/rx_data_cnt_pause_7_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.444	1.444	tNET	RR	1	R44C169[0][A]	rx_mac_rst_n_3_s0/CLK
1.588	0.144	tC2Q	RR	790	R44C169[0][A]	rx_mac_rst_n_3_s0/Q
1.950	0.362	tNET	RR	1	R42C160[0][A]	test[3].u_mac_rx_model/rx_data_cnt_pause_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.455	1.455	tNET	RR	1	R42C160[0][A]	test[3].u_mac_rx_model/rx_data_cnt_pause_7_s1/CLK
1.402	-0.053	tHld		1	R42C160[0][A]	test[3].u_mac_rx_model/rx_data_cnt_pause_7_s1

Path Statistics:

Clock Skew	0.011
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.444, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.362, 71.542%; tC2Q: 0.144, 28.458%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.455, 100.000%

Path12

Path Summary:

Slack	0.548
Data Arrival Time	1.950
Data Required Time	1.402
From	rx_mac_rst_n_3_s0
To	test[3].u_mac_rx_model/rx_data_cnt_pause_8_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.444	1.444	tNET	RR	1	R44C169[0][A]	rx_mac_rst_n_3_s0/CLK
1.588	0.144	tC2Q	RR	790	R44C169[0][A]	rx_mac_rst_n_3_s0/Q
1.950	0.362	tNET	RR	1	R42C160[0][B]	test[3].u_mac_rx_model/rx_data_cnt_pause_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.455	1.455	tNET	RR	1	R42C160[0][B]	test[3].u_mac_rx_model/rx_data_cnt_pause_8_s1/CLK
1.402	-0.053	tHld		1	R42C160[0][B]	test[3].u_mac_rx_model/rx_data_cnt_pause_8_s1

Path Statistics:

Clock Skew	0.011
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.444, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.362, 71.542%; tC2Q: 0.144, 28.458%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.455, 100.000%

Path13

Path Summary:

Slack	0.548
Data Arrival Time	1.950
Data Required Time	1.402
From	rx_mac_rst_n_3_s0
To	test[3].u_mac_rx_model/pause_address_36_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.444	1.444	tNET	RR	1	R44C169[0][A]	rx_mac_rst_n_3_s0/CLK
1.588	0.144	tC2Q	RR	790	R44C169[0][A]	rx_mac_rst_n_3_s0/Q
1.950	0.362	tNET	RR	1	R42C160[3][A]	test[3].u_mac_rx_model/pause_address_36_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.455	1.455	tNET	RR	1	R42C160[3][A]	test[3].u_mac_rx_model/pause_address_36_s1/CLK
1.402	-0.053	tHld		1	R42C160[3][A]	test[3].u_mac_rx_model/pause_address_36_s1

Path Statistics:

Clock Skew	0.011
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.444, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.362, 71.542%; tC2Q: 0.144, 28.458%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.455, 100.000%

Path14

Path Summary:

Slack	0.576
Data Arrival Time	1.985
Data Required Time	1.409
From	rx_mac_rst_n_2_s0
To	test[2].u_mac_rx_model/rx_running_s0
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.420	1.420	tNET	RR	1	R30C157[3][B]	rx_mac_rst_n_2_s0/CLK
1.564	0.144	tC2Q	RR	790	R30C157[3][B]	rx_mac_rst_n_2_s0/Q
1.985	0.421	tNET	RR	1	R38C164[2][A]	test[2].u_mac_rx_model/rx_running_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.462	1.462	tNET	RR	1	R38C164[2][A]	test[2].u_mac_rx_model/rx_running_s0/CLK
1.409	-0.053	tHld		1	R38C164[2][A]	test[2].u_mac_rx_model/rx_running_s0

Path Statistics:

Clock Skew	0.042
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.420, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.421, 74.513%; tC2Q: 0.144, 25.487%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.462, 100.000%

Path15

Path Summary:

Slack	0.588
Data Arrival Time	1.973
Data Required Time	1.386
From	rx_mac_rst_n_0_s0
To	cycle_all_time_0_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.456	1.456	tNET	RR	1	R39C167[0][A]	rx_mac_rst_n_0_s0/CLK
1.600	0.144	tC2Q	RR	790	R39C167[0][A]	rx_mac_rst_n_0_s0/Q
1.973	0.373	tNET	RR	1	R35C164[1][B]	cycle_all_time_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.439	1.439	tNET	RR	1	R35C164[1][B]	cycle_all_time_0_s1/CLK
1.386	-0.053	tHld		1	R35C164[1][B]	cycle_all_time_0_s1

Path Statistics:

Clock Skew	-0.018
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.456, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.373, 72.147%; tC2Q: 0.144, 27.853%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.439, 100.000%

Path16

Path Summary:

Slack	0.591
Data Arrival Time	1.989
Data Required Time	1.398
From	rstn_uart_s0
To	u_sysreg/reg0x0032_7_s0
Launch Clk	clk_uart:[R]
Latch Clk	clk_uart:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_uart
0.000	0.000	tCL	RR	2005	PLL_R[3]	u_pll_uart/u_pll/PLL_inst/CLKOUT0
1.457	1.457	tNET	RR	1	R41C165[0][A]	rstn_uart_s0/CLK
1.601	0.144	tC2Q	RR	956	R41C165[0][A]	rstn_uart_s0/Q
1.989	0.388	tNET	RR	1	R24C164[2][B]	u_sysreg/reg0x0032_7_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_uart
0.000	0.000	tCL	RR	2005	PLL_R[3]	u_pll_uart/u_pll/PLL_inst/CLKOUT0
1.451	1.451	tNET	RR	1	R24C164[2][B]	u_sysreg/reg0x0032_7_s0/CLK
1.398	-0.053	tHld		1	R24C164[2][B]	u_sysreg/reg0x0032_7_s0

Path Statistics:

Clock Skew	-0.006
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.457, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.388, 72.932%; tC2Q: 0.144, 27.068%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.451, 100.000%

Path17

Path Summary:

Slack	0.591
Data Arrival Time	1.989
Data Required Time	1.398
From	rstn_uart_s0
To	u_sysreg/reg0x0010_2_s0
Launch Clk	clk_uart:[R]
Latch Clk	clk_uart:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_uart
0.000	0.000	tCL	RR	2005	PLL_R[3]	u_pll_uart/u_pll/PLL_inst/CLKOUT0
1.457	1.457	tNET	RR	1	R41C165[0][A]	rstn_uart_s0/CLK
1.601	0.144	tC2Q	RR	956	R41C165[0][A]	rstn_uart_s0/Q
1.989	0.388	tNET	RR	1	R24C164[0][B]	u_sysreg/reg0x0010_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_uart
0.000	0.000	tCL	RR	2005	PLL_R[3]	u_pll_uart/u_pll/PLL_inst/CLKOUT0
1.451	1.451	tNET	RR	1	R24C164[0][B]	u_sysreg/reg0x0010_2_s0/CLK
1.398	-0.053	tHld		1	R24C164[0][B]	u_sysreg/reg0x0010_2_s0

Path Statistics:

Clock Skew	-0.006
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.457, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.388, 72.932%; tC2Q: 0.144, 27.068%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.451, 100.000%

Path18

Path Summary:

Slack	0.595
Data Arrival Time	1.989
Data Required Time	1.394
From	rstn_uart_s0
To	u_sysreg/reg0x0022_15_s0
Launch Clk	clk_uart:[R]
Latch Clk	clk_uart:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_uart
0.000	0.000	tCL	RR	2005	PLL_R[3]	u_pll_uart/u_pll/PLL_inst/CLKOUT0
1.457	1.457	tNET	RR	1	R41C165[0][A]	rstn_uart_s0/CLK
1.601	0.144	tC2Q	RR	956	R41C165[0][A]	rstn_uart_s0/Q
1.989	0.388	tNET	RR	1	R24C163[1][A]	u_sysreg/reg0x0022_15_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_uart
0.000	0.000	tCL	RR	2005	PLL_R[3]	u_pll_uart/u_pll/PLL_inst/CLKOUT0
1.447	1.447	tNET	RR	1	R24C163[1][A]	u_sysreg/reg0x0022_15_s0/CLK
1.394	-0.053	tHld		1	R24C163[1][A]	u_sysreg/reg0x0022_15_s0

Path Statistics:

Clock Skew	-0.010
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.457, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.388, 72.932%; tC2Q: 0.144, 27.068%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.447, 100.000%

Path19

Path Summary:

Slack	0.595
Data Arrival Time	1.989
Data Required Time	1.394
From	rstn_uart_s0
To	u_sysreg/reg0x0012_13_s0
Launch Clk	clk_uart:[R]
Latch Clk	clk_uart:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_uart
0.000	0.000	tCL	RR	2005	PLL_R[3]	u_pll_uart/u_pll/PLL_inst/CLKOUT0
1.457	1.457	tNET	RR	1	R41C165[0][A]	rstn_uart_s0/CLK
1.601	0.144	tC2Q	RR	956	R41C165[0][A]	rstn_uart_s0/Q
1.989	0.388	tNET	RR	1	R24C163[0][B]	u_sysreg/reg0x0012_13_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_uart
0.000	0.000	tCL	RR	2005	PLL_R[3]	u_pll_uart/u_pll/PLL_inst/CLKOUT0
1.447	1.447	tNET	RR	1	R24C163[0][B]	u_sysreg/reg0x0012_13_s0/CLK
1.394	-0.053	tHld		1	R24C163[0][B]	u_sysreg/reg0x0012_13_s0

Path Statistics:

Clock Skew	-0.010
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.457, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.388, 72.932%; tC2Q: 0.144, 27.068%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.447, 100.000%

Path20

Path Summary:

Slack	0.595
Data Arrival Time	1.989
Data Required Time	1.394
From	rstn_uart_s0
To	u_sysreg/reg0x0000_2_s0
Launch Clk	clk_uart:[R]
Latch Clk	clk_uart:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_uart
0.000	0.000	tCL	RR	2005	PLL_R[3]	u_pll_uart/u_pll/PLL_inst/CLKOUT0
1.457	1.457	tNET	RR	1	R41C165[0][A]	rstn_uart_s0/CLK
1.601	0.144	tC2Q	RR	956	R41C165[0][A]	rstn_uart_s0/Q
1.989	0.388	tNET	RR	1	R24C163[2][B]	u_sysreg/reg0x0000_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_uart
0.000	0.000	tCL	RR	2005	PLL_R[3]	u_pll_uart/u_pll/PLL_inst/CLKOUT0
1.447	1.447	tNET	RR	1	R24C163[2][B]	u_sysreg/reg0x0000_2_s0/CLK
1.394	-0.053	tHld		1	R24C163[2][B]	u_sysreg/reg0x0000_2_s0

Path Statistics:

Clock Skew	-0.010
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.457, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.388, 72.932%; tC2Q: 0.144, 27.068%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.447, 100.000%

Path21

Path Summary:

Slack	0.623
Data Arrival Time	2.003
Data Required Time	1.380
From	rx_mac_rst_n_2_s0
To	cycle_one_time_2_s0
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.420	1.420	tNET	RR	1	R30C157[3][B]	rx_mac_rst_n_2_s0/CLK
1.564	0.144	tC2Q	RR	790	R30C157[3][B]	rx_mac_rst_n_2_s0/Q
2.003	0.439	tNET	RR	1	R34C147[1][A]	cycle_one_time_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.433	1.433	tNET	RR	1	R34C147[1][A]	cycle_one_time_2_s0/CLK
1.380	-0.053	tHld		1	R34C147[1][A]	cycle_one_time_2_s0

Path Statistics:

Clock Skew	0.013
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.420, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.439, 75.300%; tC2Q: 0.144, 24.700%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.433, 100.000%

Path22

Path Summary:

Slack	0.624
Data Arrival Time	2.019
Data Required Time	1.395
From	rx_mac_rst_n_3_s0
To	test[3].u_mac_rx_model/rx_frm_cnt_6_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.444	1.444	tNET	RR	1	R44C169[0][A]	rx_mac_rst_n_3_s0/CLK
1.588	0.144	tC2Q	RR	790	R44C169[0][A]	rx_mac_rst_n_3_s0/Q
2.019	0.431	tNET	RR	1	R44C152[1][B]	test[3].u_mac_rx_model/rx_frm_cnt_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.448	1.448	tNET	RR	1	R44C152[1][B]	test[3].u_mac_rx_model/rx_frm_cnt_6_s1/CLK
1.395	-0.053	tHld		1	R44C152[1][B]	test[3].u_mac_rx_model/rx_frm_cnt_6_s1

Path Statistics:

Clock Skew	0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.444, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.431, 74.957%; tC2Q: 0.144, 25.043%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.448, 100.000%

Path23

Path Summary:

Slack	0.624
Data Arrival Time	2.019
Data Required Time	1.395
From	rx_mac_rst_n_3_s0
To	test[3].u_mac_rx_model/rx_frm_cnt_7_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.444	1.444	tNET	RR	1	R44C169[0][A]	rx_mac_rst_n_3_s0/CLK
1.588	0.144	tC2Q	RR	790	R44C169[0][A]	rx_mac_rst_n_3_s0/Q
2.019	0.431	tNET	RR	1	R44C152[1][A]	test[3].u_mac_rx_model/rx_frm_cnt_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.448	1.448	tNET	RR	1	R44C152[1][A]	test[3].u_mac_rx_model/rx_frm_cnt_7_s1/CLK
1.395	-0.053	tHld		1	R44C152[1][A]	test[3].u_mac_rx_model/rx_frm_cnt_7_s1

Path Statistics:

Clock Skew	0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.444, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.431, 74.957%; tC2Q: 0.144, 25.043%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.448, 100.000%

Path24

Path Summary:

Slack	0.628
Data Arrival Time	2.019
Data Required Time	1.391
From	rx_mac_rst_n_3_s0
To	test[3].u_mac_rx_model/latch_data_end_s2
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.444	1.444	tNET	RR	1	R44C169[0][A]	rx_mac_rst_n_3_s0/CLK
1.588	0.144	tC2Q	RR	790	R44C169[0][A]	rx_mac_rst_n_3_s0/Q
2.019	0.431	tNET	RR	1	R44C151[2][B]	test[3].u_mac_rx_model/latch_data_end_s2/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.444	1.444	tNET	RR	1	R44C151[2][B]	test[3].u_mac_rx_model/latch_data_end_s2/CLK
1.391	-0.053	tHld		1	R44C151[2][B]	test[3].u_mac_rx_model/latch_data_end_s2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.444, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.431, 74.957%; tC2Q: 0.144, 25.043%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.444, 100.000%

Path25

Path Summary:

Slack	0.628
Data Arrival Time	2.019
Data Required Time	1.391
From	rx_mac_rst_n_3_s0
To	test[3].u_mac_rx_model/pause_data_3_5_s1
Launch Clk	rx_mac_clk:[R]
Latch Clk	rx_mac_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.444	1.444	tNET	RR	1	R44C169[0][A]	rx_mac_rst_n_3_s0/CLK
1.588	0.144	tC2Q	RR	790	R44C169[0][A]	rx_mac_rst_n_3_s0/Q
2.019	0.431	tNET	RR	1	R44C151[2][A]	test[3].u_mac_rx_model/pause_data_3_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx_mac_clk
0.000	0.000	tCL	RR	6511	R0C38	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
1.444	1.444	tNET	RR	1	R44C151[2][A]	test[3].u_mac_rx_model/pause_data_3_5_s1/CLK
1.391	-0.053	tHld		1	R44C151[2][A]	test[3].u_mac_rx_model/pause_data_3_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.444, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.431, 74.957%; tC2Q: 0.144, 25.043%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.444, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	0.902
Actual Width:	1.902
Required Width:	1.000
Type:	High Pulse Width
Clock:	rx_mac_clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			rx_mac_clk
0.000	0.000	tCL	RR	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.835	3.835	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			rx_mac_clk
4.000	0.000	tCL	FF	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
5.737	1.737	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

MPW2

MPW Summary:

Slack:	0.902
Actual Width:	1.902
Required Width:	1.000
Type:	High Pulse Width
Clock:	rx_mac_clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			rx_mac_clk
0.000	0.000	tCL	RR	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.835	3.835	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			rx_mac_clk
4.000	0.000	tCL	FF	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
5.737	1.737	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/CLKB

MPW3

MPW Summary:

Slack:	1.041
Actual Width:	2.041
Required Width:	1.000
Type:	Low Pulse Width
Clock:	rx_mac_clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			rx_mac_clk
4.000	0.000	tCL	FF	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
7.397	3.397	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			rx_mac_clk
8.000	0.000	tCL	RR	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
9.438	1.438	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA

MPW4

MPW Summary:

Slack:	1.041
Actual Width:	2.041
Required Width:	1.000
Type:	Low Pulse Width
Clock:	rx_mac_clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			rx_mac_clk
4.000	0.000	tCL	FF	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
7.397	3.397	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
8.000	0.000			active clock edge time
8.000	0.000			rx_mac_clk
8.000	0.000	tCL	RR	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
9.438	1.438	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/mem_mem_0_0_s/CLKB

MPW5

MPW Summary:

Slack:	1.591
Actual Width:	1.841
Required Width:	0.250
Type:	High Pulse Width
Clock:	rx_mac_clk
Objects:	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_an/an_sync_status_fail_cnt_12_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			rx_mac_clk
0.000	0.000	tCL	RR	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.936	3.936	tNET	RR	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_an/an_sync_status_fail_cnt_12_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			rx_mac_clk
4.000	0.000	tCL	FF	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
5.777	1.777	tNET	FF	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_an/an_sync_status_fail_cnt_12_s1/CLK

MPW6

MPW Summary:

Slack:	1.591
Actual Width:	1.841
Required Width:	0.250
Type:	High Pulse Width
Clock:	rx_mac_clk
Objects:	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_an/an_sync_status_fail_cnt_11_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			rx_mac_clk
0.000	0.000	tCL	RR	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.936	3.936	tNET	RR	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_an/an_sync_status_fail_cnt_11_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			rx_mac_clk
4.000	0.000	tCL	FF	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
5.777	1.777	tNET	FF	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_an/an_sync_status_fail_cnt_11_s1/CLK

MPW7

MPW Summary:

Slack:	1.591
Actual Width:	1.841
Required Width:	0.250
Type:	High Pulse Width
Clock:	rx_mac_clk
Objects:	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/serdes_rxdata_i_d1_43_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			rx_mac_clk
0.000	0.000	tCL	RR	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.936	3.936	tNET	RR	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/serdes_rxdata_i_d1_43_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			rx_mac_clk
4.000	0.000	tCL	FF	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
5.777	1.777	tNET	FF	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/serdes_rxdata_i_d1_43_s0/CLK

MPW8

MPW Summary:

Slack:	1.591
Actual Width:	1.841
Required Width:	0.250
Type:	High Pulse Width
Clock:	rx_mac_clk
Objects:	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_rx_ctrl/u_crc_chk/crc_reg_0_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			rx_mac_clk
0.000	0.000	tCL	RR	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.936	3.936	tNET	RR	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_rx_ctrl/u_crc_chk/crc_reg_0_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			rx_mac_clk
4.000	0.000	tCL	FF	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
5.777	1.777	tNET	FF	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_rx_ctrl/u_crc_chk/crc_reg_0_s1/CLK

MPW9

MPW Summary:

Slack:	1.591
Actual Width:	1.841
Required Width:	0.250
Type:	High Pulse Width
Clock:	rx_mac_clk
Objects:	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_an/an_sync_status_fail_cnt_15_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			rx_mac_clk
0.000	0.000	tCL	RR	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.936	3.936	tNET	RR	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_an/an_sync_status_fail_cnt_15_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			rx_mac_clk
4.000	0.000	tCL	FF	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
5.777	1.777	tNET	FF	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_an/an_sync_status_fail_cnt_15_s1/CLK

MPW10

MPW Summary:

Slack:	1.591
Actual Width:	1.841
Required Width:	0.250
Type:	High Pulse Width
Clock:	rx_mac_clk
Objects:	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_an/an_sync_status_fail_cnt_14_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			rx_mac_clk
0.000	0.000	tCL	RR	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
3.936	3.936	tNET	RR	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_an/an_sync_status_fail_cnt_14_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
4.000	0.000			active clock edge time
4.000	0.000			rx_mac_clk
4.000	0.000	tCL	FF	u_SerDes_Top/gtr12_quad_inst1/LANE3_PCS_RX_O_FABRIC_CLK
5.777	1.777	tNET	FF	u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_an/an_sync_status_fail_cnt_14_s1/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
6511	rx_mac_clk[3]	0.945	3.936
3633	tx_mac_clk[3]	0.246	3.939
2005	clk_uart	85.907	3.931
956	rstn_uart	96.298	1.220
214	gw_gao_inst_0/control0[0]	42.864	5.654
196	u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/rd_ptr[2]	95.546	2.369
192	u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/rd_ptr[2]	92.866	4.768
162	test[3].u_mac_rx_model/rx_pause_state	4.290	2.730
162	test[2].u_mac_rx_model/rx_pause_state	4.058	2.873
162	test[1].u_mac_rx_model/rx_pause_state	5.096	1.913

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R2C2	100.00%
R2C3	100.00%
R2C4	100.00%
R2C61	100.00%
R2C65	100.00%
R2C67	100.00%
R2C68	100.00%
R3C16	100.00%
R4C92	100.00%
R7C64	100.00%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name tck_pad -period 50 -waveform {0 25} [get_pins {gw_gao_inst_0/tck_ibuf/I}]
TC_CLOCK	Actived	create_clock -name clk_in -period 20 -waveform {0 10} [get_pins {clk_in_ibuf/I}]
TC_CLOCK	Actived	create_clock -name tx_mac_clk -period 8 -waveform {0 4} [get_nets {tx_mac_clk[3]}]
TC_CLOCK	Actived	create_clock -name rx_mac_clk -period 8 -waveform {0 4} [get_nets {rx_mac_clk[3]}]
TC_GENERATED_CLOCK	Actived	create_generated_clock -name clk_uart -source [get_pins {clk_in_ibuf/I}] -master_clock clk_in -divide_by 80 -multiply_by 16 [get_pins {u_pll_uart/u_pll/PLL_inst/CLKOUT0}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {clk_uart tck_pad clk_in}] -to [get_clocks {rx_mac_clk tx_mac_clk clk_in}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {rx_mac_clk tx_mac_clk}] -to [get_clocks {clk_uart tck_pad}]