Power Messages

Report Title	Power Analysis Report
Design File	E:\IP_Release\QSGMII\191201\Gowin_QSGMII_IP_RefDesign\project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File	E:\IP_Release\QSGMII\191201\Gowin_QSGMII_IP_RefDesign\project\src\fpga_project.cst
Timing Constraints File	E:\IP_Release\QSGMII\191201\Gowin_QSGMII_IP_RefDesign\project\src\fpga_project.sdc
Tool Version	V1.9.12.01 (64-bit)
Part Number	GW5AST-LV138FPG676AES
Device	GW5AST-138
Device Version	B
Created Time	Tue Dec 30 11:03:41 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Configure Information:

Grade	Commercial
Process	Typical
Ambient Temperature	25.000
Use Custom Theta JA	false
Heat Sink	None
Air Flow	LFM_0
Use Custom Theta SA	false
Board Thermal Model	None
Use Custom Theta JB	false
Related Vcd File
Related Saif File
Filter Glitches	false
Default IO Toggle Rate	0.125
Default Remain Toggle Rate	0.125

Power Summary

Power Information:

Total Power (mW)	128.305
Quiescent Power (mW)	100.685
Dynamic Power (mW)	27.619

Thermal Information:

Junction Temperature	26.568
Theta JA	12.222
Max Allowed Ambient Temperature	83.432

Supply Information:

Voltage Source	Voltage	Dynamic Current(mA)	Quiescent Current(mA)	Power(mW)
VCC	0.900	28.737	80.009	97.871
VCCX	1.800	0.342	7.200	13.576
VCCIO33	3.300	0.346	3.017	11.098
VCCLDO	1.200	0.000	4.800	5.760

Power Details

Power By Block Type:

Block Type	Total Power(mW)	Static Power(mW)	Average Toggle Rate(millions of transitions/sec)
Logic	10.539	NA	13.299
IO	13.003	10.939	13.854
BSRAM	7.161	NA	NA
PLL	7.839	NA	NA

Power By Hierarchy:

Hierarchy Entity	Total Power(mW)	Block Dynamic Power(mW)
top	25.540	25.540(25.456)
top/gw_gao_inst_0/	7.261	7.261(7.261)
top/gw_gao_inst_0/u_icon_top/	0.002	0.002(0.000)
top/gw_gao_inst_0/u_la0_top/	7.259	7.259(7.207)
top/gw_gao_inst_0/u_la0_top/u_ao_crc32/	0.004	0.004(0.000)
top/gw_gao_inst_0/u_la0_top/u_ao_dynamic_expression_0/	3.430	3.430(0.000)
top/gw_gao_inst_0/u_la0_top/u_ao_match_0/	0.005	0.005(0.000)
top/gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/	3.769	3.769(0.000)
top/sw1/	0.002	0.002(0.000)
top/test[0].u_mac_rx_model/	0.895	0.895(0.000)
top/test[0].u_mac_tx_model/	0.628	0.628(0.000)
top/test[1].u_mac_rx_model/	0.897	0.897(0.000)
top/test[1].u_mac_tx_model/	0.628	0.628(0.000)
top/test[2].u_mac_rx_model/	0.895	0.895(0.000)
top/test[2].u_mac_tx_model/	0.627	0.627(0.000)
top/test[3].u_mac_rx_model/	0.895	0.895(0.000)
top/test[3].u_mac_tx_model/	0.628	0.628(0.000)
top/u_SerDes_Top/	4.102	4.102(4.102)
top/u_SerDes_Top/QSGMII_Top_inst/	4.102	4.102(4.102)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/	4.102	4.102(4.024)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/	1.002	1.002(0.986)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_an/	0.118	0.118(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_rx/	0.160	0.160(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_sync/	0.031	0.031(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_ge_tx/	0.077	0.077(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_rx_ctrl/	0.261	0.261(0.046)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_rx_ctrl/u_crc_chk/	0.046	0.046(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/	0.339	0.339(0.072)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/u_crc_gen/	0.049	0.049(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port0/u_mac_tx_ctrl/u_lfsr/	0.023	0.023(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/	1.006	1.006(0.989)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_ge_an/	0.118	0.118(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_ge_rx/	0.160	0.160(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_ge_sync/	0.031	0.031(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_ge_tx/	0.077	0.077(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/	0.259	0.259(0.046)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_rx_ctrl/u_crc_chk/	0.046	0.046(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/	0.344	0.344(0.070)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/u_crc_gen/	0.048	0.048(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port1/u_mac_tx_ctrl/u_lfsr/	0.022	0.022(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/	1.004	1.004(0.987)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_an/	0.118	0.118(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_rx/	0.160	0.160(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_sync/	0.031	0.031(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_ge_tx/	0.077	0.077(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_rx_ctrl/	0.259	0.259(0.044)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_rx_ctrl/u_crc_chk/	0.044	0.044(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/	0.343	0.343(0.072)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/u_crc_gen/	0.050	0.050(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port2/u_mac_tx_ctrl/u_lfsr/	0.022	0.022(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/	1.007	1.007(0.990)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_an/	0.118	0.118(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_rx/	0.160	0.160(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_sync/	0.031	0.031(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_ge_tx/	0.077	0.077(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_rx_ctrl/	0.263	0.263(0.047)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_rx_ctrl/u_crc_chk/	0.047	0.047(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/	0.342	0.342(0.072)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/u_crc_gen/	0.050	0.050(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_ge_pcs_port3/u_mac_tx_ctrl/u_lfsr/	0.022	0.022(0.000)
top/u_SerDes_Top/QSGMII_Top_inst/u_ge_pcs_qsgmii/u_serdes_control/	0.006	0.006(0.000)
top/u_Uart_to_Bus_Top/	0.070	0.070(0.070)
top/u_Uart_to_Bus_Top/uart_bus_core/	0.070	0.070(0.065)
top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/	0.065	0.065(0.065)
top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/	0.002	0.002(0.000)
top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/	0.031	0.031(0.031)
top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/	0.028	0.028(0.022)
top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/	0.022	0.022(0.000)
top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/	0.002	0.002(0.000)
top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/	0.032	0.032(0.032)
top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/	0.029	0.029(0.023)
top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/	0.023	0.023(0.000)
top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/	0.003	0.003(0.000)
top/u_pll_uart/	7.875	7.875(7.875)
top/u_pll_uart/u_pll/	7.839	7.839(0.000)
top/u_pll_uart/u_pll_init/	0.035	0.035(0.000)
top/u_sysreg/	0.052	0.052(0.000)
top/uart1/	0.002	0.002(0.000)

Power By Clock Domain:

Clock Domain	Clock Frequency(Mhz)	Total Dynamic Power(mW)
tx_mac_clk	125.000	4.243
rx_mac_clk	125.000	12.305
clk_uart	10.000	0.106
tck_pad	20.000	1.019
NO CLOCK DOMAIN	0.000	0.000
clk_in	50.000	7.882