Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\IP_Release\QSGMII\191201\Gowin_QSGMII_IP_RefDesign\project\src\button.v E:\IP_Release\QSGMII\191201\Gowin_QSGMII_IP_RefDesign\project\src\mac_rx_model.v E:\IP_Release\QSGMII\191201\Gowin_QSGMII_IP_RefDesign\project\src\mac_tx_model.v E:\IP_Release\QSGMII\191201\Gowin_QSGMII_IP_RefDesign\project\src\pll_uart\pll_uart.v E:\IP_Release\QSGMII\191201\Gowin_QSGMII_IP_RefDesign\project\src\serdes\qsgmii\qsgmii.v E:\IP_Release\QSGMII\191201\Gowin_QSGMII_IP_RefDesign\project\src\serdes\serdes.v E:\IP_Release\QSGMII\191201\Gowin_QSGMII_IP_RefDesign\project\src\sysreg.v E:\IP_Release\QSGMII\191201\Gowin_QSGMII_IP_RefDesign\project\src\top.v E:\IP_Release\QSGMII\191201\Gowin_QSGMII_IP_RefDesign\project\src\uart_to_bus\uart_to_bus.v E:\IP_Release\QSGMII\191201\Gowin_QSGMII_IP_RefDesign\project\src\pll_uart\pll_uart_mod.v E:\IP_Release\QSGMII\191201\Gowin_QSGMII_IP_RefDesign\project\src\pll_init.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top_138.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\data\ipcores\gw_jtag.v E:\IP_Release\QSGMII\191201\Gowin_QSGMII_IP_RefDesign\project\impl\gwsynthesis\RTL_GAO\gw_gao_top.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12.01 (64-bit) |
| Part Number | GW5AST-LV138FPG676AES |
| Device | GW5AST-138 |
| Device Version | B |
| Created Time | Tue Dec 30 11:01:08 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | top |
| Synthesis Process | Running parser: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 1616.777MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 1616.777MB Optimizing Phase 1: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 1616.777MB Optimizing Phase 2: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 1616.777MB Running inference: Inferring Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 1616.777MB Inferring Phase 1: CPU time = 0h 0m 0.39s, Elapsed time = 0h 0m 0.394s, Peak memory usage = 1616.777MB Inferring Phase 2: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.202s, Peak memory usage = 1616.777MB Inferring Phase 3: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.138s, Peak memory usage = 1616.777MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 1616.777MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.671s, Elapsed time = 0h 0m 0.665s, Peak memory usage = 1616.777MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.484s, Elapsed time = 0h 0m 0.49s, Peak memory usage = 1616.777MB Tech-Mapping Phase 3: CPU time = 0h 0m 13s, Elapsed time = 0h 0m 13s, Peak memory usage = 1616.777MB Tech-Mapping Phase 4: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 1616.777MB Generate output files: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 1616.777MB |
| Total Time and Memory Usage | CPU time = 0h 0m 28s, Elapsed time = 0h 0m 28s, Peak memory usage = 1616.777MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 12 |
| I/O Buf | 12 |
| IBUF | 6 |
| OBUF | 6 |
| Register | 12425 |
| DFFRE | 1021 |
| DFFPE | 594 |
| DFFCE | 10810 |
| LUT | 12214 |
| LUT2 | 1525 |
| LUT3 | 3544 |
| LUT4 | 7145 |
| MUX | 1 |
| MUX16 | 1 |
| ALU | 1329 |
| ALU | 1329 |
| INV | 86 |
| INV | 86 |
| BSRAM | 2 |
| SDPB | 2 |
| CLOCK | 1 |
| PLL | 1 |
| Black Box | 2 |
| GW_JTAG | 1 |
| GTR12_QUAD | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 13637(12308 LUT, 1329 ALU) / 138240 | 10% |
| Register | 12425 / 139140 | 9% |
| --Register as Latch | 0 / 139140 | 0% |
| --Register as FF | 12425 / 139140 | 9% |
| BSRAM | 2 / 340 | <1% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk_in | Base | 20.000 | 50.000 | 0.000 | 10.000 | clk_in_ibuf/I | ||
| 2 | gw_gao_inst_0/u_icon_top/n31_6 | Base | 10.000 | 100.000 | 0.000 | 5.000 | gw_gao_inst_0/u_icon_top/n31_s2/F | ||
| 3 | gw_gao_inst_0/u_la0_top/n15_6 | Base | 10.000 | 100.000 | 0.000 | 5.000 | gw_gao_inst_0/u_la0_top/n15_s2/F | ||
| 4 | u_pll_uart/u_pll/PLL_inst/CLKOUT0.default_gen_clk | Generated | 100.000 | 10.000 | 0.000 | 50.000 | clk_in_ibuf/I | clk_in | u_pll_uart/u_pll/PLL_inst/CLKOUT0 |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk_in | 50.000(MHz) | 207.308(MHz) | 5 | TOP |
| 2 | gw_gao_inst_0/u_icon_top/n31_6 | 100.000(MHz) | 1164.484(MHz) | 1 | TOP |
| 3 | gw_gao_inst_0/u_la0_top/n15_6 | 100.000(MHz) | 1164.484(MHz) | 1 | TOP |
| 4 | u_pll_uart/u_pll/PLL_inst/CLKOUT0.default_gen_clk | 10.000(MHz) | 113.928(MHz) | 9 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 9.141 |
| Data Arrival Time | 1.207 |
| Data Required Time | 10.349 |
| From | gw_gao_inst_0/u_la0_top/rst_ao_syn_s0 |
| To | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| Launch Clk | gw_gao_inst_0/u_la0_top/n15_6[R] |
| Latch Clk | gw_gao_inst_0/u_la0_top/n15_6[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | gw_gao_inst_0/u_la0_top/n15_6 | |||
| 0.000 | 0.000 | tCL | RR | 2 | gw_gao_inst_0/u_la0_top/n15_s2/F |
| 0.413 | 0.413 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/rst_ao_syn_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 1 | gw_gao_inst_0/u_la0_top/rst_ao_syn_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/rst_ao_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | gw_gao_inst_0/u_la0_top/n15_6 | |||
| 10.000 | 0.000 | tCL | RR | 2 | gw_gao_inst_0/u_la0_top/n15_s2/F |
| 10.413 | 0.413 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK |
| 10.349 | -0.064 | tSu | 1 | gw_gao_inst_0/u_la0_top/rst_ao_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.413, 51.887%; tC2Q: 0.382, 48.113% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 2
Path Summary:| Slack | 9.141 |
| Data Arrival Time | 1.207 |
| Data Required Time | 10.349 |
| From | gw_gao_inst_0/u_icon_top/enable_reg_1_s0 |
| To | gw_gao_inst_0/u_icon_top/enable_reg_0_s0 |
| Launch Clk | gw_gao_inst_0/u_icon_top/n31_6[R] |
| Latch Clk | gw_gao_inst_0/u_icon_top/n31_6[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | gw_gao_inst_0/u_icon_top/n31_6 | |||
| 0.000 | 0.000 | tCL | RR | 4 | gw_gao_inst_0/u_icon_top/n31_s2/F |
| 0.413 | 0.413 | tNET | RR | 1 | gw_gao_inst_0/u_icon_top/enable_reg_1_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 3 | gw_gao_inst_0/u_icon_top/enable_reg_1_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | gw_gao_inst_0/u_icon_top/enable_reg_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | gw_gao_inst_0/u_icon_top/n31_6 | |||
| 10.000 | 0.000 | tCL | RR | 4 | gw_gao_inst_0/u_icon_top/n31_s2/F |
| 10.413 | 0.413 | tNET | RR | 1 | gw_gao_inst_0/u_icon_top/enable_reg_0_s0/CLK |
| 10.349 | -0.064 | tSu | 1 | gw_gao_inst_0/u_icon_top/enable_reg_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.413, 51.887%; tC2Q: 0.382, 48.113% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 3
Path Summary:| Slack | 9.141 |
| Data Arrival Time | 1.207 |
| Data Required Time | 10.349 |
| From | gw_gao_inst_0/u_icon_top/enable_reg_2_s0 |
| To | gw_gao_inst_0/u_icon_top/enable_reg_1_s0 |
| Launch Clk | gw_gao_inst_0/u_icon_top/n31_6[R] |
| Latch Clk | gw_gao_inst_0/u_icon_top/n31_6[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | gw_gao_inst_0/u_icon_top/n31_6 | |||
| 0.000 | 0.000 | tCL | RR | 4 | gw_gao_inst_0/u_icon_top/n31_s2/F |
| 0.413 | 0.413 | tNET | RR | 1 | gw_gao_inst_0/u_icon_top/enable_reg_2_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 3 | gw_gao_inst_0/u_icon_top/enable_reg_2_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | gw_gao_inst_0/u_icon_top/enable_reg_1_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | gw_gao_inst_0/u_icon_top/n31_6 | |||
| 10.000 | 0.000 | tCL | RR | 4 | gw_gao_inst_0/u_icon_top/n31_s2/F |
| 10.413 | 0.413 | tNET | RR | 1 | gw_gao_inst_0/u_icon_top/enable_reg_1_s0/CLK |
| 10.349 | -0.064 | tSu | 1 | gw_gao_inst_0/u_icon_top/enable_reg_1_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.413, 51.887%; tC2Q: 0.382, 48.113% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 4
Path Summary:| Slack | 15.176 |
| Data Arrival Time | 5.173 |
| Data Required Time | 20.349 |
| From | u_pll_uart/u_pll_init/locksig_2_s0 |
| To | u_pll_uart/u_pll_init/RomAddr_0_s1 |
| Launch Clk | clk_in[R] |
| Latch Clk | clk_in[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_in | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 69 | clk_in_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | u_pll_uart/u_pll_init/locksig_2_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 6 | u_pll_uart/u_pll_init/locksig_2_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | u_pll_uart/u_pll_init/n521_s17/I0 |
| 1.786 | 0.579 | tINS | RR | 3 | u_pll_uart/u_pll_init/n521_s17/F |
| 2.199 | 0.413 | tNET | RR | 1 | u_pll_uart/u_pll_init/n527_s14/I0 |
| 2.778 | 0.579 | tINS | RR | 1 | u_pll_uart/u_pll_init/n527_s14/F |
| 3.190 | 0.413 | tNET | RR | 1 | u_pll_uart/u_pll_init/n527_s13/I0 |
| 3.769 | 0.579 | tINS | RR | 1 | u_pll_uart/u_pll_init/n527_s13/F |
| 4.181 | 0.413 | tNET | RR | 1 | u_pll_uart/u_pll_init/n527_s12/I0 |
| 4.760 | 0.579 | tINS | RR | 1 | u_pll_uart/u_pll_init/n527_s12/F |
| 5.173 | 0.413 | tNET | RR | 1 | u_pll_uart/u_pll_init/RomAddr_0_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | clk_in | |||
| 20.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 69 | clk_in_ibuf/O |
| 20.413 | 0.413 | tNET | RR | 1 | u_pll_uart/u_pll_init/RomAddr_0_s1/CLK |
| 20.349 | -0.064 | tSu | 1 | u_pll_uart/u_pll_init/RomAddr_0_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 2.315, 48.634%; route: 2.062, 43.330%; tC2Q: 0.382, 8.036% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 5
Path Summary:| Slack | 15.259 |
| Data Arrival Time | 5.090 |
| Data Required Time | 20.349 |
| From | u_pll_uart/u_pll_init/locksig_0_s0 |
| To | u_pll_uart/u_pll_init/RomAddr_2_s1 |
| Launch Clk | clk_in[R] |
| Latch Clk | clk_in[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk_in | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 69 | clk_in_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | u_pll_uart/u_pll_init/locksig_0_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 7 | u_pll_uart/u_pll_init/locksig_0_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | u_pll_uart/u_pll_init/n523_s19/I0 |
| 1.786 | 0.579 | tINS | RR | 2 | u_pll_uart/u_pll_init/n523_s19/F |
| 2.199 | 0.413 | tNET | RR | 1 | u_pll_uart/u_pll_init/n523_s16/I2 |
| 2.706 | 0.507 | tINS | RR | 1 | u_pll_uart/u_pll_init/n523_s16/F |
| 3.119 | 0.413 | tNET | RR | 1 | u_pll_uart/u_pll_init/n523_s14/I0 |
| 3.698 | 0.579 | tINS | RR | 1 | u_pll_uart/u_pll_init/n523_s14/F |
| 4.110 | 0.413 | tNET | RR | 1 | u_pll_uart/u_pll_init/n523_s12/I1 |
| 4.678 | 0.567 | tINS | RR | 1 | u_pll_uart/u_pll_init/n523_s12/F |
| 5.090 | 0.413 | tNET | RR | 1 | u_pll_uart/u_pll_init/RomAddr_2_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | clk_in | |||
| 20.000 | 0.000 | tCL | RR | 1 | clk_in_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 69 | clk_in_ibuf/O |
| 20.413 | 0.413 | tNET | RR | 1 | u_pll_uart/u_pll_init/RomAddr_2_s1/CLK |
| 20.349 | -0.064 | tSu | 1 | u_pll_uart/u_pll_init/RomAddr_2_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 2.233, 47.729%; route: 2.062, 44.094%; tC2Q: 0.382, 8.177% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |