Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\W_File\RS_Code\Onboard\RS_Code_Ref_Design\fpga_project\src\rs_decoder\rs_decoder.v E:\W_File\RS_Code\Onboard\RS_Code_Ref_Design\fpga_project\src\rs_encoder\rs_encoder.v E:\W_File\RS_Code\Onboard\RS_Code_Ref_Design\fpga_project\src\RS_exp.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.9.01 (64-bit) |
| Part Number | GW2A-LV55PG484C8/I7 |
| Device | GW2A-55 |
| Device Version | C |
| Created Time | Tue Dec 26 10:27:52 2023 |
| Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | RS_exp |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.358s, Peak memory usage = 288.875MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 288.875MB Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.032s, Peak memory usage = 288.875MB Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 288.875MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 288.875MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 288.875MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 288.875MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 288.875MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.031s, Peak memory usage = 288.875MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 288.875MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 288.875MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.329s, Peak memory usage = 315.102MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.026s, Peak memory usage = 315.102MB Generate output files: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.106s, Peak memory usage = 315.102MB |
| Total Time and Memory Usage | CPU time = 0h 0m 0.994s, Elapsed time = 0h 0m 0.986s, Peak memory usage = 315.102MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 22 |
| I/O Buf | 21 |
| IBUF | 2 |
| OBUF | 19 |
| Register | 765 |
| DFFP | 7 |
| DFFPE | 3 |
| DFFC | 473 |
| DFFCE | 282 |
| LUT | 1630 |
| LUT2 | 191 |
| LUT3 | 368 |
| LUT4 | 1071 |
| ALU | 6 |
| ALU | 6 |
| SSRAM | 8 |
| RAM16SDP4 | 8 |
| INV | 3 |
| INV | 3 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 1687(1633 LUT, 6 ALU, 8 RAM16) / 54720 | 4% |
| Register | 765 / 41997 | 2% |
| --Register as Latch | 0 / 41997 | 0% |
| --Register as FF | 765 / 41997 | 2% |
| BSRAM | 0 / 140 | 0% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| SYM_CLK | Base | 10.000 | 100.0 | 0.000 | 5.000 | SYM_CLK_ibuf/I |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | SYM_CLK | 100.0(MHz) | 168.5(MHz) | 8 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 4.066 |
| Data Arrival Time | 6.762 |
| Data Required Time | 10.828 |
| From | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0 |
| To | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_1_s |
| Launch Clk | SYM_CLK[R] |
| Latch Clk | SYM_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | SYM_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 773 | SYM_CLK_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 8 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s22/I1 |
| 1.887 | 0.555 | tINS | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s22/F |
| 2.124 | 0.237 | tNET | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s13/I1 |
| 2.679 | 0.555 | tINS | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s13/F |
| 2.916 | 0.237 | tNET | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s8/I1 |
| 3.471 | 0.555 | tINS | FF | 9 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s8/F |
| 3.708 | 0.237 | tNET | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_1_s4/I0 |
| 4.225 | 0.517 | tINS | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_1_s4/F |
| 4.462 | 0.237 | tNET | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_1_s2/I0 |
| 4.979 | 0.517 | tINS | FF | 3 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_1_s2/F |
| 5.216 | 0.237 | tNET | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s3/I0 |
| 5.733 | 0.517 | tINS | FF | 2 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s3/F |
| 5.970 | 0.237 | tNET | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s1/I1 |
| 6.525 | 0.555 | tINS | FF | 2 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s1/F |
| 6.762 | 0.237 | tNET | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_1_s/DI[1] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | SYM_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 773 | SYM_CLK_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_1_s/CLK |
| 10.828 | -0.035 | tSu | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_1_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 3.771, 63.926%; route: 1.896, 32.141%; tC2Q: 0.232, 3.933% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:| Slack | 4.066 |
| Data Arrival Time | 6.762 |
| Data Required Time | 10.828 |
| From | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0 |
| To | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_1_s |
| Launch Clk | SYM_CLK[R] |
| Latch Clk | SYM_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | SYM_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 773 | SYM_CLK_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 8 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s22/I1 |
| 1.887 | 0.555 | tINS | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s22/F |
| 2.124 | 0.237 | tNET | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s13/I1 |
| 2.679 | 0.555 | tINS | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s13/F |
| 2.916 | 0.237 | tNET | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s8/I1 |
| 3.471 | 0.555 | tINS | FF | 9 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s8/F |
| 3.708 | 0.237 | tNET | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_1_s4/I0 |
| 4.225 | 0.517 | tINS | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_1_s4/F |
| 4.462 | 0.237 | tNET | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_1_s2/I0 |
| 4.979 | 0.517 | tINS | FF | 3 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_1_s2/F |
| 5.216 | 0.237 | tNET | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s3/I0 |
| 5.733 | 0.517 | tINS | FF | 2 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s3/F |
| 5.970 | 0.237 | tNET | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_4_s1/I1 |
| 6.525 | 0.555 | tINS | FF | 2 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_4_s1/F |
| 6.762 | 0.237 | tNET | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_1_s/DI[0] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | SYM_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 773 | SYM_CLK_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_1_s/CLK |
| 10.828 | -0.035 | tSu | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_1_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 3.771, 63.926%; route: 1.896, 32.141%; tC2Q: 0.232, 3.933% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:| Slack | 4.066 |
| Data Arrival Time | 6.762 |
| Data Required Time | 10.828 |
| From | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0 |
| To | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_1_s |
| Launch Clk | SYM_CLK[R] |
| Latch Clk | SYM_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | SYM_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 773 | SYM_CLK_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 8 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s22/I1 |
| 1.887 | 0.555 | tINS | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s22/F |
| 2.124 | 0.237 | tNET | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s13/I1 |
| 2.679 | 0.555 | tINS | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s13/F |
| 2.916 | 0.237 | tNET | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s8/I1 |
| 3.471 | 0.555 | tINS | FF | 9 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s8/F |
| 3.708 | 0.237 | tNET | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_1_s4/I0 |
| 4.225 | 0.517 | tINS | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_1_s4/F |
| 4.462 | 0.237 | tNET | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_1_s2/I0 |
| 4.979 | 0.517 | tINS | FF | 3 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_1_s2/F |
| 5.216 | 0.237 | tNET | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s3/I0 |
| 5.733 | 0.517 | tINS | FF | 2 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s3/F |
| 5.970 | 0.237 | tNET | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s1/I1 |
| 6.525 | 0.555 | tINS | FF | 2 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s1/F |
| 6.762 | 0.237 | tNET | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_1_s/DI[1] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | SYM_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 773 | SYM_CLK_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_1_s/CLK |
| 10.828 | -0.035 | tSu | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_1_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 3.771, 63.926%; route: 1.896, 32.141%; tC2Q: 0.232, 3.933% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:| Slack | 4.066 |
| Data Arrival Time | 6.762 |
| Data Required Time | 10.828 |
| From | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0 |
| To | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_1_s |
| Launch Clk | SYM_CLK[R] |
| Latch Clk | SYM_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | SYM_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 773 | SYM_CLK_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 8 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_3_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s22/I1 |
| 1.887 | 0.555 | tINS | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s22/F |
| 2.124 | 0.237 | tNET | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s13/I1 |
| 2.679 | 0.555 | tINS | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s13/F |
| 2.916 | 0.237 | tNET | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s8/I1 |
| 3.471 | 0.555 | tINS | FF | 9 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s8/F |
| 3.708 | 0.237 | tNET | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_1_s4/I0 |
| 4.225 | 0.517 | tINS | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_1_s4/F |
| 4.462 | 0.237 | tNET | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_1_s2/I0 |
| 4.979 | 0.517 | tINS | FF | 3 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_1_s2/F |
| 5.216 | 0.237 | tNET | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s3/I0 |
| 5.733 | 0.517 | tINS | FF | 2 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_5_s3/F |
| 5.970 | 0.237 | tNET | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_4_s1/I1 |
| 6.525 | 0.555 | tINS | FF | 2 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_4_s1/F |
| 6.762 | 0.237 | tNET | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_1_s/DI[0] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | SYM_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 773 | SYM_CLK_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_1_s/CLK |
| 10.828 | -0.035 | tSu | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_0_1_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 3.771, 63.926%; route: 1.896, 32.141%; tC2Q: 0.232, 3.933% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:| Slack | 4.130 |
| Data Arrival Time | 6.698 |
| Data Required Time | 10.828 |
| From | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_6_s0 |
| To | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_0_s |
| Launch Clk | SYM_CLK[R] |
| Latch Clk | SYM_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | SYM_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 773 | SYM_CLK_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_6_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 9 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/Omega_v_d_6_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s15/I1 |
| 1.887 | 0.555 | tINS | FF | 3 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s15/F |
| 2.124 | 0.237 | tNET | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s11/I1 |
| 2.679 | 0.555 | tINS | FF | 7 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s11/F |
| 2.916 | 0.237 | tNET | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s5/I1 |
| 3.471 | 0.555 | tINS | FF | 5 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_7_s5/F |
| 3.708 | 0.237 | tNET | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s17/I1 |
| 4.263 | 0.555 | tINS | FF | 2 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s17/F |
| 4.500 | 0.237 | tNET | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s6/I2 |
| 4.953 | 0.453 | tINS | FF | 2 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s6/F |
| 5.190 | 0.237 | tNET | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s3/I0 |
| 5.707 | 0.517 | tINS | FF | 4 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_0_s3/F |
| 5.944 | 0.237 | tNET | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_3_s1/I0 |
| 6.461 | 0.517 | tINS | FF | 2 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_data_3_s1/F |
| 6.698 | 0.237 | tNET | FF | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_0_s/DI[3] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | SYM_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 773 | SYM_CLK_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_0_s/CLK |
| 10.828 | -0.035 | tSu | 1 | RS_Decoder_Top/RS_Decoder/RS_Error_Locator/error_mem_error_mem_1_0_s |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 3.707, 63.530%; route: 1.896, 32.494%; tC2Q: 0.232, 3.976% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |