Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\USB_DEVICE_CONTROLLER\data\usb_device_controller_top.v
C:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\USB_DEVICE_CONTROLLER\data\usb_device_controller.v
GowinSynthesis Constraints File ---
Version GowinSynthesis V1.9.8.07
Part Number GW2AR-LV18QN88C7/I6
Device GW2AR-18C
Created Time Fri Jul 22 01:59:16 2022
Legal Announcement Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module USB_Device_Controller_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.562s, Elapsed time = 0h 0m 1s, Peak memory usage = 37.219MB
Running netlist conversion:
    CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.079s, Peak memory usage = 37.219MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.414s, Peak memory usage = 37.219MB
    Optimizing Phase 1: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.191s, Peak memory usage = 37.219MB
    Optimizing Phase 2: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.501s, Peak memory usage = 37.219MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.075s, Peak memory usage = 37.219MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 37.219MB
    Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.046s, Peak memory usage = 37.219MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 37.219MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.377s, Peak memory usage = 37.219MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.164s, Peak memory usage = 37.219MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.16s, Peak memory usage = 37.219MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 21s, Elapsed time = 0h 0m 26s, Peak memory usage = 52.645MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.419s, Peak memory usage = 52.645MB
Generate output files:
    CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.44s, Peak memory usage = 52.645MB
Total Time and Memory Usage CPU time = 0h 0m 23s, Elapsed time = 0h 0m 29s, Peak memory usage = 52.645MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 436
I/O Buf 432
    IBUF 344
    OBUF 88
Register 497
    DFF 17
    DFFE 111
    DFFS 5
    DFFSE 33
    DFFR 56
    DFFRE 223
    DFFC 10
    DFFCE 42
LUT 1517
    LUT2 186
    LUT3 465
    LUT4 866
ALU 113
    ALU 113
INV 1
    INV 1

Resource Utilization Summary

Resource Usage Utilization
Logic 1631(1518 LUTs, 113 ALUs) / 20736 8%
Register 497 / 15750 3%
  --Register as Latch 0 / 15750 0%
  --Register as FF 497 / 15750 3%
BSRAM 0 / 46 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk_i Base 10.000 100.0 0.000 5.000 clk_i_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk_i 100.0(MHz) 90.1(MHz) 13 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -1.102
Data Arrival Time 12.136
Data Required Time 11.034
From u_usb_device_controller/usb_control_inst/s_desctyp_5_s0
To u_usb_device_controller/usb_control_inst/s_answerptr_5_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.853 0.853 tINS RR 497 clk_i_ibuf/O
1.078 0.225 tNET RR 1 u_usb_device_controller/usb_control_inst/s_desctyp_5_s0/CLK
1.368 0.290 tC2Q RF 10 u_usb_device_controller/usb_control_inst/s_desctyp_5_s0/Q
1.664 0.296 tNET FF 1 u_usb_device_controller/usbc_dsclen_15_s14/I1
2.358 0.694 tINS FF 11 u_usb_device_controller/usbc_dsclen_15_s14/F
2.654 0.296 tNET FF 1 u_usb_device_controller/usbc_dsclen_12_s11/I2
3.221 0.566 tINS FF 11 u_usb_device_controller/usbc_dsclen_12_s11/F
3.517 0.296 tNET FF 1 u_usb_device_controller/usbc_dsclen_14_s18/I2
4.083 0.566 tINS FF 2 u_usb_device_controller/usbc_dsclen_14_s18/F
4.379 0.296 tNET FF 1 u_usb_device_controller/usbc_dsclen_13_s12/I0
5.026 0.646 tINS FF 1 u_usb_device_controller/usbc_dsclen_13_s12/F
5.322 0.296 tNET FF 1 u_usb_device_controller/usbc_dsclen_13_s10/I0
5.968 0.646 tINS FF 2 u_usb_device_controller/usbc_dsclen_13_s10/F
6.264 0.296 tNET FF 1 u_usb_device_controller/usbc_dsclen_13_s8/I2
6.831 0.566 tINS FF 1 u_usb_device_controller/usbc_dsclen_13_s8/F
7.127 0.296 tNET FF 2 u_usb_device_controller/usb_control_inst/n1482_s0/I1
7.839 0.712 tINS FR 1 u_usb_device_controller/usb_control_inst/n1482_s0/COUT
7.839 0.000 tNET RR 2 u_usb_device_controller/usb_control_inst/n1483_s0/CIN
7.883 0.044 tINS RF 1 u_usb_device_controller/usb_control_inst/n1483_s0/COUT
7.883 0.000 tNET FF 2 u_usb_device_controller/usb_control_inst/n1484_s0/CIN
7.927 0.044 tINS FF 5 u_usb_device_controller/usb_control_inst/n1484_s0/COUT
8.224 0.296 tNET FF 1 u_usb_device_controller/usb_control_inst/n1748_s41/I1
8.917 0.694 tINS FF 1 u_usb_device_controller/usb_control_inst/n1748_s41/F
9.214 0.296 tNET FF 1 u_usb_device_controller/usb_control_inst/n1748_s39/I0
9.860 0.646 tINS FF 2 u_usb_device_controller/usb_control_inst/n1748_s39/F
10.156 0.296 tNET FF 1 u_usb_device_controller/usb_control_inst/n1723_s13/I1
10.850 0.694 tINS FF 2 u_usb_device_controller/usb_control_inst/n1723_s13/F
11.146 0.296 tNET FF 1 u_usb_device_controller/usb_control_inst/n1723_s11/I1
11.840 0.694 tINS FF 1 u_usb_device_controller/usb_control_inst/n1723_s11/F
12.136 0.296 tNET FF 1 u_usb_device_controller/usb_control_inst/s_answerptr_5_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_i
10.000 0.000 tCL RR 1 clk_i_ibuf/I
10.853 0.853 tINS RR 497 clk_i_ibuf/O
11.078 0.225 tNET RR 1 u_usb_device_controller/usb_control_inst/s_answerptr_5_s0/CLK
11.034 -0.044 tSu 1 u_usb_device_controller/usb_control_inst/s_answerptr_5_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 13
Arrival Clock Path Delay: cell: 0.853, 79.130%; route: 0.225, 20.870%
Arrival Data Path Delay: cell: 7.213, 65.228%; route: 3.555, 32.149%; tC2Q: 0.290, 2.623%
Required Clock Path Delay: cell: 0.853, 79.130%; route: 0.225, 20.870%

Path 2

Path Summary:
Slack -1.007
Data Arrival Time 12.041
Data Required Time 11.034
From u_usb_device_controller/usb_control_inst/s_desctyp_5_s0
To u_usb_device_controller/usb_control_inst/s_answerptr_2_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.853 0.853 tINS RR 497 clk_i_ibuf/O
1.078 0.225 tNET RR 1 u_usb_device_controller/usb_control_inst/s_desctyp_5_s0/CLK
1.368 0.290 tC2Q RF 10 u_usb_device_controller/usb_control_inst/s_desctyp_5_s0/Q
1.664 0.296 tNET FF 1 u_usb_device_controller/usbc_dsclen_15_s14/I1
2.358 0.694 tINS FF 11 u_usb_device_controller/usbc_dsclen_15_s14/F
2.654 0.296 tNET FF 1 u_usb_device_controller/usbc_dsclen_12_s11/I2
3.221 0.566 tINS FF 11 u_usb_device_controller/usbc_dsclen_12_s11/F
3.517 0.296 tNET FF 1 u_usb_device_controller/usbc_dsclen_14_s18/I2
4.083 0.566 tINS FF 2 u_usb_device_controller/usbc_dsclen_14_s18/F
4.379 0.296 tNET FF 1 u_usb_device_controller/usbc_dsclen_13_s12/I0
5.026 0.646 tINS FF 1 u_usb_device_controller/usbc_dsclen_13_s12/F
5.322 0.296 tNET FF 1 u_usb_device_controller/usbc_dsclen_13_s10/I0
5.968 0.646 tINS FF 2 u_usb_device_controller/usbc_dsclen_13_s10/F
6.264 0.296 tNET FF 1 u_usb_device_controller/usbc_dsclen_13_s8/I2
6.831 0.566 tINS FF 1 u_usb_device_controller/usbc_dsclen_13_s8/F
7.127 0.296 tNET FF 2 u_usb_device_controller/usb_control_inst/n1482_s0/I1
7.839 0.712 tINS FR 1 u_usb_device_controller/usb_control_inst/n1482_s0/COUT
7.839 0.000 tNET RR 2 u_usb_device_controller/usb_control_inst/n1483_s0/CIN
7.883 0.044 tINS RF 1 u_usb_device_controller/usb_control_inst/n1483_s0/COUT
7.883 0.000 tNET FF 2 u_usb_device_controller/usb_control_inst/n1484_s0/CIN
7.927 0.044 tINS FF 5 u_usb_device_controller/usb_control_inst/n1484_s0/COUT
8.224 0.296 tNET FF 1 u_usb_device_controller/usb_control_inst/n1729_s19/I1
8.917 0.694 tINS FF 3 u_usb_device_controller/usb_control_inst/n1729_s19/F
9.214 0.296 tNET FF 1 u_usb_device_controller/usb_control_inst/n1732_s16/I0
9.860 0.646 tINS FF 1 u_usb_device_controller/usb_control_inst/n1732_s16/F
10.156 0.296 tNET FF 1 u_usb_device_controller/usb_control_inst/n1732_s12/I0
10.802 0.646 tINS FF 1 u_usb_device_controller/usb_control_inst/n1732_s12/F
11.099 0.296 tNET FF 1 u_usb_device_controller/usb_control_inst/n1732_s15/I0
11.745 0.646 tINS FF 1 u_usb_device_controller/usb_control_inst/n1732_s15/F
12.041 0.296 tNET FF 1 u_usb_device_controller/usb_control_inst/s_answerptr_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_i
10.000 0.000 tCL RR 1 clk_i_ibuf/I
10.853 0.853 tINS RR 497 clk_i_ibuf/O
11.078 0.225 tNET RR 1 u_usb_device_controller/usb_control_inst/s_answerptr_2_s0/CLK
11.034 -0.044 tSu 1 u_usb_device_controller/usb_control_inst/s_answerptr_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 13
Arrival Clock Path Delay: cell: 0.853, 79.130%; route: 0.225, 20.870%
Arrival Data Path Delay: cell: 7.118, 64.928%; route: 3.555, 32.427%; tC2Q: 0.290, 2.645%
Required Clock Path Delay: cell: 0.853, 79.130%; route: 0.225, 20.870%

Path 3

Path Summary:
Slack -0.974
Data Arrival Time 12.009
Data Required Time 11.034
From u_usb_device_controller/usb_control_inst/s_desctyp_5_s0
To u_usb_device_controller/usb_control_inst/s_answerptr_0_s0
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.853 0.853 tINS RR 497 clk_i_ibuf/O
1.078 0.225 tNET RR 1 u_usb_device_controller/usb_control_inst/s_desctyp_5_s0/CLK
1.368 0.290 tC2Q RF 10 u_usb_device_controller/usb_control_inst/s_desctyp_5_s0/Q
1.664 0.296 tNET FF 1 u_usb_device_controller/usbc_dsclen_15_s14/I1
2.358 0.694 tINS FF 11 u_usb_device_controller/usbc_dsclen_15_s14/F
2.654 0.296 tNET FF 1 u_usb_device_controller/usbc_dsclen_12_s11/I2
3.221 0.566 tINS FF 11 u_usb_device_controller/usbc_dsclen_12_s11/F
3.517 0.296 tNET FF 1 u_usb_device_controller/usbc_dsclen_14_s18/I2
4.083 0.566 tINS FF 2 u_usb_device_controller/usbc_dsclen_14_s18/F
4.379 0.296 tNET FF 1 u_usb_device_controller/usbc_dsclen_13_s12/I0
5.026 0.646 tINS FF 1 u_usb_device_controller/usbc_dsclen_13_s12/F
5.322 0.296 tNET FF 1 u_usb_device_controller/usbc_dsclen_13_s10/I0
5.968 0.646 tINS FF 2 u_usb_device_controller/usbc_dsclen_13_s10/F
6.264 0.296 tNET FF 1 u_usb_device_controller/usbc_dsclen_13_s8/I2
6.831 0.566 tINS FF 1 u_usb_device_controller/usbc_dsclen_13_s8/F
7.127 0.296 tNET FF 2 u_usb_device_controller/usb_control_inst/n1482_s0/I1
7.839 0.712 tINS FR 1 u_usb_device_controller/usb_control_inst/n1482_s0/COUT
7.839 0.000 tNET RR 2 u_usb_device_controller/usb_control_inst/n1483_s0/CIN
7.883 0.044 tINS RF 1 u_usb_device_controller/usb_control_inst/n1483_s0/COUT
7.883 0.000 tNET FF 2 u_usb_device_controller/usb_control_inst/n1484_s0/CIN
7.927 0.044 tINS FF 5 u_usb_device_controller/usb_control_inst/n1484_s0/COUT
8.224 0.296 tNET FF 1 u_usb_device_controller/usb_control_inst/n1748_s41/I1
8.917 0.694 tINS FF 1 u_usb_device_controller/usb_control_inst/n1748_s41/F
9.214 0.296 tNET FF 1 u_usb_device_controller/usb_control_inst/n1748_s39/I0
9.860 0.646 tINS FF 2 u_usb_device_controller/usb_control_inst/n1748_s39/F
10.156 0.296 tNET FF 1 u_usb_device_controller/usb_control_inst/n1723_s13/I1
10.850 0.694 tINS FF 2 u_usb_device_controller/usb_control_inst/n1723_s13/F
11.146 0.296 tNET FF 1 u_usb_device_controller/usb_control_inst/n1738_s12/I2
11.712 0.566 tINS FF 1 u_usb_device_controller/usb_control_inst/n1738_s12/F
12.009 0.296 tNET FF 1 u_usb_device_controller/usb_control_inst/s_answerptr_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_i
10.000 0.000 tCL RR 1 clk_i_ibuf/I
10.853 0.853 tINS RR 497 clk_i_ibuf/O
11.078 0.225 tNET RR 1 u_usb_device_controller/usb_control_inst/s_answerptr_0_s0/CLK
11.034 -0.044 tSu 1 u_usb_device_controller/usb_control_inst/s_answerptr_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 13
Arrival Clock Path Delay: cell: 0.853, 79.130%; route: 0.225, 20.870%
Arrival Data Path Delay: cell: 7.086, 64.823%; route: 3.555, 32.524%; tC2Q: 0.290, 2.653%
Required Clock Path Delay: cell: 0.853, 79.130%; route: 0.225, 20.870%

Path 4

Path Summary:
Slack -0.744
Data Arrival Time 11.779
Data Required Time 11.034
From u_usb_device_controller/usb_control_inst/s_desctyp_5_s0
To u_usb_device_controller/usb_control_inst/s_state_9_s2
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.853 0.853 tINS RR 497 clk_i_ibuf/O
1.078 0.225 tNET RR 1 u_usb_device_controller/usb_control_inst/s_desctyp_5_s0/CLK
1.368 0.290 tC2Q RF 10 u_usb_device_controller/usb_control_inst/s_desctyp_5_s0/Q
1.664 0.296 tNET FF 1 u_usb_device_controller/usbc_dsclen_15_s14/I1
2.358 0.694 tINS FF 11 u_usb_device_controller/usbc_dsclen_15_s14/F
2.654 0.296 tNET FF 1 u_usb_device_controller/usbc_dsclen_12_s11/I2
3.221 0.566 tINS FF 11 u_usb_device_controller/usbc_dsclen_12_s11/F
3.517 0.296 tNET FF 1 u_usb_device_controller/usbc_dsclen_14_s18/I2
4.083 0.566 tINS FF 2 u_usb_device_controller/usbc_dsclen_14_s18/F
4.379 0.296 tNET FF 1 u_usb_device_controller/usbc_dsclen_13_s12/I0
5.026 0.646 tINS FF 1 u_usb_device_controller/usbc_dsclen_13_s12/F
5.322 0.296 tNET FF 1 u_usb_device_controller/usbc_dsclen_13_s10/I0
5.968 0.646 tINS FF 2 u_usb_device_controller/usbc_dsclen_13_s10/F
6.264 0.296 tNET FF 1 u_usb_device_controller/usbc_dsclen_13_s8/I2
6.831 0.566 tINS FF 1 u_usb_device_controller/usbc_dsclen_13_s8/F
7.127 0.296 tNET FF 2 u_usb_device_controller/usb_control_inst/n1482_s0/I1
7.839 0.712 tINS FR 1 u_usb_device_controller/usb_control_inst/n1482_s0/COUT
7.839 0.000 tNET RR 2 u_usb_device_controller/usb_control_inst/n1483_s0/CIN
7.883 0.044 tINS RF 1 u_usb_device_controller/usb_control_inst/n1483_s0/COUT
7.883 0.000 tNET FF 2 u_usb_device_controller/usb_control_inst/n1484_s0/CIN
7.927 0.044 tINS FF 5 u_usb_device_controller/usb_control_inst/n1484_s0/COUT
8.224 0.296 tNET FF 1 u_usb_device_controller/usb_control_inst/n1729_s19/I1
8.917 0.694 tINS FF 3 u_usb_device_controller/usb_control_inst/n1729_s19/F
9.214 0.296 tNET FF 1 u_usb_device_controller/usb_control_inst/n1746_s48/I3
9.677 0.464 tINS FF 1 u_usb_device_controller/usb_control_inst/n1746_s48/F
9.974 0.296 tNET FF 1 u_usb_device_controller/usb_control_inst/n1746_s43/I0
10.620 0.646 tINS FF 1 u_usb_device_controller/usb_control_inst/n1746_s43/F
10.916 0.296 tNET FF 1 u_usb_device_controller/usb_control_inst/n1746_s40/I2
11.482 0.566 tINS FF 1 u_usb_device_controller/usb_control_inst/n1746_s40/F
11.779 0.296 tNET FF 1 u_usb_device_controller/usb_control_inst/s_state_9_s2/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_i
10.000 0.000 tCL RR 1 clk_i_ibuf/I
10.853 0.853 tINS RR 497 clk_i_ibuf/O
11.078 0.225 tNET RR 1 u_usb_device_controller/usb_control_inst/s_state_9_s2/CLK
11.034 -0.044 tSu 1 u_usb_device_controller/usb_control_inst/s_state_9_s2
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 13
Arrival Clock Path Delay: cell: 0.853, 79.130%; route: 0.225, 20.870%
Arrival Data Path Delay: cell: 6.856, 64.067%; route: 3.555, 33.223%; tC2Q: 0.290, 2.710%
Required Clock Path Delay: cell: 0.853, 79.130%; route: 0.225, 20.870%

Path 5

Path Summary:
Slack -0.023
Data Arrival Time 11.057
Data Required Time 11.034
From u_usb_device_controller/usb_transact_inst/s_state_10_s1
To u_usb_device_controller/usb_transact_inst/s_sendpid_1_s2
Launch Clk clk_i[R]
Latch Clk clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_i
0.000 0.000 tCL RR 1 clk_i_ibuf/I
0.853 0.853 tINS RR 497 clk_i_ibuf/O
1.078 0.225 tNET RR 1 u_usb_device_controller/usb_transact_inst/s_state_10_s1/CLK
1.368 0.290 tC2Q RF 6 u_usb_device_controller/usb_transact_inst/s_state_10_s1/Q
1.664 0.296 tNET FF 1 u_usb_device_controller/usb_transact_inst/n1090_s48/I1
2.358 0.694 tINS FF 1 u_usb_device_controller/usb_transact_inst/n1090_s48/F
2.654 0.296 tNET FF 1 u_usb_device_controller/usb_transact_inst/n1090_s47/I1
3.348 0.694 tINS FF 3 u_usb_device_controller/usb_transact_inst/n1090_s47/F
3.644 0.296 tNET FF 1 u_usb_device_controller/usb_transact_inst/T_PING_s3/I1
4.338 0.694 tINS FF 12 u_usb_device_controller/usb_transact_inst/T_PING_s3/F
4.634 0.296 tNET FF 1 u_usb_device_controller/usb_transact_inst/T_PING_s6/I1
5.328 0.694 tINS FF 1 u_usb_device_controller/usb_transact_inst/T_PING_s6/F
5.624 0.296 tNET FF 1 u_usb_device_controller/n1559_s4/I3
6.088 0.464 tINS FF 4 u_usb_device_controller/n1559_s4/F
6.384 0.296 tNET FF 1 u_usb_device_controller/n1560_s7/I1
7.078 0.694 tINS FF 2 u_usb_device_controller/n1560_s7/F
7.374 0.296 tNET FF 1 u_usb_device_controller/usb_transact_inst/s_sendpid_3_s9/I1
8.068 0.694 tINS FF 2 u_usb_device_controller/usb_transact_inst/s_sendpid_3_s9/F
8.364 0.296 tNET FF 1 u_usb_device_controller/usb_transact_inst/s_sendpid_3_s6/I0
9.011 0.646 tINS FF 5 u_usb_device_controller/usb_transact_inst/s_sendpid_3_s6/F
9.307 0.296 tNET FF 1 u_usb_device_controller/usb_transact_inst/s_sendpid_3_s4/I1
10.001 0.694 tINS FF 4 u_usb_device_controller/usb_transact_inst/s_sendpid_3_s4/F
10.297 0.296 tNET FF 1 u_usb_device_controller/usb_transact_inst/n1161_s11/I3
10.761 0.464 tINS FF 1 u_usb_device_controller/usb_transact_inst/n1161_s11/F
11.057 0.296 tNET FF 1 u_usb_device_controller/usb_transact_inst/s_sendpid_1_s2/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk_i
10.000 0.000 tCL RR 1 clk_i_ibuf/I
10.853 0.853 tINS RR 497 clk_i_ibuf/O
11.078 0.225 tNET RR 1 u_usb_device_controller/usb_transact_inst/s_sendpid_1_s2/CLK
11.034 -0.044 tSu 1 u_usb_device_controller/usb_transact_inst/s_sendpid_1_s2
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 11
Arrival Clock Path Delay: cell: 0.853, 79.130%; route: 0.225, 20.870%
Arrival Data Path Delay: cell: 6.430, 64.437%; route: 3.259, 32.657%; tC2Q: 0.290, 2.906%
Required Clock Path Delay: cell: 0.853, 79.130%; route: 0.225, 20.870%