Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\VFB\data\vfb_top.v
C:\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\VFB\data\vfb_wrapper.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.01 (64-bit)
Part Number GW2AR-LV18EQ144C8/I7
Device GW2AR-18
Device Version C
Created Time Wed Jan 10 09:24:35 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Video_Frame_Buffer_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.179s, Peak memory usage = 42.438MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 42.438MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.026s, Peak memory usage = 42.438MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 42.438MB
    Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 42.438MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 42.438MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 42.438MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 42.438MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 42.438MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.032s, Peak memory usage = 42.438MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 42.438MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 42.438MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 72.469MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.097s, Peak memory usage = 72.469MB
Generate output files:
    CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.066s, Peak memory usage = 72.469MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 72.469MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 163
I/O Buf 163
    IBUF 69
    OBUF 94
Register 497
    DFFS 8
    DFFR 2
    DFFP 20
    DFFPE 2
    DFFC 353
    DFFCE 112
LUT 590
    LUT2 103
    LUT3 201
    LUT4 286
ALU 46
    ALU 46
INV 5
    INV 5
BSRAM 8
    SDPB 8

Resource Utilization Summary

Resource Usage Utilization
Logic 641(595 LUT, 46 ALU) / 20736 4%
Register 497 / 15912 4%
  --Register as Latch 0 / 15912 0%
  --Register as FF 497 / 15912 4%
BSRAM 8 / 46 18%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
I_vin0_clk Base 10.000 100.0 0.000 5.000 I_vin0_clk_ibuf/I
I_dma_clk Base 10.000 100.0 0.000 5.000 I_dma_clk_ibuf/I
I_vout0_clk Base 10.000 100.0 0.000 5.000 I_vout0_clk_ibuf/I
vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n38_6 Base 10.000 100.0 0.000 5.000 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n38_s2/O
vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n43_6 Base 10.000 100.0 0.000 5.000 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n43_s2/O
vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n38_6_0 Base 10.000 100.0 0.000 5.000 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n38_s2/O

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_vin0_clk 100.0(MHz) 229.9(MHz) 6 TOP
2 I_dma_clk 100.0(MHz) 175.1(MHz) 9 TOP
3 I_vout0_clk 100.0(MHz) 173.6(MHz) 9 TOP
4 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n38_6 100.0(MHz) 1984.1(MHz) 1 TOP
5 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n43_6 100.0(MHz) 1984.1(MHz) 1 TOP
6 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n38_6_0 100.0(MHz) 1984.1(MHz) 1 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 4.240
Data Arrival Time 6.587
Data Required Time 10.828
From vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_1_s0
To vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0
Launch Clk I_vout0_clk[R]
Latch Clk I_vout0_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_vout0_clk
0.000 0.000 tCL RR 1 I_vout0_clk_ibuf/I
0.683 0.683 tINS RR 127 I_vout0_clk_ibuf/O
0.863 0.180 tNET RR 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_1_s0/CLK
1.095 0.232 tC2Q RF 4 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_1_s0/Q
1.332 0.237 tNET FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_2_s4/I1
1.887 0.555 tINS FF 7 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_2_s4/F
2.124 0.237 tNET FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_5_s4/I3
2.495 0.371 tINS FF 7 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_5_s4/F
2.732 0.237 tNET FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_6_s4/I1
3.287 0.555 tINS FF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_6_s4/F
3.524 0.237 tNET FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_8_s3/I2
3.977 0.453 tINS FF 3 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_8_s3/F
4.214 0.237 tNET FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rgraynext_7_s0/I1
4.769 0.555 tINS FF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rgraynext_7_s0/F
5.006 0.237 tNET FF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n242_s0/I0
5.555 0.549 tINS FR 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n242_s0/COUT
5.555 0.000 tNET RR 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n243_s0/CIN
5.590 0.035 tINS RF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n243_s0/COUT
5.590 0.000 tNET FF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n244_s0/CIN
5.625 0.035 tINS FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n244_s0/COUT
5.625 0.000 tNET FF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n245_s0/CIN
5.660 0.035 tINS FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n245_s0/COUT
5.897 0.237 tNET FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rempty_val_s1/I2
6.350 0.453 tINS FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rempty_val_s1/F
6.587 0.237 tNET FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_vout0_clk
10.000 0.000 tCL RR 1 I_vout0_clk_ibuf/I
10.682 0.683 tINS RR 127 I_vout0_clk_ibuf/O
10.863 0.180 tNET RR 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0/CLK
10.828 -0.035 tSu 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.597, 62.827%; route: 1.896, 33.120%; tC2Q: 0.232, 4.053%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 4.290
Data Arrival Time 6.538
Data Required Time 10.828
From vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0
To vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0
Launch Clk I_dma_clk[R]
Latch Clk I_dma_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_dma_clk
0.000 0.000 tCL RR 1 I_dma_clk_ibuf/I
0.683 0.683 tINS RR 241 I_dma_clk_ibuf/O
0.863 0.180 tNET RR 1 vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/CLK
1.095 0.232 tC2Q RF 23 vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q
1.332 0.237 tNET FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_en_s0/I1
1.887 0.555 tINS FF 28 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_en_s0/F
2.124 0.237 tNET FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s4/I3
2.495 0.371 tINS FF 8 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s4/F
2.732 0.237 tNET FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/I3
3.103 0.371 tINS FF 11 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/F
3.340 0.237 tNET FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_6_s3/I1
3.895 0.555 tINS FF 4 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_6_s3/F
4.132 0.237 tNET FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rgraynext_5_s1/I0
4.649 0.517 tINS FF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rgraynext_5_s1/F
4.886 0.237 tNET FF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n239_s0/I0
5.435 0.549 tINS FR 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n239_s0/COUT
5.435 0.000 tNET RR 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n240_s0/CIN
5.470 0.035 tINS RF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n240_s0/COUT
5.470 0.000 tNET FF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n241_s0/CIN
5.505 0.035 tINS FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n241_s0/COUT
5.505 0.000 tNET FF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n242_s0/CIN
5.540 0.035 tINS FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n242_s0/COUT
5.540 0.000 tNET FF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n243_s0/CIN
5.575 0.035 tINS FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n243_s0/COUT
5.575 0.000 tNET FF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n244_s0/CIN
5.611 0.035 tINS FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n244_s0/COUT
5.848 0.237 tNET FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rempty_val_s1/I2
6.301 0.453 tINS FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rempty_val_s1/F
6.538 0.237 tNET FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_dma_clk
10.000 0.000 tCL RR 1 I_dma_clk_ibuf/I
10.682 0.683 tINS RR 241 I_dma_clk_ibuf/O
10.863 0.180 tNET RR 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0/CLK
10.828 -0.035 tSu 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 9
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.547, 62.502%; route: 1.896, 33.410%; tC2Q: 0.232, 4.088%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack 5.102
Data Arrival Time 5.725
Data Required Time 10.828
From vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq2_rptr_9_s1
To vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Wnum_11_s0
Launch Clk I_dma_clk[R]
Latch Clk I_dma_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_dma_clk
0.000 0.000 tCL RR 1 I_dma_clk_ibuf/I
0.683 0.683 tINS RR 241 I_dma_clk_ibuf/O
0.863 0.180 tNET RR 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq2_rptr_9_s1/CLK
1.095 0.232 tC2Q RF 3 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq2_rptr_9_s1/Q
1.332 0.237 tNET FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rcount_w_8_s1/I1
1.887 0.555 tINS FF 4 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rcount_w_8_s1/F
2.124 0.237 tNET FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rcount_w_5_s0/I3
2.495 0.371 tINS FF 4 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rcount_w_5_s0/F
2.732 0.237 tNET FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rcount_w_2_s0/I3
3.103 0.371 tINS FF 3 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rcount_w_2_s0/F
3.340 0.237 tNET FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rcount_w_1_s0/I1
3.895 0.555 tINS FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rcount_w_1_s0/F
4.132 0.237 tNET FF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_1_s/I1
4.702 0.570 tINS FR 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_1_s/COUT
4.702 0.000 tNET RR 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_2_s/CIN
4.737 0.035 tINS RF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_2_s/COUT
4.737 0.000 tNET FF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_3_s/CIN
4.772 0.035 tINS FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_3_s/COUT
4.772 0.000 tNET FF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_4_s/CIN
4.807 0.035 tINS FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_4_s/COUT
4.807 0.000 tNET FF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_5_s/CIN
4.842 0.035 tINS FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_5_s/COUT
4.842 0.000 tNET FF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_6_s/CIN
4.878 0.035 tINS FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_6_s/COUT
4.878 0.000 tNET FF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_7_s/CIN
4.913 0.035 tINS FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_7_s/COUT
4.913 0.000 tNET FF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_8_s/CIN
4.948 0.035 tINS FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_8_s/COUT
4.948 0.000 tNET FF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_9_s/CIN
4.983 0.035 tINS FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_9_s/COUT
4.983 0.000 tNET FF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_10_s/CIN
5.018 0.035 tINS FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_10_s/COUT
5.018 0.000 tNET FF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_11_s/CIN
5.488 0.470 tINS FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_11_s/SUM
5.725 0.237 tNET FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Wnum_11_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_dma_clk
10.000 0.000 tCL RR 1 I_dma_clk_ibuf/I
10.682 0.683 tINS RR 241 I_dma_clk_ibuf/O
10.863 0.180 tNET RR 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Wnum_11_s0/CLK
10.828 -0.035 tSu 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Wnum_11_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.209, 65.987%; route: 1.422, 29.242%; tC2Q: 0.232, 4.771%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 5.123
Data Arrival Time 5.704
Data Required Time 10.828
From vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq2_wptr_8_s1
To vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_11_s0
Launch Clk I_dma_clk[R]
Latch Clk I_dma_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_dma_clk
0.000 0.000 tCL RR 1 I_dma_clk_ibuf/I
0.683 0.683 tINS RR 241 I_dma_clk_ibuf/O
0.863 0.180 tNET RR 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq2_wptr_8_s1/CLK
1.095 0.232 tC2Q RF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rq2_wptr_8_s1/Q
1.332 0.237 tNET FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.wcount_r_8_s1/I1
1.887 0.555 tINS FF 4 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.wcount_r_8_s1/F
2.124 0.237 tNET FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.wcount_r_5_s0/I3
2.495 0.371 tINS FF 4 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.wcount_r_5_s0/F
2.732 0.237 tNET FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.wcount_r_2_s0/I3
3.103 0.371 tINS FF 3 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.wcount_r_2_s0/F
3.340 0.237 tNET FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.wcount_r_1_s0/I1
3.895 0.555 tINS FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.wcount_r_1_s0/F
4.132 0.237 tNET FF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_1_s/I0
4.681 0.549 tINS FR 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_1_s/COUT
4.681 0.000 tNET RR 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_2_s/CIN
4.716 0.035 tINS RF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_2_s/COUT
4.716 0.000 tNET FF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_3_s/CIN
4.751 0.035 tINS FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_3_s/COUT
4.751 0.000 tNET FF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_4_s/CIN
4.786 0.035 tINS FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_4_s/COUT
4.786 0.000 tNET FF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_5_s/CIN
4.821 0.035 tINS FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_5_s/COUT
4.821 0.000 tNET FF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_6_s/CIN
4.857 0.035 tINS FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_6_s/COUT
4.857 0.000 tNET FF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_7_s/CIN
4.892 0.035 tINS FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_7_s/COUT
4.892 0.000 tNET FF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_8_s/CIN
4.927 0.035 tINS FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_8_s/COUT
4.927 0.000 tNET FF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_9_s/CIN
4.962 0.035 tINS FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_9_s/COUT
4.962 0.000 tNET FF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_10_s/CIN
4.997 0.035 tINS FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_10_s/COUT
4.997 0.000 tNET FF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_11_s/CIN
5.467 0.470 tINS FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rcnt_sub_11_s/SUM
5.704 0.237 tNET FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_11_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_dma_clk
10.000 0.000 tCL RR 1 I_dma_clk_ibuf/I
10.682 0.683 tINS RR 241 I_dma_clk_ibuf/O
10.863 0.180 tNET RR 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_11_s0/CLK
10.828 -0.035 tSu 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_11_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.188, 65.839%; route: 1.422, 29.369%; tC2Q: 0.232, 4.792%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack 5.137
Data Arrival Time 5.690
Data Required Time 10.828
From vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq2_rptr_9_s1
To vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Wnum_10_s0
Launch Clk I_dma_clk[R]
Latch Clk I_dma_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_dma_clk
0.000 0.000 tCL RR 1 I_dma_clk_ibuf/I
0.683 0.683 tINS RR 241 I_dma_clk_ibuf/O
0.863 0.180 tNET RR 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq2_rptr_9_s1/CLK
1.095 0.232 tC2Q RF 3 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.wq2_rptr_9_s1/Q
1.332 0.237 tNET FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rcount_w_8_s1/I1
1.887 0.555 tINS FF 4 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rcount_w_8_s1/F
2.124 0.237 tNET FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rcount_w_5_s0/I3
2.495 0.371 tINS FF 4 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rcount_w_5_s0/F
2.732 0.237 tNET FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rcount_w_2_s0/I3
3.103 0.371 tINS FF 3 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rcount_w_2_s0/F
3.340 0.237 tNET FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rcount_w_1_s0/I1
3.895 0.555 tINS FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Equal.rcount_w_1_s0/F
4.132 0.237 tNET FF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_1_s/I1
4.702 0.570 tINS FR 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_1_s/COUT
4.702 0.000 tNET RR 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_2_s/CIN
4.737 0.035 tINS RF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_2_s/COUT
4.737 0.000 tNET FF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_3_s/CIN
4.772 0.035 tINS FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_3_s/COUT
4.772 0.000 tNET FF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_4_s/CIN
4.807 0.035 tINS FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_4_s/COUT
4.807 0.000 tNET FF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_5_s/CIN
4.842 0.035 tINS FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_5_s/COUT
4.842 0.000 tNET FF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_6_s/CIN
4.878 0.035 tINS FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_6_s/COUT
4.878 0.000 tNET FF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_7_s/CIN
4.913 0.035 tINS FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_7_s/COUT
4.913 0.000 tNET FF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_8_s/CIN
4.948 0.035 tINS FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_8_s/COUT
4.948 0.000 tNET FF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_9_s/CIN
4.983 0.035 tINS FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_9_s/COUT
4.983 0.000 tNET FF 2 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_10_s/CIN
5.453 0.470 tINS FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wcnt_sub_10_s/SUM
5.690 0.237 tNET FF 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Wnum_10_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_dma_clk
10.000 0.000 tCL RR 1 I_dma_clk_ibuf/I
10.682 0.683 tINS RR 241 I_dma_clk_ibuf/O
10.863 0.180 tNET RR 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Wnum_10_s0/CLK
10.828 -0.035 tSu 1 vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Wnum_10_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 8
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 3.174, 65.738%; route: 1.422, 29.456%; tC2Q: 0.232, 4.806%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%