Timing Messages
| Report Title | Timing Analysis Report |
| Design File | E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_SDRAM_RefDesign\project\impl\gwsynthesis\dk_video.vg |
| Physical Constraints File | E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_SDRAM_RefDesign\project\src\dk_video.cst |
| Timing Constraint File | E:\myWork\IP\releaseVerify\version\1.9.9.01\Gowin_Video_Frame_Buffer_RefDesign\Gowin_VFB_SDRAM_RefDesign\project\src\dk_video.sdc |
| Tool Version | V1.9.9.01 (64-bit) |
| Part Number | GW2AR-LV18EQ144C8/I7 |
| Device | GW2AR-18 |
| Device Version | C |
| Created Time | Wed Jan 10 09:25:22 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
| Setup Delay Model | Slow 0.95V 85C C8/I7 |
| Hold Delay Model | Fast 1.05V 0C C8/I7 |
| Numbers of Paths Analyzed | 2980 |
| Numbers of Endpoints Analyzed | 2918 |
| Numbers of Falling Endpoints | 8 |
| Numbers of Setup Violated Endpoints | 0 |
| Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
|---|---|---|---|---|---|---|---|---|
| O_clk | Base | 15.385 | 64.998 | 0.000 | 7.692 | O_clk O_clk_d | ||
| I_clk | Base | 20.000 | 50.000 | 0.000 | 10.000 | I_clk | ||
| O_sdram_clk | Base | 8.333 | 120.005 | 0.000 | 4.167 | O_sdram_clk O_sdram_clk_d | ||
| sdrc_clk | Base | 8.333 | 120.005 | 0.000 | 4.167 | sdrc_clk | ||
| pix_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk | Generated | 15.385 | 65.000 | 0.000 | 7.692 | I_clk_ibuf/I | I_clk | pix_rpll_inst/rpll_inst/CLKOUTP |
| pix_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk | Generated | 30.769 | 32.500 | 0.000 | 15.385 | I_clk_ibuf/I | I_clk | pix_rpll_inst/rpll_inst/CLKOUTD |
| pix_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 46.154 | 21.667 | 0.000 | 23.077 | I_clk_ibuf/I | I_clk | pix_rpll_inst/rpll_inst/CLKOUTD3 |
| gw_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk | Generated | 16.667 | 60.000 | 0.000 | 8.333 | I_clk_ibuf/I | I_clk | gw_rpll_inst/rpll_inst/CLKOUTD |
| gw_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 25.000 | 40.000 | 0.000 | 12.500 | I_clk_ibuf/I | I_clk | gw_rpll_inst/rpll_inst/CLKOUTD3 |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | O_clk | 64.998(MHz) | 144.838(MHz) | 8 | TOP |
| 2 | I_clk | 50.000(MHz) | 209.034(MHz) | 6 | TOP |
| 3 | sdrc_clk | 120.005(MHz) | 125.731(MHz) | 9 | TOP |
No timing paths to get frequency of O_sdram_clk!
No timing paths to get frequency of pix_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk!
No timing paths to get frequency of pix_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk!
No timing paths to get frequency of pix_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk!
No timing paths to get frequency of gw_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk!
No timing paths to get frequency of gw_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk!
Total Negative Slack Summary:
| Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
|---|---|---|---|
| O_clk | Setup | 0.000 | 0 |
| O_clk | Hold | 0.000 | 0 |
| I_clk | Setup | 0.000 | 0 |
| I_clk | Hold | 0.000 | 0 |
| O_sdram_clk | Setup | 0.000 | 0 |
| O_sdram_clk | Hold | 0.000 | 0 |
| sdrc_clk | Setup | 0.000 | 0 |
| sdrc_clk | Hold | 0.000 | 0 |
| pix_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0 |
| pix_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0 |
| pix_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk | Setup | 0.000 | 0 |
| pix_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk | Hold | 0.000 | 0 |
| pix_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0 |
| pix_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0 |
| gw_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk | Setup | 0.000 | 0 |
| gw_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk | Hold | 0.000 | 0 |
| gw_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0 |
| gw_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 0.379 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0/D | sdrc_clk:[R] | sdrc_clk:[R] | 8.333 | 0.000 | 7.919 |
| 2 | 0.625 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0/Q | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/Data_len_0_wrd_1_s0/D | sdrc_clk:[R] | sdrc_clk:[R] | 8.333 | 0.000 | 7.673 |
| 3 | 0.699 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0/Q | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/Double_wrd_flag_s0/D | sdrc_clk:[R] | sdrc_clk:[R] | 8.333 | 0.000 | 7.599 |
| 4 | 0.709 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0/Q | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/Data_len_0_wrd_0_s0/D | sdrc_clk:[R] | sdrc_clk:[R] | 8.333 | 0.000 | 7.589 |
| 5 | 0.759 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0/Q | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/Data_len_0_wrd_3_s0/D | sdrc_clk:[R] | sdrc_clk:[R] | 8.333 | 0.000 | 7.539 |
| 6 | 0.759 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0/Q | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/Data_len_0_wrd_4_s0/D | sdrc_clk:[R] | sdrc_clk:[R] | 8.333 | 0.000 | 7.539 |
| 7 | 0.800 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0/Q | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/Data_len_0_wrd_2_s0/D | sdrc_clk:[R] | sdrc_clk:[R] | 8.333 | 0.000 | 7.498 |
| 8 | 1.010 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0/Q | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/Data_len_0_wrd_5_s0/D | sdrc_clk:[R] | sdrc_clk:[R] | 8.333 | 0.000 | 7.288 |
| 9 | 1.568 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s/ADB[10] | sdrc_clk:[R] | sdrc_clk:[R] | 8.333 | 0.000 | 6.730 |
| 10 | 1.592 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_0_s/ADB[10] | sdrc_clk:[R] | sdrc_clk:[R] | 8.333 | 0.000 | 6.707 |
| 11 | 1.684 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s/ADB[10] | sdrc_clk:[R] | sdrc_clk:[R] | 8.333 | 0.000 | 6.614 |
| 12 | 1.717 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s/ADB[13] | sdrc_clk:[R] | sdrc_clk:[R] | 8.333 | 0.000 | 6.581 |
| 13 | 1.733 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s/ADB[13] | sdrc_clk:[R] | sdrc_clk:[R] | 8.333 | 0.000 | 6.565 |
| 14 | 1.745 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_5_s1/D | sdrc_clk:[R] | sdrc_clk:[R] | 8.333 | 0.000 | 6.553 |
| 15 | 1.761 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_1_s/ADB[13] | sdrc_clk:[R] | sdrc_clk:[R] | 8.333 | 0.000 | 6.537 |
| 16 | 1.782 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_dly_9_s0/D | sdrc_clk:[R] | sdrc_clk:[R] | 8.333 | 0.000 | 6.516 |
| 17 | 1.819 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_10_s1/D | sdrc_clk:[R] | sdrc_clk:[R] | 8.333 | 0.000 | 6.479 |
| 18 | 1.830 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s/ADB[12] | sdrc_clk:[R] | sdrc_clk:[R] | 8.333 | 0.000 | 6.468 |
| 19 | 1.834 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_1_s/ADB[10] | sdrc_clk:[R] | sdrc_clk:[R] | 8.333 | 0.000 | 6.464 |
| 20 | 1.988 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_0_s/ADB[13] | sdrc_clk:[R] | sdrc_clk:[R] | 8.333 | 0.000 | 6.311 |
| 21 | 2.024 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_0_s/ADB[12] | sdrc_clk:[R] | sdrc_clk:[R] | 8.333 | 0.000 | 6.274 |
| 22 | 2.050 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_dly_10_s0/D | sdrc_clk:[R] | sdrc_clk:[R] | 8.333 | 0.000 | 6.248 |
| 23 | 2.050 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_10_s0/D | sdrc_clk:[R] | sdrc_clk:[R] | 8.333 | 0.000 | 6.248 |
| 24 | 2.064 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s/ADB[12] | sdrc_clk:[R] | sdrc_clk:[R] | 8.333 | 0.000 | 6.235 |
| 25 | 2.065 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_7_s1/D | sdrc_clk:[R] | sdrc_clk:[R] | 8.333 | 0.000 | 6.233 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 0.074 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_17_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s/DI[1] | I_clk:[R] | I_clk:[R] | 0.000 | 0.000 | 0.323 |
| 2 | 0.074 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_16_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s/DI[0] | I_clk:[R] | I_clk:[R] | 0.000 | 0.000 | 0.323 |
| 3 | 0.198 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_22_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s/DI[6] | I_clk:[R] | I_clk:[R] | 0.000 | 0.000 | 0.447 |
| 4 | 0.213 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_24_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s/DI[0] | I_clk:[R] | I_clk:[R] | 0.000 | 0.000 | 0.462 |
| 5 | 0.213 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_23_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s/DI[7] | I_clk:[R] | I_clk:[R] | 0.000 | 0.000 | 0.462 |
| 6 | 0.213 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_20_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s/DI[4] | I_clk:[R] | I_clk:[R] | 0.000 | 0.000 | 0.462 |
| 7 | 0.213 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_12_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_1_s/DI[4] | I_clk:[R] | I_clk:[R] | 0.000 | 0.000 | 0.462 |
| 8 | 0.225 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_28_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s/DI[4] | I_clk:[R] | I_clk:[R] | 0.000 | 0.000 | 0.474 |
| 9 | 0.225 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_21_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s/DI[5] | I_clk:[R] | I_clk:[R] | 0.000 | 0.000 | 0.474 |
| 10 | 0.335 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_31_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s/DI[7] | I_clk:[R] | I_clk:[R] | 0.000 | 0.000 | 0.584 |
| 11 | 0.335 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_19_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s/DI[3] | I_clk:[R] | I_clk:[R] | 0.000 | 0.000 | 0.584 |
| 12 | 0.335 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_9_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_1_s/DI[1] | I_clk:[R] | I_clk:[R] | 0.000 | 0.000 | 0.584 |
| 13 | 0.335 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_8_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_1_s/DI[0] | I_clk:[R] | I_clk:[R] | 0.000 | 0.000 | 0.584 |
| 14 | 0.337 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_25_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s/DI[1] | I_clk:[R] | I_clk:[R] | 0.000 | 0.000 | 0.586 |
| 15 | 0.340 | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/User_data_i_0_s2/Q | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/User_data_i_0_s12/AD[0] | sdrc_clk:[R] | sdrc_clk:[R] | 0.000 | 0.000 | 0.352 |
| 16 | 0.347 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_10_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_1_s/DI[2] | I_clk:[R] | I_clk:[R] | 0.000 | 0.000 | 0.596 |
| 17 | 0.363 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_30_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s/DI[6] | I_clk:[R] | I_clk:[R] | 0.000 | 0.000 | 0.612 |
| 18 | 0.363 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_18_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s/DI[2] | I_clk:[R] | I_clk:[R] | 0.000 | 0.000 | 0.612 |
| 19 | 0.363 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_4_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_0_s/DI[4] | I_clk:[R] | I_clk:[R] | 0.000 | 0.000 | 0.612 |
| 20 | 0.363 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_0_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_0_s/DI[0] | I_clk:[R] | I_clk:[R] | 0.000 | 0.000 | 0.612 |
| 21 | 0.364 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.wbin_0_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_1_s/ADA[3] | I_clk:[R] | I_clk:[R] | 0.000 | 0.000 | 0.482 |
| 22 | 0.375 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_26_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s/DI[2] | I_clk:[R] | I_clk:[R] | 0.000 | 0.000 | 0.624 |
| 23 | 0.424 | cnt_vs_3_s0/Q | cnt_vs_3_s0/D | I_clk:[R] | I_clk:[R] | 0.000 | 0.000 | 0.435 |
| 24 | 0.425 | testpattern_inst/De_cyc_hcnt_3_s3/Q | testpattern_inst/De_cyc_hcnt_3_s3/D | I_clk:[R] | I_clk:[R] | 0.000 | 0.000 | 0.436 |
| 25 | 0.425 | testpattern_inst/Sqr_v_trig_s1/Q | testpattern_inst/Sqr_v_trig_s1/D | I_clk:[R] | I_clk:[R] | 0.000 | 0.000 | 0.436 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 1.908 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s/RESETB | sdrc_clk:[F] | sdrc_clk:[R] | 4.166 | 0.018 | 1.802 |
| 2 | 1.908 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s/RESETB | sdrc_clk:[F] | sdrc_clk:[R] | 4.166 | 0.018 | 1.802 |
| 3 | 1.908 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_1_s/RESETB | sdrc_clk:[F] | sdrc_clk:[R] | 4.166 | 0.018 | 1.802 |
| 4 | 1.908 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_0_s/RESETB | sdrc_clk:[F] | sdrc_clk:[R] | 4.166 | 0.018 | 1.802 |
| 5 | 2.311 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_dly_10_s0/CLEAR | sdrc_clk:[F] | sdrc_clk:[R] | 4.166 | 0.018 | 1.802 |
| 6 | 2.311 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_0_s0/CLEAR | sdrc_clk:[F] | sdrc_clk:[R] | 4.166 | 0.018 | 1.802 |
| 7 | 2.311 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_1_s0/CLEAR | sdrc_clk:[F] | sdrc_clk:[R] | 4.166 | 0.018 | 1.802 |
| 8 | 2.311 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_2_s0/CLEAR | sdrc_clk:[F] | sdrc_clk:[R] | 4.166 | 0.018 | 1.802 |
| 9 | 2.311 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_3_s0/CLEAR | sdrc_clk:[F] | sdrc_clk:[R] | 4.166 | 0.018 | 1.802 |
| 10 | 2.311 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_4_s0/CLEAR | sdrc_clk:[F] | sdrc_clk:[R] | 4.166 | 0.018 | 1.802 |
| 11 | 2.311 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_5_s0/CLEAR | sdrc_clk:[F] | sdrc_clk:[R] | 4.166 | 0.018 | 1.802 |
| 12 | 2.311 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_6_s0/CLEAR | sdrc_clk:[F] | sdrc_clk:[R] | 4.166 | 0.018 | 1.802 |
| 13 | 2.311 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_7_s0/CLEAR | sdrc_clk:[F] | sdrc_clk:[R] | 4.166 | 0.018 | 1.802 |
| 14 | 2.311 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_8_s0/CLEAR | sdrc_clk:[F] | sdrc_clk:[R] | 4.166 | 0.018 | 1.802 |
| 15 | 2.311 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_9_s0/CLEAR | sdrc_clk:[F] | sdrc_clk:[R] | 4.166 | 0.018 | 1.802 |
| 16 | 2.311 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_10_s0/CLEAR | sdrc_clk:[F] | sdrc_clk:[R] | 4.166 | 0.018 | 1.802 |
| 17 | 2.311 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_11_s0/CLEAR | sdrc_clk:[F] | sdrc_clk:[R] | 4.166 | 0.018 | 1.802 |
| 18 | 2.311 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0/PRESET | sdrc_clk:[F] | sdrc_clk:[R] | 4.166 | 0.018 | 1.802 |
| 19 | 2.311 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_0_s1/CLEAR | sdrc_clk:[F] | sdrc_clk:[R] | 4.166 | 0.018 | 1.802 |
| 20 | 2.311 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_1_s1/CLEAR | sdrc_clk:[F] | sdrc_clk:[R] | 4.166 | 0.018 | 1.802 |
| 21 | 2.311 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_2_s1/CLEAR | sdrc_clk:[F] | sdrc_clk:[R] | 4.166 | 0.018 | 1.802 |
| 22 | 2.311 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_3_s1/CLEAR | sdrc_clk:[F] | sdrc_clk:[R] | 4.166 | 0.018 | 1.802 |
| 23 | 2.311 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_4_s1/CLEAR | sdrc_clk:[F] | sdrc_clk:[R] | 4.166 | 0.018 | 1.802 |
| 24 | 2.311 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_5_s1/CLEAR | sdrc_clk:[F] | sdrc_clk:[R] | 4.166 | 0.018 | 1.802 |
| 25 | 2.311 | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_6_s1/CLEAR | sdrc_clk:[F] | sdrc_clk:[R] | 4.166 | 0.018 | 1.802 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 0.937 | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IDLE_s4/PRESET | sdrc_clk:[R] | sdrc_clk:[R] | 0.000 | 0.000 | 0.948 |
| 2 | 0.937 | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/CLEAR | sdrc_clk:[R] | sdrc_clk:[R] | 0.000 | 0.000 | 0.948 |
| 3 | 0.937 | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_OFF0_READ_DDR_s0/CLEAR | sdrc_clk:[R] | sdrc_clk:[R] | 0.000 | 0.000 | 0.948 |
| 4 | 0.937 | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0/CLEAR | sdrc_clk:[R] | sdrc_clk:[R] | 0.000 | 0.000 | 0.948 |
| 5 | 0.937 | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_rd_baseaddr_19_s0/CLEAR | sdrc_clk:[R] | sdrc_clk:[R] | 0.000 | 0.000 | 0.948 |
| 6 | 0.937 | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_rd_baseaddr_20_s0/CLEAR | sdrc_clk:[R] | sdrc_clk:[R] | 0.000 | 0.000 | 0.948 |
| 7 | 0.937 | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_wr_baseaddr_19_s0/CLEAR | sdrc_clk:[R] | sdrc_clk:[R] | 0.000 | 0.000 | 0.948 |
| 8 | 0.937 | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_wr_baseaddr_20_s0/CLEAR | sdrc_clk:[R] | sdrc_clk:[R] | 0.000 | 0.000 | 0.948 |
| 9 | 0.937 | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/rd_ptr_0_s0/CLEAR | sdrc_clk:[R] | sdrc_clk:[R] | 0.000 | 0.000 | 0.948 |
| 10 | 0.937 | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/rd_ptr_1_s0/CLEAR | sdrc_clk:[R] | sdrc_clk:[R] | 0.000 | 0.000 | 0.948 |
| 11 | 0.937 | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/wr_ptr_0_s0/CLEAR | sdrc_clk:[R] | sdrc_clk:[R] | 0.000 | 0.000 | 0.948 |
| 12 | 0.937 | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/wr_ptr_1_s0/CLEAR | sdrc_clk:[R] | sdrc_clk:[R] | 0.000 | 0.000 | 0.948 |
| 13 | 0.937 | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_req_o_s5/CLEAR | sdrc_clk:[R] | sdrc_clk:[R] | 0.000 | 0.000 | 0.948 |
| 14 | 0.937 | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_0_s1/CLEAR | sdrc_clk:[R] | sdrc_clk:[R] | 0.000 | 0.000 | 0.948 |
| 15 | 0.937 | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_1_s1/CLEAR | sdrc_clk:[R] | sdrc_clk:[R] | 0.000 | 0.000 | 0.948 |
| 16 | 0.937 | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_2_s1/CLEAR | sdrc_clk:[R] | sdrc_clk:[R] | 0.000 | 0.000 | 0.948 |
| 17 | 0.937 | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_0_s1/CLEAR | sdrc_clk:[R] | sdrc_clk:[R] | 0.000 | 0.000 | 0.948 |
| 18 | 0.937 | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_1_s1/CLEAR | sdrc_clk:[R] | sdrc_clk:[R] | 0.000 | 0.000 | 0.948 |
| 19 | 0.937 | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_2_s1/CLEAR | sdrc_clk:[R] | sdrc_clk:[R] | 0.000 | 0.000 | 0.948 |
| 20 | 0.937 | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_3_s1/CLEAR | sdrc_clk:[R] | sdrc_clk:[R] | 0.000 | 0.000 | 0.948 |
| 21 | 0.937 | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_4_s1/CLEAR | sdrc_clk:[R] | sdrc_clk:[R] | 0.000 | 0.000 | 0.948 |
| 22 | 0.937 | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_5_s1/CLEAR | sdrc_clk:[R] | sdrc_clk:[R] | 0.000 | 0.000 | 0.948 |
| 23 | 0.937 | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_6_s1/CLEAR | sdrc_clk:[R] | sdrc_clk:[R] | 0.000 | 0.000 | 0.948 |
| 24 | 0.937 | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_7_s1/CLEAR | sdrc_clk:[R] | sdrc_clk:[R] | 0.000 | 0.000 | 0.948 |
| 25 | 0.937 | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_8_s1/CLEAR | sdrc_clk:[R] | sdrc_clk:[R] | 0.000 | 0.000 | 0.948 |
Minimum Pulse Width Table:
| Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
|---|---|---|---|---|---|---|
| 1 | 3.089 | 4.089 | 1.000 | Low Pulse Width | sdrc_clk | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d0_s0 |
| 2 | 3.089 | 4.089 | 1.000 | Low Pulse Width | sdrc_clk | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d1_s0 |
| 3 | 3.089 | 4.089 | 1.000 | Low Pulse Width | sdrc_clk | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_end_o_s1 |
| 4 | 3.089 | 4.089 | 1.000 | Low Pulse Width | sdrc_clk | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_6_s1 |
| 5 | 3.089 | 4.089 | 1.000 | Low Pulse Width | sdrc_clk | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_5_s1 |
| 6 | 3.089 | 4.089 | 1.000 | Low Pulse Width | sdrc_clk | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_4_s1 |
| 7 | 3.089 | 4.089 | 1.000 | Low Pulse Width | sdrc_clk | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_20_s1 |
| 8 | 3.089 | 4.089 | 1.000 | Low Pulse Width | sdrc_clk | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_18_s1 |
| 9 | 3.089 | 4.089 | 1.000 | Low Pulse Width | sdrc_clk | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_17_s1 |
| 10 | 3.089 | 4.089 | 1.000 | Low Pulse Width | sdrc_clk | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/Sdrc_addr_i_9_s0 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 0.379 |
| Data Arrival Time | 8.162 |
| Data Required Time | 8.541 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0 |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.243 | 0.243 | tNET | RR | 1 | R27C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 23 | R27C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q |
| 1.540 | 1.065 | tNET | FF | 1 | R29C33[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_en_s0/I1 |
| 2.057 | 0.517 | tINS | FF | 28 | R29C33[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_en_s0/F |
| 2.493 | 0.436 | tNET | FF | 1 | R31C33[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s4/I3 |
| 2.864 | 0.371 | tINS | FF | 8 | R31C33[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s4/F |
| 3.270 | 0.406 | tNET | FF | 1 | R31C34[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/I3 |
| 3.641 | 0.371 | tINS | FF | 11 | R31C34[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/F |
| 4.182 | 0.541 | tNET | FF | 1 | R30C30[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_6_s3/I1 |
| 4.635 | 0.453 | tINS | FF | 4 | R30C30[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_6_s3/F |
| 5.216 | 0.581 | tNET | FF | 1 | R30C33[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rgraynext_5_s1/I0 |
| 5.587 | 0.371 | tINS | FF | 2 | R30C33[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rgraynext_5_s1/F |
| 6.005 | 0.418 | tNET | FF | 2 | R32C32[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n239_s0/I0 |
| 6.554 | 0.549 | tINS | FR | 1 | R32C32[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n239_s0/COUT |
| 6.554 | 0.000 | tNET | RR | 2 | R32C33[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n240_s0/CIN |
| 6.589 | 0.035 | tINS | RF | 1 | R32C33[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n240_s0/COUT |
| 6.589 | 0.000 | tNET | FF | 2 | R32C33[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n241_s0/CIN |
| 6.624 | 0.035 | tINS | FF | 1 | R32C33[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n241_s0/COUT |
| 6.624 | 0.000 | tNET | FF | 2 | R32C33[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n242_s0/CIN |
| 6.659 | 0.035 | tINS | FF | 1 | R32C33[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n242_s0/COUT |
| 6.659 | 0.000 | tNET | FF | 2 | R32C33[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n243_s0/CIN |
| 6.694 | 0.035 | tINS | FF | 1 | R32C33[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n243_s0/COUT |
| 6.694 | 0.000 | tNET | FF | 2 | R32C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n244_s0/CIN |
| 6.730 | 0.035 | tINS | FF | 1 | R32C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n244_s0/COUT |
| 7.613 | 0.883 | tNET | FF | 1 | R31C31[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rempty_val_s1/I2 |
| 8.162 | 0.549 | tINS | FR | 1 | R31C31[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rempty_val_s1/F |
| 8.162 | 0.000 | tNET | RR | 1 | R31C31[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | R31C31[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0/CLK |
| 8.541 | -0.035 | tSu | 1 | R31C31[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 8.333 |
| Logic Level | 9 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 3.357, 42.394%; route: 4.330, 54.676%; tC2Q: 0.232, 2.930% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path2
Path Summary:
| Slack | 0.625 |
| Data Arrival Time | 7.916 |
| Data Required Time | 8.541 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0 |
| To | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/Data_len_0_wrd_1_s0 |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.243 | 0.243 | tNET | RR | 1 | R29C28[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 2 | R29C28[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0/Q |
| 0.998 | 0.523 | tNET | FF | 1 | R20C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n64_s2/I0 |
| 1.553 | 0.555 | tINS | FF | 49 | R20C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n64_s2/F |
| 1.864 | 0.311 | tNET | FF | 1 | R18C28[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/I0 |
| 2.381 | 0.517 | tINS | FF | 24 | R18C28[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/F |
| 3.085 | 0.704 | tNET | FF | 1 | R21C29[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/O_sdrc_addr_d_0_s/I0 |
| 3.640 | 0.555 | tINS | FF | 4 | R21C29[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/O_sdrc_addr_d_0_s/F |
| 4.437 | 0.798 | tNET | FF | 1 | R26C25[1][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s14/I2 |
| 5.007 | 0.570 | tINS | FR | 1 | R26C25[1][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s14/F |
| 5.180 | 0.172 | tNET | RR | 1 | R26C26[0][B] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s8/I2 |
| 5.642 | 0.462 | tINS | RR | 1 | R26C26[0][B] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s8/F |
| 5.643 | 0.001 | tNET | RR | 1 | R26C26[0][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s4/I0 |
| 6.213 | 0.570 | tINS | RR | 1 | R26C26[0][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s4/F |
| 6.386 | 0.172 | tNET | RR | 1 | R25C26[1][B] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s3/I0 |
| 6.941 | 0.555 | tINS | RF | 7 | R25C26[1][B] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s3/F |
| 7.367 | 0.426 | tNET | FF | 1 | R25C23[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n989_s0/I3 |
| 7.916 | 0.549 | tINS | FR | 1 | R25C23[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n989_s0/F |
| 7.916 | 0.000 | tNET | RR | 1 | R25C23[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/Data_len_0_wrd_1_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | R25C23[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/Data_len_0_wrd_1_s0/CLK |
| 8.541 | -0.035 | tSu | 1 | R25C23[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/Data_len_0_wrd_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 8.333 |
| Logic Level | 9 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 4.333, 56.474%; route: 3.108, 40.502%; tC2Q: 0.232, 3.024% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path3
Path Summary:
| Slack | 0.699 |
| Data Arrival Time | 7.843 |
| Data Required Time | 8.541 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0 |
| To | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/Double_wrd_flag_s0 |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.243 | 0.243 | tNET | RR | 1 | R29C28[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 2 | R29C28[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0/Q |
| 0.998 | 0.523 | tNET | FF | 1 | R20C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n64_s2/I0 |
| 1.553 | 0.555 | tINS | FF | 49 | R20C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n64_s2/F |
| 1.864 | 0.311 | tNET | FF | 1 | R18C28[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/I0 |
| 2.381 | 0.517 | tINS | FF | 24 | R18C28[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/F |
| 3.085 | 0.704 | tNET | FF | 1 | R21C29[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/O_sdrc_addr_d_0_s/I0 |
| 3.640 | 0.555 | tINS | FF | 4 | R21C29[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/O_sdrc_addr_d_0_s/F |
| 4.437 | 0.798 | tNET | FF | 1 | R26C25[1][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s14/I2 |
| 5.007 | 0.570 | tINS | FR | 1 | R26C25[1][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s14/F |
| 5.180 | 0.172 | tNET | RR | 1 | R26C26[0][B] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s8/I2 |
| 5.642 | 0.462 | tINS | RR | 1 | R26C26[0][B] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s8/F |
| 5.643 | 0.001 | tNET | RR | 1 | R26C26[0][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s4/I0 |
| 6.213 | 0.570 | tINS | RR | 1 | R26C26[0][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s4/F |
| 6.386 | 0.172 | tNET | RR | 1 | R25C26[1][B] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s3/I0 |
| 6.941 | 0.555 | tINS | RF | 7 | R25C26[1][B] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s3/F |
| 7.472 | 0.531 | tNET | FF | 1 | R21C24[0][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n982_s18/I2 |
| 7.843 | 0.371 | tINS | FF | 1 | R21C24[0][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n982_s18/F |
| 7.843 | 0.000 | tNET | FF | 1 | R21C24[0][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/Double_wrd_flag_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | R21C24[0][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/Double_wrd_flag_s0/CLK |
| 8.541 | -0.035 | tSu | 1 | R21C24[0][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/Double_wrd_flag_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 8.333 |
| Logic Level | 9 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 4.155, 54.675%; route: 3.212, 42.272%; tC2Q: 0.232, 3.053% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path4
Path Summary:
| Slack | 0.709 |
| Data Arrival Time | 7.832 |
| Data Required Time | 8.541 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0 |
| To | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/Data_len_0_wrd_0_s0 |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.243 | 0.243 | tNET | RR | 1 | R29C28[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 2 | R29C28[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0/Q |
| 0.998 | 0.523 | tNET | FF | 1 | R20C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n64_s2/I0 |
| 1.553 | 0.555 | tINS | FF | 49 | R20C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n64_s2/F |
| 1.864 | 0.311 | tNET | FF | 1 | R18C28[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/I0 |
| 2.381 | 0.517 | tINS | FF | 24 | R18C28[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/F |
| 3.085 | 0.704 | tNET | FF | 1 | R21C29[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/O_sdrc_addr_d_0_s/I0 |
| 3.640 | 0.555 | tINS | FF | 4 | R21C29[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/O_sdrc_addr_d_0_s/F |
| 4.437 | 0.798 | tNET | FF | 1 | R26C25[1][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s14/I2 |
| 5.007 | 0.570 | tINS | FR | 1 | R26C25[1][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s14/F |
| 5.180 | 0.172 | tNET | RR | 1 | R26C26[0][B] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s8/I2 |
| 5.642 | 0.462 | tINS | RR | 1 | R26C26[0][B] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s8/F |
| 5.643 | 0.001 | tNET | RR | 1 | R26C26[0][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s4/I0 |
| 6.213 | 0.570 | tINS | RR | 1 | R26C26[0][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s4/F |
| 6.386 | 0.172 | tNET | RR | 1 | R25C26[1][B] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s3/I0 |
| 6.941 | 0.555 | tINS | RF | 7 | R25C26[1][B] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s3/F |
| 7.370 | 0.429 | tNET | FF | 1 | R27C26[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n990_s0/I3 |
| 7.832 | 0.462 | tINS | FR | 1 | R27C26[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n990_s0/F |
| 7.832 | 0.000 | tNET | RR | 1 | R27C26[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/Data_len_0_wrd_0_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | R27C26[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/Data_len_0_wrd_0_s0/CLK |
| 8.541 | -0.035 | tSu | 1 | R27C26[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/Data_len_0_wrd_0_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 8.333 |
| Logic Level | 9 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 4.246, 55.952%; route: 3.111, 40.991%; tC2Q: 0.232, 3.057% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path5
Path Summary:
| Slack | 0.759 |
| Data Arrival Time | 7.782 |
| Data Required Time | 8.541 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0 |
| To | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/Data_len_0_wrd_3_s0 |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.243 | 0.243 | tNET | RR | 1 | R29C28[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 2 | R29C28[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0/Q |
| 0.998 | 0.523 | tNET | FF | 1 | R20C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n64_s2/I0 |
| 1.553 | 0.555 | tINS | FF | 49 | R20C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n64_s2/F |
| 1.864 | 0.311 | tNET | FF | 1 | R18C28[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/I0 |
| 2.381 | 0.517 | tINS | FF | 24 | R18C28[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/F |
| 3.085 | 0.704 | tNET | FF | 1 | R21C29[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/O_sdrc_addr_d_0_s/I0 |
| 3.640 | 0.555 | tINS | FF | 4 | R21C29[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/O_sdrc_addr_d_0_s/F |
| 4.437 | 0.798 | tNET | FF | 1 | R26C25[1][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s14/I2 |
| 5.007 | 0.570 | tINS | FR | 1 | R26C25[1][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s14/F |
| 5.180 | 0.172 | tNET | RR | 1 | R26C26[0][B] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s8/I2 |
| 5.642 | 0.462 | tINS | RR | 1 | R26C26[0][B] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s8/F |
| 5.643 | 0.001 | tNET | RR | 1 | R26C26[0][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s4/I0 |
| 6.213 | 0.570 | tINS | RR | 1 | R26C26[0][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s4/F |
| 6.386 | 0.172 | tNET | RR | 1 | R25C26[1][B] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s3/I0 |
| 6.941 | 0.555 | tINS | RF | 7 | R25C26[1][B] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s3/F |
| 7.212 | 0.272 | tNET | FF | 1 | R27C26[1][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n987_s0/I3 |
| 7.782 | 0.570 | tINS | FR | 1 | R27C26[1][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n987_s0/F |
| 7.782 | 0.000 | tNET | RR | 1 | R27C26[1][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/Data_len_0_wrd_3_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | R27C26[1][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/Data_len_0_wrd_3_s0/CLK |
| 8.541 | -0.035 | tSu | 1 | R27C26[1][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/Data_len_0_wrd_3_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 8.333 |
| Logic Level | 9 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 4.354, 57.753%; route: 2.953, 39.170%; tC2Q: 0.232, 3.077% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path6
Path Summary:
| Slack | 0.759 |
| Data Arrival Time | 7.782 |
| Data Required Time | 8.541 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0 |
| To | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/Data_len_0_wrd_4_s0 |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.243 | 0.243 | tNET | RR | 1 | R29C28[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 2 | R29C28[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0/Q |
| 0.998 | 0.523 | tNET | FF | 1 | R20C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n64_s2/I0 |
| 1.553 | 0.555 | tINS | FF | 49 | R20C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n64_s2/F |
| 1.864 | 0.311 | tNET | FF | 1 | R18C28[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/I0 |
| 2.381 | 0.517 | tINS | FF | 24 | R18C28[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/F |
| 3.085 | 0.704 | tNET | FF | 1 | R21C29[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/O_sdrc_addr_d_0_s/I0 |
| 3.640 | 0.555 | tINS | FF | 4 | R21C29[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/O_sdrc_addr_d_0_s/F |
| 4.437 | 0.798 | tNET | FF | 1 | R26C25[1][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s14/I2 |
| 5.007 | 0.570 | tINS | FR | 1 | R26C25[1][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s14/F |
| 5.180 | 0.172 | tNET | RR | 1 | R26C26[0][B] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s8/I2 |
| 5.642 | 0.462 | tINS | RR | 1 | R26C26[0][B] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s8/F |
| 5.643 | 0.001 | tNET | RR | 1 | R26C26[0][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s4/I0 |
| 6.213 | 0.570 | tINS | RR | 1 | R26C26[0][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s4/F |
| 6.386 | 0.172 | tNET | RR | 1 | R25C26[1][B] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s3/I0 |
| 6.941 | 0.555 | tINS | RF | 7 | R25C26[1][B] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s3/F |
| 7.212 | 0.272 | tNET | FF | 1 | R27C26[1][B] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n986_s0/I3 |
| 7.782 | 0.570 | tINS | FR | 1 | R27C26[1][B] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n986_s0/F |
| 7.782 | 0.000 | tNET | RR | 1 | R27C26[1][B] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/Data_len_0_wrd_4_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | R27C26[1][B] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/Data_len_0_wrd_4_s0/CLK |
| 8.541 | -0.035 | tSu | 1 | R27C26[1][B] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/Data_len_0_wrd_4_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 8.333 |
| Logic Level | 9 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 4.354, 57.753%; route: 2.953, 39.170%; tC2Q: 0.232, 3.077% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path7
Path Summary:
| Slack | 0.800 |
| Data Arrival Time | 7.741 |
| Data Required Time | 8.541 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0 |
| To | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/Data_len_0_wrd_2_s0 |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.243 | 0.243 | tNET | RR | 1 | R29C28[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 2 | R29C28[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0/Q |
| 0.998 | 0.523 | tNET | FF | 1 | R20C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n64_s2/I0 |
| 1.553 | 0.555 | tINS | FF | 49 | R20C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n64_s2/F |
| 1.864 | 0.311 | tNET | FF | 1 | R18C28[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/I0 |
| 2.381 | 0.517 | tINS | FF | 24 | R18C28[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/F |
| 3.085 | 0.704 | tNET | FF | 1 | R21C29[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/O_sdrc_addr_d_0_s/I0 |
| 3.640 | 0.555 | tINS | FF | 4 | R21C29[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/O_sdrc_addr_d_0_s/F |
| 4.437 | 0.798 | tNET | FF | 1 | R26C25[1][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s14/I2 |
| 5.007 | 0.570 | tINS | FR | 1 | R26C25[1][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s14/F |
| 5.180 | 0.172 | tNET | RR | 1 | R26C26[0][B] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s8/I2 |
| 5.642 | 0.462 | tINS | RR | 1 | R26C26[0][B] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s8/F |
| 5.643 | 0.001 | tNET | RR | 1 | R26C26[0][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s4/I0 |
| 6.213 | 0.570 | tINS | RR | 1 | R26C26[0][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s4/F |
| 6.386 | 0.172 | tNET | RR | 1 | R25C26[1][B] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s3/I0 |
| 6.941 | 0.555 | tINS | RF | 7 | R25C26[1][B] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s3/F |
| 7.370 | 0.429 | tNET | FF | 1 | R27C26[0][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n988_s0/I3 |
| 7.741 | 0.371 | tINS | FF | 1 | R27C26[0][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n988_s0/F |
| 7.741 | 0.000 | tNET | FF | 1 | R27C26[0][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/Data_len_0_wrd_2_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | R27C26[0][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/Data_len_0_wrd_2_s0/CLK |
| 8.541 | -0.035 | tSu | 1 | R27C26[0][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/Data_len_0_wrd_2_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 8.333 |
| Logic Level | 9 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 4.155, 55.417%; route: 3.111, 41.489%; tC2Q: 0.232, 3.094% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path8
Path Summary:
| Slack | 1.010 |
| Data Arrival Time | 7.531 |
| Data Required Time | 8.541 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0 |
| To | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/Data_len_0_wrd_5_s0 |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.243 | 0.243 | tNET | RR | 1 | R29C28[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 2 | R29C28[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0/Q |
| 0.998 | 0.523 | tNET | FF | 1 | R20C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n64_s2/I0 |
| 1.553 | 0.555 | tINS | FF | 49 | R20C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n64_s2/F |
| 1.864 | 0.311 | tNET | FF | 1 | R18C28[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/I0 |
| 2.381 | 0.517 | tINS | FF | 24 | R18C28[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/next_state.ST_OFF0_READ_DDR_s1/F |
| 3.085 | 0.704 | tNET | FF | 1 | R21C29[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/O_sdrc_addr_d_0_s/I0 |
| 3.640 | 0.555 | tINS | FF | 4 | R21C29[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/O_sdrc_addr_d_0_s/F |
| 4.437 | 0.798 | tNET | FF | 1 | R26C25[1][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s14/I2 |
| 5.007 | 0.570 | tINS | FR | 1 | R26C25[1][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s14/F |
| 5.180 | 0.172 | tNET | RR | 1 | R26C26[0][B] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s8/I2 |
| 5.642 | 0.462 | tINS | RR | 1 | R26C26[0][B] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s8/F |
| 5.643 | 0.001 | tNET | RR | 1 | R26C26[0][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s4/I0 |
| 6.213 | 0.570 | tINS | RR | 1 | R26C26[0][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s4/F |
| 6.386 | 0.172 | tNET | RR | 1 | R25C26[1][B] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s3/I0 |
| 6.956 | 0.570 | tINS | RR | 7 | R25C26[1][B] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s3/F |
| 6.961 | 0.005 | tNET | RR | 1 | R25C26[1][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s0/I3 |
| 7.531 | 0.570 | tINS | RR | 1 | R25C26[1][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/n985_s0/F |
| 7.531 | 0.000 | tNET | RR | 1 | R25C26[1][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/Data_len_0_wrd_5_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | R25C26[1][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/Data_len_0_wrd_5_s0/CLK |
| 8.541 | -0.035 | tSu | 1 | R25C26[1][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/Data_len_0_wrd_5_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 8.333 |
| Logic Level | 9 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 4.369, 59.951%; route: 2.687, 36.865%; tC2Q: 0.232, 3.183% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path9
Path Summary:
| Slack | 1.568 |
| Data Arrival Time | 6.973 |
| Data Required Time | 8.542 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.243 | 0.243 | tNET | RR | 1 | R27C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 23 | R27C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q |
| 1.540 | 1.065 | tNET | FF | 1 | R29C33[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_en_s0/I1 |
| 2.057 | 0.517 | tINS | FF | 28 | R29C33[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_en_s0/F |
| 2.493 | 0.436 | tNET | FF | 1 | R31C33[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s4/I3 |
| 2.864 | 0.371 | tINS | FF | 8 | R31C33[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s4/F |
| 3.270 | 0.406 | tNET | FF | 1 | R31C34[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/I3 |
| 3.641 | 0.371 | tINS | FF | 11 | R31C34[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/F |
| 4.244 | 0.603 | tNET | FF | 1 | R31C31[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_7_s3/I2 |
| 4.615 | 0.371 | tINS | FF | 4 | R31C31[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_7_s3/F |
| 5.561 | 0.946 | tNET | FF | 1 | R33C36[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_7_s2/I0 |
| 6.014 | 0.453 | tINS | FF | 4 | R33C36[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_7_s2/F |
| 6.973 | 0.959 | tNET | FF | 1 | BSRAM_R28[11] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s/ADB[10] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | BSRAM_R28[11] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s/CLKB |
| 8.542 | -0.035 | tSu | 1 | BSRAM_R28[11] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 8.333 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 2.083, 30.951%; route: 4.415, 65.602%; tC2Q: 0.232, 3.447% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path10
Path Summary:
| Slack | 1.592 |
| Data Arrival Time | 6.950 |
| Data Required Time | 8.542 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_0_s |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.243 | 0.243 | tNET | RR | 1 | R27C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 23 | R27C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q |
| 1.540 | 1.065 | tNET | FF | 1 | R29C33[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_en_s0/I1 |
| 2.057 | 0.517 | tINS | FF | 28 | R29C33[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_en_s0/F |
| 2.493 | 0.436 | tNET | FF | 1 | R31C33[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s4/I3 |
| 2.864 | 0.371 | tINS | FF | 8 | R31C33[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s4/F |
| 3.270 | 0.406 | tNET | FF | 1 | R31C34[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/I3 |
| 3.641 | 0.371 | tINS | FF | 11 | R31C34[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/F |
| 4.244 | 0.603 | tNET | FF | 1 | R31C31[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_7_s3/I2 |
| 4.615 | 0.371 | tINS | FF | 4 | R31C31[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_7_s3/F |
| 5.561 | 0.946 | tNET | FF | 1 | R33C36[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_7_s2/I0 |
| 6.014 | 0.453 | tINS | FF | 4 | R33C36[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_7_s2/F |
| 6.950 | 0.936 | tNET | FF | 1 | BSRAM_R28[8] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_0_s/ADB[10] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | BSRAM_R28[8] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_0_s/CLKB |
| 8.542 | -0.035 | tSu | 1 | BSRAM_R28[8] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_0_s |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 8.333 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 2.083, 31.058%; route: 4.392, 65.482%; tC2Q: 0.232, 3.459% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path11
Path Summary:
| Slack | 1.684 |
| Data Arrival Time | 6.857 |
| Data Required Time | 8.542 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.243 | 0.243 | tNET | RR | 1 | R27C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 23 | R27C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q |
| 1.540 | 1.065 | tNET | FF | 1 | R29C33[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_en_s0/I1 |
| 2.057 | 0.517 | tINS | FF | 28 | R29C33[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_en_s0/F |
| 2.493 | 0.436 | tNET | FF | 1 | R31C33[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s4/I3 |
| 2.864 | 0.371 | tINS | FF | 8 | R31C33[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s4/F |
| 3.270 | 0.406 | tNET | FF | 1 | R31C34[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/I3 |
| 3.641 | 0.371 | tINS | FF | 11 | R31C34[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/F |
| 4.244 | 0.603 | tNET | FF | 1 | R31C31[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_7_s3/I2 |
| 4.615 | 0.371 | tINS | FF | 4 | R31C31[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_7_s3/F |
| 5.561 | 0.946 | tNET | FF | 1 | R33C36[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_7_s2/I0 |
| 6.014 | 0.453 | tINS | FF | 4 | R33C36[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_7_s2/F |
| 6.857 | 0.843 | tNET | FF | 1 | BSRAM_R28[10] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s/ADB[10] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | BSRAM_R28[10] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s/CLKB |
| 8.542 | -0.035 | tSu | 1 | BSRAM_R28[10] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 8.333 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 2.083, 31.495%; route: 4.299, 64.998%; tC2Q: 0.232, 3.508% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path12
Path Summary:
| Slack | 1.717 |
| Data Arrival Time | 6.825 |
| Data Required Time | 8.542 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.243 | 0.243 | tNET | RR | 1 | R27C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 23 | R27C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q |
| 1.540 | 1.065 | tNET | FF | 1 | R29C33[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_en_s0/I1 |
| 2.057 | 0.517 | tINS | FF | 28 | R29C33[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_en_s0/F |
| 2.493 | 0.436 | tNET | FF | 1 | R31C33[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s4/I3 |
| 2.864 | 0.371 | tINS | FF | 8 | R31C33[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s4/F |
| 3.270 | 0.406 | tNET | FF | 1 | R31C34[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/I3 |
| 3.641 | 0.371 | tINS | FF | 11 | R31C34[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/F |
| 4.600 | 0.959 | tNET | FF | 1 | R31C35[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_10_s3/I3 |
| 5.155 | 0.555 | tINS | FF | 2 | R31C35[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_10_s3/F |
| 5.573 | 0.418 | tNET | FF | 1 | R30C34[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_10_s2/I2 |
| 6.128 | 0.555 | tINS | FF | 4 | R30C34[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_10_s2/F |
| 6.825 | 0.697 | tNET | FF | 1 | BSRAM_R28[10] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s/ADB[13] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | BSRAM_R28[10] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s/CLKB |
| 8.542 | -0.035 | tSu | 1 | BSRAM_R28[10] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 8.333 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 2.369, 35.995%; route: 3.980, 60.480%; tC2Q: 0.232, 3.525% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path13
Path Summary:
| Slack | 1.733 |
| Data Arrival Time | 6.809 |
| Data Required Time | 8.542 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.243 | 0.243 | tNET | RR | 1 | R27C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 23 | R27C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q |
| 1.540 | 1.065 | tNET | FF | 1 | R29C33[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_en_s0/I1 |
| 2.057 | 0.517 | tINS | FF | 28 | R29C33[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_en_s0/F |
| 2.493 | 0.436 | tNET | FF | 1 | R31C33[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s4/I3 |
| 2.864 | 0.371 | tINS | FF | 8 | R31C33[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s4/F |
| 3.270 | 0.406 | tNET | FF | 1 | R31C34[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/I3 |
| 3.641 | 0.371 | tINS | FF | 11 | R31C34[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/F |
| 4.600 | 0.959 | tNET | FF | 1 | R31C35[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_10_s3/I3 |
| 5.155 | 0.555 | tINS | FF | 2 | R31C35[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_10_s3/F |
| 5.573 | 0.418 | tNET | FF | 1 | R30C34[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_10_s2/I2 |
| 6.128 | 0.555 | tINS | FF | 4 | R30C34[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_10_s2/F |
| 6.809 | 0.681 | tNET | FF | 1 | BSRAM_R28[11] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s/ADB[13] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | BSRAM_R28[11] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s/CLKB |
| 8.542 | -0.035 | tSu | 1 | BSRAM_R28[11] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 8.333 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 2.369, 36.084%; route: 3.964, 60.382%; tC2Q: 0.232, 3.534% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path14
Path Summary:
| Slack | 1.745 |
| Data Arrival Time | 6.796 |
| Data Required Time | 8.541 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_5_s1 |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.243 | 0.243 | tNET | RR | 1 | R27C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 23 | R27C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q |
| 1.540 | 1.065 | tNET | FF | 1 | R29C33[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_en_s0/I1 |
| 2.057 | 0.517 | tINS | FF | 28 | R29C33[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_en_s0/F |
| 2.493 | 0.436 | tNET | FF | 1 | R31C33[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s4/I3 |
| 2.864 | 0.371 | tINS | FF | 8 | R31C33[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s4/F |
| 3.270 | 0.406 | tNET | FF | 1 | R31C34[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/I3 |
| 3.641 | 0.371 | tINS | FF | 11 | R31C34[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/F |
| 4.182 | 0.541 | tNET | FF | 1 | R30C30[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_6_s3/I1 |
| 4.635 | 0.453 | tINS | FF | 4 | R30C30[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_6_s3/F |
| 5.216 | 0.581 | tNET | FF | 1 | R30C33[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rgraynext_5_s1/I0 |
| 5.587 | 0.371 | tINS | FF | 2 | R30C33[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rgraynext_5_s1/F |
| 6.796 | 1.209 | tNET | FF | 1 | R35C34[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_5_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | R35C34[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_5_s1/CLK |
| 8.541 | -0.035 | tSu | 1 | R35C34[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_5_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 8.333 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 2.083, 31.787%; route: 4.238, 64.673%; tC2Q: 0.232, 3.540% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path15
Path Summary:
| Slack | 1.761 |
| Data Arrival Time | 6.780 |
| Data Required Time | 8.542 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_1_s |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.243 | 0.243 | tNET | RR | 1 | R27C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 23 | R27C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q |
| 1.540 | 1.065 | tNET | FF | 1 | R29C33[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_en_s0/I1 |
| 2.057 | 0.517 | tINS | FF | 28 | R29C33[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_en_s0/F |
| 2.493 | 0.436 | tNET | FF | 1 | R31C33[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s4/I3 |
| 2.864 | 0.371 | tINS | FF | 8 | R31C33[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s4/F |
| 3.270 | 0.406 | tNET | FF | 1 | R31C34[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/I3 |
| 3.641 | 0.371 | tINS | FF | 11 | R31C34[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/F |
| 4.600 | 0.959 | tNET | FF | 1 | R31C35[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_10_s3/I3 |
| 5.155 | 0.555 | tINS | FF | 2 | R31C35[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_10_s3/F |
| 5.573 | 0.418 | tNET | FF | 1 | R30C34[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_10_s2/I2 |
| 6.128 | 0.555 | tINS | FF | 4 | R30C34[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_10_s2/F |
| 6.780 | 0.653 | tNET | FF | 1 | BSRAM_R28[9] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_1_s/ADB[13] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | BSRAM_R28[9] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_1_s/CLKB |
| 8.542 | -0.035 | tSu | 1 | BSRAM_R28[9] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_1_s |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 8.333 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 2.369, 36.240%; route: 3.936, 60.211%; tC2Q: 0.232, 3.549% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path16
Path Summary:
| Slack | 1.782 |
| Data Arrival Time | 6.759 |
| Data Required Time | 8.541 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_dly_9_s0 |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.243 | 0.243 | tNET | RR | 1 | R27C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 23 | R27C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q |
| 1.540 | 1.065 | tNET | FF | 1 | R29C33[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_en_s0/I1 |
| 2.057 | 0.517 | tINS | FF | 28 | R29C33[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_en_s0/F |
| 2.493 | 0.436 | tNET | FF | 1 | R31C33[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s4/I3 |
| 2.864 | 0.371 | tINS | FF | 8 | R31C33[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s4/F |
| 3.270 | 0.406 | tNET | FF | 1 | R31C34[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/I3 |
| 3.641 | 0.371 | tINS | FF | 11 | R31C34[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/F |
| 4.244 | 0.603 | tNET | FF | 1 | R31C31[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_9_s3/I3 |
| 4.814 | 0.570 | tINS | FR | 5 | R31C31[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_9_s3/F |
| 4.818 | 0.004 | tNET | RR | 1 | R31C31[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_9_s3/I1 |
| 5.335 | 0.517 | tINS | RF | 2 | R31C31[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_9_s3/F |
| 6.759 | 1.424 | tNET | FF | 1 | R31C34[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_dly_9_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | R31C34[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_dly_9_s0/CLK |
| 8.541 | -0.035 | tSu | 1 | R31C34[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_dly_9_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 8.333 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 2.346, 36.006%; route: 3.938, 60.433%; tC2Q: 0.232, 3.561% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path17
Path Summary:
| Slack | 1.819 |
| Data Arrival Time | 6.723 |
| Data Required Time | 8.541 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_10_s1 |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.243 | 0.243 | tNET | RR | 1 | R27C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 23 | R27C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q |
| 1.540 | 1.065 | tNET | FF | 1 | R29C33[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_en_s0/I1 |
| 2.057 | 0.517 | tINS | FF | 28 | R29C33[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_en_s0/F |
| 2.493 | 0.436 | tNET | FF | 1 | R31C33[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s4/I3 |
| 2.864 | 0.371 | tINS | FF | 8 | R31C33[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s4/F |
| 3.270 | 0.406 | tNET | FF | 1 | R31C34[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/I3 |
| 3.641 | 0.371 | tINS | FF | 11 | R31C34[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/F |
| 4.244 | 0.603 | tNET | FF | 1 | R31C31[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_9_s3/I3 |
| 4.799 | 0.555 | tINS | FF | 5 | R31C31[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_9_s3/F |
| 4.996 | 0.197 | tNET | FF | 1 | R32C31[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rgraynext_10_s0/I1 |
| 5.513 | 0.517 | tINS | FF | 2 | R32C31[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rgraynext_10_s0/F |
| 6.723 | 1.209 | tNET | FF | 1 | R32C36[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_10_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | R32C36[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_10_s1/CLK |
| 8.541 | -0.035 | tSu | 1 | R32C36[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_10_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 8.333 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 2.331, 35.976%; route: 3.916, 60.443%; tC2Q: 0.232, 3.581% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path18
Path Summary:
| Slack | 1.830 |
| Data Arrival Time | 6.712 |
| Data Required Time | 8.542 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.243 | 0.243 | tNET | RR | 1 | R27C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 23 | R27C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q |
| 1.540 | 1.065 | tNET | FF | 1 | R29C33[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_en_s0/I1 |
| 2.057 | 0.517 | tINS | FF | 28 | R29C33[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_en_s0/F |
| 2.493 | 0.436 | tNET | FF | 1 | R31C33[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s4/I3 |
| 2.864 | 0.371 | tINS | FF | 8 | R31C33[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s4/F |
| 3.270 | 0.406 | tNET | FF | 1 | R31C34[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/I3 |
| 3.641 | 0.371 | tINS | FF | 11 | R31C34[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/F |
| 4.244 | 0.603 | tNET | FF | 1 | R31C31[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_9_s3/I3 |
| 4.799 | 0.555 | tINS | FF | 5 | R31C31[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_9_s3/F |
| 5.221 | 0.422 | tNET | FF | 1 | R31C34[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_9_s2/I2 |
| 5.776 | 0.555 | tINS | FF | 4 | R31C34[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_9_s2/F |
| 6.712 | 0.936 | tNET | FF | 1 | BSRAM_R28[10] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s/ADB[12] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | BSRAM_R28[10] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s/CLKB |
| 8.542 | -0.035 | tSu | 1 | BSRAM_R28[10] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 8.333 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 2.369, 36.625%; route: 3.867, 59.788%; tC2Q: 0.232, 3.587% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path19
Path Summary:
| Slack | 1.834 |
| Data Arrival Time | 6.707 |
| Data Required Time | 8.542 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_1_s |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.243 | 0.243 | tNET | RR | 1 | R27C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 23 | R27C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q |
| 1.540 | 1.065 | tNET | FF | 1 | R29C33[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_en_s0/I1 |
| 2.057 | 0.517 | tINS | FF | 28 | R29C33[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_en_s0/F |
| 2.493 | 0.436 | tNET | FF | 1 | R31C33[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s4/I3 |
| 2.864 | 0.371 | tINS | FF | 8 | R31C33[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s4/F |
| 3.270 | 0.406 | tNET | FF | 1 | R31C34[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/I3 |
| 3.641 | 0.371 | tINS | FF | 11 | R31C34[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/F |
| 4.244 | 0.603 | tNET | FF | 1 | R31C31[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_7_s3/I2 |
| 4.615 | 0.371 | tINS | FF | 4 | R31C31[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_7_s3/F |
| 5.561 | 0.946 | tNET | FF | 1 | R33C36[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_7_s2/I0 |
| 6.014 | 0.453 | tINS | FF | 4 | R33C36[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_7_s2/F |
| 6.707 | 0.693 | tNET | FF | 1 | BSRAM_R28[9] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_1_s/ADB[10] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | BSRAM_R28[9] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_1_s/CLKB |
| 8.542 | -0.035 | tSu | 1 | BSRAM_R28[9] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_1_s |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 8.333 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 2.083, 32.225%; route: 4.149, 64.186%; tC2Q: 0.232, 3.589% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path20
Path Summary:
| Slack | 1.988 |
| Data Arrival Time | 6.554 |
| Data Required Time | 8.542 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_0_s |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.243 | 0.243 | tNET | RR | 1 | R27C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 23 | R27C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q |
| 1.540 | 1.065 | tNET | FF | 1 | R29C33[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_en_s0/I1 |
| 2.057 | 0.517 | tINS | FF | 28 | R29C33[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_en_s0/F |
| 2.493 | 0.436 | tNET | FF | 1 | R31C33[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s4/I3 |
| 2.864 | 0.371 | tINS | FF | 8 | R31C33[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s4/F |
| 3.270 | 0.406 | tNET | FF | 1 | R31C34[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/I3 |
| 3.641 | 0.371 | tINS | FF | 11 | R31C34[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/F |
| 4.600 | 0.959 | tNET | FF | 1 | R31C35[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_10_s3/I3 |
| 5.155 | 0.555 | tINS | FF | 2 | R31C35[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_10_s3/F |
| 5.573 | 0.418 | tNET | FF | 1 | R30C34[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_10_s2/I2 |
| 6.128 | 0.555 | tINS | FF | 4 | R30C34[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_10_s2/F |
| 6.554 | 0.426 | tNET | FF | 1 | BSRAM_R28[8] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_0_s/ADB[13] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | BSRAM_R28[8] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_0_s/CLKB |
| 8.542 | -0.035 | tSu | 1 | BSRAM_R28[8] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_0_s |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 8.333 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 2.369, 37.541%; route: 3.710, 58.783%; tC2Q: 0.232, 3.676% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path21
Path Summary:
| Slack | 2.024 |
| Data Arrival Time | 6.517 |
| Data Required Time | 8.542 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_0_s |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.243 | 0.243 | tNET | RR | 1 | R27C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 23 | R27C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q |
| 1.540 | 1.065 | tNET | FF | 1 | R29C33[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_en_s0/I1 |
| 2.057 | 0.517 | tINS | FF | 28 | R29C33[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_en_s0/F |
| 2.493 | 0.436 | tNET | FF | 1 | R31C33[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s4/I3 |
| 2.864 | 0.371 | tINS | FF | 8 | R31C33[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s4/F |
| 3.270 | 0.406 | tNET | FF | 1 | R31C34[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/I3 |
| 3.641 | 0.371 | tINS | FF | 11 | R31C34[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/F |
| 4.244 | 0.603 | tNET | FF | 1 | R31C31[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_9_s3/I3 |
| 4.799 | 0.555 | tINS | FF | 5 | R31C31[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_9_s3/F |
| 5.221 | 0.422 | tNET | FF | 1 | R31C34[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_9_s2/I2 |
| 5.776 | 0.555 | tINS | FF | 4 | R31C34[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_9_s2/F |
| 6.517 | 0.741 | tNET | FF | 1 | BSRAM_R28[8] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_0_s/ADB[12] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | BSRAM_R28[8] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_0_s/CLKB |
| 8.542 | -0.035 | tSu | 1 | BSRAM_R28[8] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_0_s |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 8.333 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 2.369, 37.759%; route: 3.673, 58.543%; tC2Q: 0.232, 3.698% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path22
Path Summary:
| Slack | 2.050 |
| Data Arrival Time | 6.491 |
| Data Required Time | 8.541 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_dly_10_s0 |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.243 | 0.243 | tNET | RR | 1 | R27C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 23 | R27C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q |
| 1.540 | 1.065 | tNET | FF | 1 | R29C33[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_en_s0/I1 |
| 2.057 | 0.517 | tINS | FF | 28 | R29C33[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_en_s0/F |
| 2.493 | 0.436 | tNET | FF | 1 | R31C33[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s4/I3 |
| 2.864 | 0.371 | tINS | FF | 8 | R31C33[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s4/F |
| 3.270 | 0.406 | tNET | FF | 1 | R31C34[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/I3 |
| 3.641 | 0.371 | tINS | FF | 11 | R31C34[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/F |
| 4.600 | 0.959 | tNET | FF | 1 | R31C35[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_10_s3/I3 |
| 5.155 | 0.555 | tINS | FF | 2 | R31C35[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_10_s3/F |
| 5.406 | 0.252 | tNET | FF | 1 | R31C34[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_10_s3/I1 |
| 5.961 | 0.555 | tINS | FF | 2 | R31C34[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_10_s3/F |
| 6.491 | 0.530 | tNET | FF | 1 | R31C34[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_dly_10_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | R31C34[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_dly_10_s0/CLK |
| 8.541 | -0.035 | tSu | 1 | R31C34[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_dly_10_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 8.333 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 2.369, 37.918%; route: 3.647, 58.369%; tC2Q: 0.232, 3.713% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path23
Path Summary:
| Slack | 2.050 |
| Data Arrival Time | 6.491 |
| Data Required Time | 8.541 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_10_s0 |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.243 | 0.243 | tNET | RR | 1 | R27C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 23 | R27C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q |
| 1.540 | 1.065 | tNET | FF | 1 | R29C33[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_en_s0/I1 |
| 2.057 | 0.517 | tINS | FF | 28 | R29C33[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_en_s0/F |
| 2.493 | 0.436 | tNET | FF | 1 | R31C33[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s4/I3 |
| 2.864 | 0.371 | tINS | FF | 8 | R31C33[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s4/F |
| 3.270 | 0.406 | tNET | FF | 1 | R31C34[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/I3 |
| 3.641 | 0.371 | tINS | FF | 11 | R31C34[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/F |
| 4.600 | 0.959 | tNET | FF | 1 | R31C35[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_10_s3/I3 |
| 5.155 | 0.555 | tINS | FF | 2 | R31C35[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_10_s3/F |
| 5.406 | 0.252 | tNET | FF | 1 | R31C34[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_10_s3/I1 |
| 5.961 | 0.555 | tINS | FF | 2 | R31C34[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_10_s3/F |
| 6.491 | 0.530 | tNET | FF | 1 | R31C34[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_10_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | R31C34[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_10_s0/CLK |
| 8.541 | -0.035 | tSu | 1 | R31C34[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_10_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 8.333 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 2.369, 37.918%; route: 3.647, 58.369%; tC2Q: 0.232, 3.713% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path24
Path Summary:
| Slack | 2.064 |
| Data Arrival Time | 6.478 |
| Data Required Time | 8.542 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.243 | 0.243 | tNET | RR | 1 | R27C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 23 | R27C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q |
| 1.540 | 1.065 | tNET | FF | 1 | R29C33[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_en_s0/I1 |
| 2.057 | 0.517 | tINS | FF | 28 | R29C33[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_en_s0/F |
| 2.493 | 0.436 | tNET | FF | 1 | R31C33[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s4/I3 |
| 2.864 | 0.371 | tINS | FF | 8 | R31C33[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s4/F |
| 3.270 | 0.406 | tNET | FF | 1 | R31C34[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/I3 |
| 3.641 | 0.371 | tINS | FF | 11 | R31C34[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/F |
| 4.244 | 0.603 | tNET | FF | 1 | R31C31[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_9_s3/I3 |
| 4.799 | 0.555 | tINS | FF | 5 | R31C31[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_9_s3/F |
| 5.221 | 0.422 | tNET | FF | 1 | R31C34[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_9_s2/I2 |
| 5.776 | 0.555 | tINS | FF | 4 | R31C34[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_f_9_s2/F |
| 6.478 | 0.702 | tNET | FF | 1 | BSRAM_R28[11] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s/ADB[12] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | BSRAM_R28[11] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s/CLKB |
| 8.542 | -0.035 | tSu | 1 | BSRAM_R28[11] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 8.333 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 2.369, 37.998%; route: 3.634, 58.281%; tC2Q: 0.232, 3.721% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path25
Path Summary:
| Slack | 2.065 |
| Data Arrival Time | 6.476 |
| Data Required Time | 8.541 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_7_s1 |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.243 | 0.243 | tNET | RR | 1 | R27C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/CLK |
| 0.475 | 0.232 | tC2Q | RF | 23 | R27C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/Q |
| 1.540 | 1.065 | tNET | FF | 1 | R29C33[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_en_s0/I1 |
| 2.057 | 0.517 | tINS | FF | 28 | R29C33[3][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_en_s0/F |
| 2.493 | 0.436 | tNET | FF | 1 | R31C33[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s4/I3 |
| 2.864 | 0.371 | tINS | FF | 8 | R31C33[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_2_s4/F |
| 3.270 | 0.406 | tNET | FF | 1 | R31C34[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/I3 |
| 3.641 | 0.371 | tINS | FF | 11 | R31C34[3][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_5_s4/F |
| 4.176 | 0.536 | tNET | FF | 1 | R31C30[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rgraynext_7_s1/I1 |
| 4.746 | 0.570 | tINS | FR | 2 | R31C30[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rgraynext_7_s1/F |
| 4.749 | 0.003 | tNET | RR | 1 | R31C30[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rgraynext_7_s0/I1 |
| 5.202 | 0.453 | tINS | RF | 2 | R31C30[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rgraynext_7_s0/F |
| 6.476 | 1.274 | tNET | FF | 1 | R34C33[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_7_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | R34C33[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_7_s1/CLK |
| 8.541 | -0.035 | tSu | 1 | R34C33[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_7_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 8.333 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
| Arrival Data Path Delay | cell: 2.282, 36.613%; route: 3.719, 59.665%; tC2Q: 0.232, 3.722% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 0.074 |
| Data Arrival Time | 1.862 |
| Data Required Time | 1.788 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_17_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s |
| Launch Clk | I_clk:[R] |
| Latch Clk | I_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | R27C38[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_17_s0/CLK |
| 1.740 | 0.201 | tC2Q | RF | 1 | R27C38[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_17_s0/Q |
| 1.862 | 0.122 | tNET | FF | 1 | BSRAM_R28[10] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s/DI[1] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | BSRAM_R28[10] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s/CLKA |
| 1.788 | 0.249 | tHld | 1 | BSRAM_R28[10] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249% |
| Required Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
Path2
Path Summary:
| Slack | 0.074 |
| Data Arrival Time | 1.862 |
| Data Required Time | 1.788 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_16_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s |
| Launch Clk | I_clk:[R] |
| Latch Clk | I_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | R29C38[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_16_s0/CLK |
| 1.740 | 0.201 | tC2Q | RF | 1 | R29C38[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_16_s0/Q |
| 1.862 | 0.122 | tNET | FF | 1 | BSRAM_R28[10] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s/DI[0] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | BSRAM_R28[10] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s/CLKA |
| 1.788 | 0.249 | tHld | 1 | BSRAM_R28[10] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249% |
| Required Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
Path3
Path Summary:
| Slack | 0.198 |
| Data Arrival Time | 1.987 |
| Data Required Time | 1.788 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_22_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s |
| Launch Clk | I_clk:[R] |
| Latch Clk | I_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | R32C38[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_22_s0/CLK |
| 1.741 | 0.202 | tC2Q | RR | 1 | R32C38[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_22_s0/Q |
| 1.987 | 0.245 | tNET | RR | 1 | BSRAM_R28[10] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s/DI[6] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | BSRAM_R28[10] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s/CLKA |
| 1.788 | 0.249 | tHld | 1 | BSRAM_R28[10] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.245, 54.832%; tC2Q: 0.202, 45.168% |
| Required Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
Path4
Path Summary:
| Slack | 0.213 |
| Data Arrival Time | 2.002 |
| Data Required Time | 1.788 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_24_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s |
| Launch Clk | I_clk:[R] |
| Latch Clk | I_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | R29C39[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_24_s0/CLK |
| 1.741 | 0.202 | tC2Q | RR | 1 | R29C39[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_24_s0/Q |
| 2.002 | 0.260 | tNET | RR | 1 | BSRAM_R28[11] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s/DI[0] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | BSRAM_R28[11] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s/CLKA |
| 1.788 | 0.249 | tHld | 1 | BSRAM_R28[11] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686% |
| Required Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
Path5
Path Summary:
| Slack | 0.213 |
| Data Arrival Time | 2.002 |
| Data Required Time | 1.788 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_23_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s |
| Launch Clk | I_clk:[R] |
| Latch Clk | I_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | R31C38[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_23_s0/CLK |
| 1.741 | 0.202 | tC2Q | RR | 1 | R31C38[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_23_s0/Q |
| 2.002 | 0.260 | tNET | RR | 1 | BSRAM_R28[10] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s/DI[7] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | BSRAM_R28[10] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s/CLKA |
| 1.788 | 0.249 | tHld | 1 | BSRAM_R28[10] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686% |
| Required Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
Path6
Path Summary:
| Slack | 0.213 |
| Data Arrival Time | 2.002 |
| Data Required Time | 1.788 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_20_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s |
| Launch Clk | I_clk:[R] |
| Latch Clk | I_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | R27C37[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_20_s0/CLK |
| 1.741 | 0.202 | tC2Q | RR | 1 | R27C37[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_20_s0/Q |
| 2.002 | 0.260 | tNET | RR | 1 | BSRAM_R28[10] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s/DI[4] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | BSRAM_R28[10] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s/CLKA |
| 1.788 | 0.249 | tHld | 1 | BSRAM_R28[10] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686% |
| Required Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
Path7
Path Summary:
| Slack | 0.213 |
| Data Arrival Time | 2.002 |
| Data Required Time | 1.788 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_12_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_1_s |
| Launch Clk | I_clk:[R] |
| Latch Clk | I_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | R27C37[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_12_s0/CLK |
| 1.741 | 0.202 | tC2Q | RR | 1 | R27C37[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_12_s0/Q |
| 2.002 | 0.260 | tNET | RR | 1 | BSRAM_R28[9] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_1_s/DI[4] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | BSRAM_R28[9] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_1_s/CLKA |
| 1.788 | 0.249 | tHld | 1 | BSRAM_R28[9] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_1_s |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686% |
| Required Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
Path8
Path Summary:
| Slack | 0.225 |
| Data Arrival Time | 2.014 |
| Data Required Time | 1.788 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_28_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s |
| Launch Clk | I_clk:[R] |
| Latch Clk | I_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | R29C37[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_28_s0/CLK |
| 1.741 | 0.202 | tC2Q | RR | 1 | R29C37[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_28_s0/Q |
| 2.014 | 0.272 | tNET | RR | 1 | BSRAM_R28[11] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s/DI[4] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | BSRAM_R28[11] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s/CLKA |
| 1.788 | 0.249 | tHld | 1 | BSRAM_R28[11] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573% |
| Required Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
Path9
Path Summary:
| Slack | 0.225 |
| Data Arrival Time | 2.014 |
| Data Required Time | 1.788 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_21_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s |
| Launch Clk | I_clk:[R] |
| Latch Clk | I_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | R32C40[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_21_s0/CLK |
| 1.741 | 0.202 | tC2Q | RR | 1 | R32C40[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_21_s0/Q |
| 2.014 | 0.272 | tNET | RR | 1 | BSRAM_R28[10] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s/DI[5] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | BSRAM_R28[10] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s/CLKA |
| 1.788 | 0.249 | tHld | 1 | BSRAM_R28[10] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573% |
| Required Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
Path10
Path Summary:
| Slack | 0.335 |
| Data Arrival Time | 2.124 |
| Data Required Time | 1.788 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_31_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s |
| Launch Clk | I_clk:[R] |
| Latch Clk | I_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | R31C39[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_31_s0/CLK |
| 1.741 | 0.202 | tC2Q | RR | 1 | R31C39[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_31_s0/Q |
| 2.124 | 0.382 | tNET | RR | 1 | BSRAM_R28[11] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s/DI[7] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | BSRAM_R28[11] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s/CLKA |
| 1.788 | 0.249 | tHld | 1 | BSRAM_R28[11] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.382, 65.434%; tC2Q: 0.202, 34.566% |
| Required Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
Path11
Path Summary:
| Slack | 0.335 |
| Data Arrival Time | 2.124 |
| Data Required Time | 1.788 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_19_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s |
| Launch Clk | I_clk:[R] |
| Latch Clk | I_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | R32C37[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_19_s0/CLK |
| 1.741 | 0.202 | tC2Q | RR | 1 | R32C37[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_19_s0/Q |
| 2.124 | 0.382 | tNET | RR | 1 | BSRAM_R28[10] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s/DI[3] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | BSRAM_R28[10] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s/CLKA |
| 1.788 | 0.249 | tHld | 1 | BSRAM_R28[10] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.382, 65.434%; tC2Q: 0.202, 34.566% |
| Required Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
Path12
Path Summary:
| Slack | 0.335 |
| Data Arrival Time | 2.124 |
| Data Required Time | 1.788 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_9_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_1_s |
| Launch Clk | I_clk:[R] |
| Latch Clk | I_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | R27C38[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_9_s0/CLK |
| 1.741 | 0.202 | tC2Q | RR | 1 | R27C38[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_9_s0/Q |
| 2.124 | 0.382 | tNET | RR | 1 | BSRAM_R28[9] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_1_s/DI[1] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | BSRAM_R28[9] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_1_s/CLKA |
| 1.788 | 0.249 | tHld | 1 | BSRAM_R28[9] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_1_s |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.382, 65.434%; tC2Q: 0.202, 34.566% |
| Required Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
Path13
Path Summary:
| Slack | 0.335 |
| Data Arrival Time | 2.124 |
| Data Required Time | 1.788 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_8_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_1_s |
| Launch Clk | I_clk:[R] |
| Latch Clk | I_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | R29C38[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_8_s0/CLK |
| 1.741 | 0.202 | tC2Q | RR | 1 | R29C38[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_8_s0/Q |
| 2.124 | 0.382 | tNET | RR | 1 | BSRAM_R28[9] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_1_s/DI[0] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | BSRAM_R28[9] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_1_s/CLKA |
| 1.788 | 0.249 | tHld | 1 | BSRAM_R28[9] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_1_s |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.382, 65.434%; tC2Q: 0.202, 34.566% |
| Required Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
Path14
Path Summary:
| Slack | 0.337 |
| Data Arrival Time | 2.125 |
| Data Required Time | 1.788 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_25_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s |
| Launch Clk | I_clk:[R] |
| Latch Clk | I_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | R27C39[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_25_s0/CLK |
| 1.740 | 0.201 | tC2Q | RF | 1 | R27C39[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_25_s0/Q |
| 2.125 | 0.385 | tNET | FF | 1 | BSRAM_R28[11] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s/DI[1] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | BSRAM_R28[11] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s/CLKA |
| 1.788 | 0.249 | tHld | 1 | BSRAM_R28[11] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.385, 65.673%; tC2Q: 0.201, 34.327% |
| Required Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
Path15
Path Summary:
| Slack | 0.340 |
| Data Arrival Time | 0.537 |
| Data Required Time | 0.196 |
| From | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/User_data_i_0_s2 |
| To | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/User_data_i_0_s12 |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R22C26[0][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/User_data_i_0_s2/CLK |
| 0.386 | 0.202 | tC2Q | RR | 19 | R22C26[0][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/User_data_i_0_s2/Q |
| 0.537 | 0.150 | tNET | RR | 1 | R23C26 | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/User_data_i_0_s12/AD[0] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R23C26 | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/User_data_i_0_s12/CLK |
| 0.196 | 0.012 | tHld | 1 | R23C26 | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/User_data_i_0_s12 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.150, 42.686%; tC2Q: 0.202, 57.314% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path16
Path Summary:
| Slack | 0.347 |
| Data Arrival Time | 2.136 |
| Data Required Time | 1.788 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_10_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_1_s |
| Launch Clk | I_clk:[R] |
| Latch Clk | I_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | R34C37[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_10_s0/CLK |
| 1.741 | 0.202 | tC2Q | RR | 1 | R34C37[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_10_s0/Q |
| 2.136 | 0.394 | tNET | RR | 1 | BSRAM_R28[9] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_1_s/DI[2] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | BSRAM_R28[9] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_1_s/CLKA |
| 1.788 | 0.249 | tHld | 1 | BSRAM_R28[9] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_1_s |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.394, 66.134%; tC2Q: 0.202, 33.866% |
| Required Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
Path17
Path Summary:
| Slack | 0.363 |
| Data Arrival Time | 2.151 |
| Data Required Time | 1.788 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_30_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s |
| Launch Clk | I_clk:[R] |
| Latch Clk | I_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | R32C38[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_30_s0/CLK |
| 1.741 | 0.202 | tC2Q | RR | 1 | R32C38[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_30_s0/Q |
| 2.151 | 0.410 | tNET | RR | 1 | BSRAM_R28[11] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s/DI[6] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | BSRAM_R28[11] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s/CLKA |
| 1.788 | 0.249 | tHld | 1 | BSRAM_R28[11] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.410, 66.974%; tC2Q: 0.202, 33.026% |
| Required Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
Path18
Path Summary:
| Slack | 0.363 |
| Data Arrival Time | 2.151 |
| Data Required Time | 1.788 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_18_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s |
| Launch Clk | I_clk:[R] |
| Latch Clk | I_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | R34C37[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_18_s0/CLK |
| 1.741 | 0.202 | tC2Q | RR | 1 | R34C37[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_18_s0/Q |
| 2.151 | 0.410 | tNET | RR | 1 | BSRAM_R28[10] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s/DI[2] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | BSRAM_R28[10] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s/CLKA |
| 1.788 | 0.249 | tHld | 1 | BSRAM_R28[10] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.410, 66.974%; tC2Q: 0.202, 33.026% |
| Required Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
Path19
Path Summary:
| Slack | 0.363 |
| Data Arrival Time | 2.151 |
| Data Required Time | 1.788 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_4_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_0_s |
| Launch Clk | I_clk:[R] |
| Latch Clk | I_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | R27C37[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_4_s0/CLK |
| 1.741 | 0.202 | tC2Q | RR | 1 | R27C37[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_4_s0/Q |
| 2.151 | 0.410 | tNET | RR | 1 | BSRAM_R28[8] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_0_s/DI[4] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | BSRAM_R28[8] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_0_s/CLKA |
| 1.788 | 0.249 | tHld | 1 | BSRAM_R28[8] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_0_s |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.410, 66.974%; tC2Q: 0.202, 33.026% |
| Required Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
Path20
Path Summary:
| Slack | 0.363 |
| Data Arrival Time | 2.151 |
| Data Required Time | 1.788 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_0_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_0_s |
| Launch Clk | I_clk:[R] |
| Latch Clk | I_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | R29C38[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_0_s0/CLK |
| 1.741 | 0.202 | tC2Q | RR | 1 | R29C38[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_0_s0/Q |
| 2.151 | 0.410 | tNET | RR | 1 | BSRAM_R28[8] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_0_s/DI[0] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | BSRAM_R28[8] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_0_s/CLKA |
| 1.788 | 0.249 | tHld | 1 | BSRAM_R28[8] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_0_s |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.410, 66.974%; tC2Q: 0.202, 33.026% |
| Required Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
Path21
Path Summary:
| Slack | 0.364 |
| Data Arrival Time | 2.021 |
| Data Required Time | 1.657 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.wbin_0_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_1_s |
| Launch Clk | I_clk:[R] |
| Latch Clk | I_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | R34C36[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.wbin_0_s0/CLK |
| 1.741 | 0.202 | tC2Q | RR | 8 | R34C36[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.wbin_0_s0/Q |
| 2.021 | 0.280 | tNET | RR | 1 | BSRAM_R28[9] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_1_s/ADA[3] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | BSRAM_R28[9] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_1_s/CLKA |
| 1.657 | 0.118 | tHld | 1 | BSRAM_R28[9] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_1_s |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.280, 58.058%; tC2Q: 0.202, 41.942% |
| Required Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
Path22
Path Summary:
| Slack | 0.375 |
| Data Arrival Time | 2.163 |
| Data Required Time | 1.788 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_26_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s |
| Launch Clk | I_clk:[R] |
| Latch Clk | I_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | R35C37[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_26_s0/CLK |
| 1.741 | 0.202 | tC2Q | RR | 1 | R35C37[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_24b_32b/dma_d_32b_26_s0/Q |
| 2.163 | 0.422 | tNET | RR | 1 | BSRAM_R28[11] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s/DI[2] |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | BSRAM_R28[11] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s/CLKA |
| 1.788 | 0.249 | tHld | 1 | BSRAM_R28[11] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.422, 67.614%; tC2Q: 0.202, 32.386% |
| Required Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
Path23
Path Summary:
| Slack | 0.424 |
| Data Arrival Time | 1.975 |
| Data Required Time | 1.550 |
| From | cnt_vs_3_s0 |
| To | cnt_vs_3_s0 |
| Launch Clk | I_clk:[R] |
| Latch Clk | I_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | R35C16[1][A] | cnt_vs_3_s0/CLK |
| 1.741 | 0.202 | tC2Q | RR | 1 | R35C16[1][A] | cnt_vs_3_s0/Q |
| 1.743 | 0.001 | tNET | RR | 2 | R35C16[1][A] | n187_s/I1 |
| 1.975 | 0.232 | tINS | RF | 1 | R35C16[1][A] | n187_s/SUM |
| 1.975 | 0.000 | tNET | FF | 1 | R35C16[1][A] | cnt_vs_3_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | R35C16[1][A] | cnt_vs_3_s0/CLK |
| 1.550 | 0.011 | tHld | 1 | R35C16[1][A] | cnt_vs_3_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
| Arrival Data Path Delay | cell: 0.232, 53.306%; route: 0.001, 0.281%; tC2Q: 0.202, 46.413% |
| Required Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
Path24
Path Summary:
| Slack | 0.425 |
| Data Arrival Time | 1.976 |
| Data Required Time | 1.550 |
| From | testpattern_inst/De_cyc_hcnt_3_s3 |
| To | testpattern_inst/De_cyc_hcnt_3_s3 |
| Launch Clk | I_clk:[R] |
| Latch Clk | I_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | R33C24[0][A] | testpattern_inst/De_cyc_hcnt_3_s3/CLK |
| 1.741 | 0.202 | tC2Q | RR | 2 | R33C24[0][A] | testpattern_inst/De_cyc_hcnt_3_s3/Q |
| 1.744 | 0.002 | tNET | RR | 1 | R33C24[0][A] | testpattern_inst/n636_s6/I2 |
| 1.976 | 0.232 | tINS | RF | 1 | R33C24[0][A] | testpattern_inst/n636_s6/F |
| 1.976 | 0.000 | tNET | FF | 1 | R33C24[0][A] | testpattern_inst/De_cyc_hcnt_3_s3/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | R33C24[0][A] | testpattern_inst/De_cyc_hcnt_3_s3/CLK |
| 1.550 | 0.011 | tHld | 1 | R33C24[0][A] | testpattern_inst/De_cyc_hcnt_3_s3 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
| Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
| Required Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
Path25
Path Summary:
| Slack | 0.425 |
| Data Arrival Time | 1.976 |
| Data Required Time | 1.550 |
| From | testpattern_inst/Sqr_v_trig_s1 |
| To | testpattern_inst/Sqr_v_trig_s1 |
| Launch Clk | I_clk:[R] |
| Latch Clk | I_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | R33C24[1][A] | testpattern_inst/Sqr_v_trig_s1/CLK |
| 1.741 | 0.202 | tC2Q | RR | 2 | R33C24[1][A] | testpattern_inst/Sqr_v_trig_s1/Q |
| 1.744 | 0.002 | tNET | RR | 1 | R33C24[1][A] | testpattern_inst/n1320_s11/I0 |
| 1.976 | 0.232 | tINS | RF | 1 | R33C24[1][A] | testpattern_inst/n1320_s11/F |
| 1.976 | 0.000 | tNET | FF | 1 | R33C24[1][A] | testpattern_inst/Sqr_v_trig_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | I_clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL7[A] | I_clk_ibuf/I |
| 0.675 | 0.675 | tINS | RR | 339 | IOL7[A] | I_clk_ibuf/O |
| 1.539 | 0.864 | tNET | RR | 1 | R33C24[1][A] | testpattern_inst/Sqr_v_trig_s1/CLK |
| 1.550 | 0.011 | tHld | 1 | R33C24[1][A] | testpattern_inst/Sqr_v_trig_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
| Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
| Required Clock Path Delay | cell: 0.675, 43.879%; route: 0.864, 56.121% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 1.908 |
| Data Arrival Time | 6.231 |
| Data Required Time | 8.138 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s |
| Launch Clk | sdrc_clk:[F] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | sdrc_clk | ||||
| 4.167 | 0.000 | tCL | FF | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 4.428 | 0.261 | tNET | FF | 1 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK |
| 4.660 | 0.232 | tC2Q | FF | 75 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q |
| 6.231 | 1.570 | tNET | FF | 8 | BSRAM_R28[11] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s/RESETB |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | BSRAM_R28[11] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s/CLKB |
| 8.138 | -0.438 | tSu | 1 | BSRAM_R28[11] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_3_s |
Path Statistics:
| Clock Skew | -0.018 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.261, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path2
Path Summary:
| Slack | 1.908 |
| Data Arrival Time | 6.231 |
| Data Required Time | 8.138 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s |
| Launch Clk | sdrc_clk:[F] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | sdrc_clk | ||||
| 4.167 | 0.000 | tCL | FF | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 4.428 | 0.261 | tNET | FF | 1 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK |
| 4.660 | 0.232 | tC2Q | FF | 75 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q |
| 6.231 | 1.570 | tNET | FF | 8 | BSRAM_R28[10] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s/RESETB |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | BSRAM_R28[10] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s/CLKB |
| 8.138 | -0.438 | tSu | 1 | BSRAM_R28[10] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_2_s |
Path Statistics:
| Clock Skew | -0.018 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.261, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path3
Path Summary:
| Slack | 1.908 |
| Data Arrival Time | 6.231 |
| Data Required Time | 8.138 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_1_s |
| Launch Clk | sdrc_clk:[F] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | sdrc_clk | ||||
| 4.167 | 0.000 | tCL | FF | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 4.428 | 0.261 | tNET | FF | 1 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK |
| 4.660 | 0.232 | tC2Q | FF | 75 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q |
| 6.231 | 1.570 | tNET | FF | 8 | BSRAM_R28[9] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_1_s/RESETB |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | BSRAM_R28[9] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_1_s/CLKB |
| 8.138 | -0.438 | tSu | 1 | BSRAM_R28[9] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_1_s |
Path Statistics:
| Clock Skew | -0.018 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.261, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path4
Path Summary:
| Slack | 1.908 |
| Data Arrival Time | 6.231 |
| Data Required Time | 8.138 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_0_s |
| Launch Clk | sdrc_clk:[F] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | sdrc_clk | ||||
| 4.167 | 0.000 | tCL | FF | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 4.428 | 0.261 | tNET | FF | 1 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK |
| 4.660 | 0.232 | tC2Q | FF | 75 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q |
| 6.231 | 1.570 | tNET | FF | 8 | BSRAM_R28[8] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_0_s/RESETB |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | BSRAM_R28[8] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_0_s/CLKB |
| 8.138 | -0.438 | tSu | 1 | BSRAM_R28[8] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.mem_Equal.mem_0_0_s |
Path Statistics:
| Clock Skew | -0.018 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.261, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path5
Path Summary:
| Slack | 2.311 |
| Data Arrival Time | 6.231 |
| Data Required Time | 8.541 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_dly_10_s0 |
| Launch Clk | sdrc_clk:[F] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | sdrc_clk | ||||
| 4.167 | 0.000 | tCL | FF | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 4.428 | 0.261 | tNET | FF | 1 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK |
| 4.660 | 0.232 | tC2Q | FF | 75 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q |
| 6.231 | 1.570 | tNET | FF | 1 | R31C34[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_dly_10_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | R31C34[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_dly_10_s0/CLK |
| 8.541 | -0.035 | tSu | 1 | R31C34[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/raddr_num_dly_10_s0 |
Path Statistics:
| Clock Skew | -0.018 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.261, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path6
Path Summary:
| Slack | 2.311 |
| Data Arrival Time | 6.231 |
| Data Required Time | 8.541 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_0_s0 |
| Launch Clk | sdrc_clk:[F] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | sdrc_clk | ||||
| 4.167 | 0.000 | tCL | FF | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 4.428 | 0.261 | tNET | FF | 1 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK |
| 4.660 | 0.232 | tC2Q | FF | 75 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q |
| 6.231 | 1.570 | tNET | FF | 1 | R32C34[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | R32C34[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_0_s0/CLK |
| 8.541 | -0.035 | tSu | 1 | R32C34[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_0_s0 |
Path Statistics:
| Clock Skew | -0.018 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.261, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path7
Path Summary:
| Slack | 2.311 |
| Data Arrival Time | 6.231 |
| Data Required Time | 8.541 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_1_s0 |
| Launch Clk | sdrc_clk:[F] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | sdrc_clk | ||||
| 4.167 | 0.000 | tCL | FF | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 4.428 | 0.261 | tNET | FF | 1 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK |
| 4.660 | 0.232 | tC2Q | FF | 75 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q |
| 6.231 | 1.570 | tNET | FF | 1 | R32C34[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | R32C34[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_1_s0/CLK |
| 8.541 | -0.035 | tSu | 1 | R32C34[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_1_s0 |
Path Statistics:
| Clock Skew | -0.018 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.261, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path8
Path Summary:
| Slack | 2.311 |
| Data Arrival Time | 6.231 |
| Data Required Time | 8.541 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_2_s0 |
| Launch Clk | sdrc_clk:[F] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | sdrc_clk | ||||
| 4.167 | 0.000 | tCL | FF | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 4.428 | 0.261 | tNET | FF | 1 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK |
| 4.660 | 0.232 | tC2Q | FF | 75 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q |
| 6.231 | 1.570 | tNET | FF | 1 | R32C34[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_2_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | R32C34[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_2_s0/CLK |
| 8.541 | -0.035 | tSu | 1 | R32C34[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_2_s0 |
Path Statistics:
| Clock Skew | -0.018 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.261, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path9
Path Summary:
| Slack | 2.311 |
| Data Arrival Time | 6.231 |
| Data Required Time | 8.541 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_3_s0 |
| Launch Clk | sdrc_clk:[F] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | sdrc_clk | ||||
| 4.167 | 0.000 | tCL | FF | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 4.428 | 0.261 | tNET | FF | 1 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK |
| 4.660 | 0.232 | tC2Q | FF | 75 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q |
| 6.231 | 1.570 | tNET | FF | 1 | R32C34[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_3_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | R32C34[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_3_s0/CLK |
| 8.541 | -0.035 | tSu | 1 | R32C34[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_3_s0 |
Path Statistics:
| Clock Skew | -0.018 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.261, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path10
Path Summary:
| Slack | 2.311 |
| Data Arrival Time | 6.231 |
| Data Required Time | 8.541 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_4_s0 |
| Launch Clk | sdrc_clk:[F] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | sdrc_clk | ||||
| 4.167 | 0.000 | tCL | FF | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 4.428 | 0.261 | tNET | FF | 1 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK |
| 4.660 | 0.232 | tC2Q | FF | 75 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q |
| 6.231 | 1.570 | tNET | FF | 1 | R32C34[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_4_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | R32C34[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_4_s0/CLK |
| 8.541 | -0.035 | tSu | 1 | R32C34[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_4_s0 |
Path Statistics:
| Clock Skew | -0.018 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.261, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path11
Path Summary:
| Slack | 2.311 |
| Data Arrival Time | 6.231 |
| Data Required Time | 8.541 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_5_s0 |
| Launch Clk | sdrc_clk:[F] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | sdrc_clk | ||||
| 4.167 | 0.000 | tCL | FF | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 4.428 | 0.261 | tNET | FF | 1 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK |
| 4.660 | 0.232 | tC2Q | FF | 75 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q |
| 6.231 | 1.570 | tNET | FF | 1 | R32C35[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_5_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | R32C35[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_5_s0/CLK |
| 8.541 | -0.035 | tSu | 1 | R32C35[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_5_s0 |
Path Statistics:
| Clock Skew | -0.018 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.261, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path12
Path Summary:
| Slack | 2.311 |
| Data Arrival Time | 6.231 |
| Data Required Time | 8.541 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_6_s0 |
| Launch Clk | sdrc_clk:[F] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | sdrc_clk | ||||
| 4.167 | 0.000 | tCL | FF | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 4.428 | 0.261 | tNET | FF | 1 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK |
| 4.660 | 0.232 | tC2Q | FF | 75 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q |
| 6.231 | 1.570 | tNET | FF | 1 | R32C35[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_6_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | R32C35[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_6_s0/CLK |
| 8.541 | -0.035 | tSu | 1 | R32C35[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_6_s0 |
Path Statistics:
| Clock Skew | -0.018 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.261, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path13
Path Summary:
| Slack | 2.311 |
| Data Arrival Time | 6.231 |
| Data Required Time | 8.541 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_7_s0 |
| Launch Clk | sdrc_clk:[F] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | sdrc_clk | ||||
| 4.167 | 0.000 | tCL | FF | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 4.428 | 0.261 | tNET | FF | 1 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK |
| 4.660 | 0.232 | tC2Q | FF | 75 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q |
| 6.231 | 1.570 | tNET | FF | 1 | R32C35[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_7_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | R32C35[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_7_s0/CLK |
| 8.541 | -0.035 | tSu | 1 | R32C35[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_7_s0 |
Path Statistics:
| Clock Skew | -0.018 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.261, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path14
Path Summary:
| Slack | 2.311 |
| Data Arrival Time | 6.231 |
| Data Required Time | 8.541 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_8_s0 |
| Launch Clk | sdrc_clk:[F] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | sdrc_clk | ||||
| 4.167 | 0.000 | tCL | FF | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 4.428 | 0.261 | tNET | FF | 1 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK |
| 4.660 | 0.232 | tC2Q | FF | 75 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q |
| 6.231 | 1.570 | tNET | FF | 1 | R32C35[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_8_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | R32C35[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_8_s0/CLK |
| 8.541 | -0.035 | tSu | 1 | R32C35[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_8_s0 |
Path Statistics:
| Clock Skew | -0.018 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.261, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path15
Path Summary:
| Slack | 2.311 |
| Data Arrival Time | 6.231 |
| Data Required Time | 8.541 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_9_s0 |
| Launch Clk | sdrc_clk:[F] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | sdrc_clk | ||||
| 4.167 | 0.000 | tCL | FF | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 4.428 | 0.261 | tNET | FF | 1 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK |
| 4.660 | 0.232 | tC2Q | FF | 75 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q |
| 6.231 | 1.570 | tNET | FF | 1 | R32C35[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_9_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | R32C35[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_9_s0/CLK |
| 8.541 | -0.035 | tSu | 1 | R32C35[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_9_s0 |
Path Statistics:
| Clock Skew | -0.018 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.261, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path16
Path Summary:
| Slack | 2.311 |
| Data Arrival Time | 6.231 |
| Data Required Time | 8.541 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_10_s0 |
| Launch Clk | sdrc_clk:[F] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | sdrc_clk | ||||
| 4.167 | 0.000 | tCL | FF | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 4.428 | 0.261 | tNET | FF | 1 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK |
| 4.660 | 0.232 | tC2Q | FF | 75 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q |
| 6.231 | 1.570 | tNET | FF | 1 | R32C35[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_10_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | R32C35[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_10_s0/CLK |
| 8.541 | -0.035 | tSu | 1 | R32C35[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_10_s0 |
Path Statistics:
| Clock Skew | -0.018 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.261, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path17
Path Summary:
| Slack | 2.311 |
| Data Arrival Time | 6.231 |
| Data Required Time | 8.541 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_11_s0 |
| Launch Clk | sdrc_clk:[F] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | sdrc_clk | ||||
| 4.167 | 0.000 | tCL | FF | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 4.428 | 0.261 | tNET | FF | 1 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK |
| 4.660 | 0.232 | tC2Q | FF | 75 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q |
| 6.231 | 1.570 | tNET | FF | 1 | R32C36[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_11_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | R32C36[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_11_s0/CLK |
| 8.541 | -0.035 | tSu | 1 | R32C36[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_11_s0 |
Path Statistics:
| Clock Skew | -0.018 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.261, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path18
Path Summary:
| Slack | 2.311 |
| Data Arrival Time | 6.231 |
| Data Required Time | 8.541 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0 |
| Launch Clk | sdrc_clk:[F] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | sdrc_clk | ||||
| 4.167 | 0.000 | tCL | FF | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 4.428 | 0.261 | tNET | FF | 1 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK |
| 4.660 | 0.232 | tC2Q | FF | 75 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q |
| 6.231 | 1.570 | tNET | FF | 1 | R31C31[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0/PRESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | R31C31[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0/CLK |
| 8.541 | -0.035 | tSu | 1 | R31C31[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0 |
Path Statistics:
| Clock Skew | -0.018 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.261, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path19
Path Summary:
| Slack | 2.311 |
| Data Arrival Time | 6.231 |
| Data Required Time | 8.541 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_0_s1 |
| Launch Clk | sdrc_clk:[F] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | sdrc_clk | ||||
| 4.167 | 0.000 | tCL | FF | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 4.428 | 0.261 | tNET | FF | 1 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK |
| 4.660 | 0.232 | tC2Q | FF | 75 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q |
| 6.231 | 1.570 | tNET | FF | 1 | R33C32[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_0_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | R33C32[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_0_s1/CLK |
| 8.541 | -0.035 | tSu | 1 | R33C32[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_0_s1 |
Path Statistics:
| Clock Skew | -0.018 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.261, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path20
Path Summary:
| Slack | 2.311 |
| Data Arrival Time | 6.231 |
| Data Required Time | 8.541 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_1_s1 |
| Launch Clk | sdrc_clk:[F] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | sdrc_clk | ||||
| 4.167 | 0.000 | tCL | FF | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 4.428 | 0.261 | tNET | FF | 1 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK |
| 4.660 | 0.232 | tC2Q | FF | 75 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q |
| 6.231 | 1.570 | tNET | FF | 1 | R33C32[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_1_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | R33C32[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_1_s1/CLK |
| 8.541 | -0.035 | tSu | 1 | R33C32[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_1_s1 |
Path Statistics:
| Clock Skew | -0.018 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.261, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path21
Path Summary:
| Slack | 2.311 |
| Data Arrival Time | 6.231 |
| Data Required Time | 8.541 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_2_s1 |
| Launch Clk | sdrc_clk:[F] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | sdrc_clk | ||||
| 4.167 | 0.000 | tCL | FF | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 4.428 | 0.261 | tNET | FF | 1 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK |
| 4.660 | 0.232 | tC2Q | FF | 75 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q |
| 6.231 | 1.570 | tNET | FF | 1 | R35C32[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_2_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | R35C32[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_2_s1/CLK |
| 8.541 | -0.035 | tSu | 1 | R35C32[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_2_s1 |
Path Statistics:
| Clock Skew | -0.018 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.261, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path22
Path Summary:
| Slack | 2.311 |
| Data Arrival Time | 6.231 |
| Data Required Time | 8.541 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_3_s1 |
| Launch Clk | sdrc_clk:[F] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | sdrc_clk | ||||
| 4.167 | 0.000 | tCL | FF | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 4.428 | 0.261 | tNET | FF | 1 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK |
| 4.660 | 0.232 | tC2Q | FF | 75 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q |
| 6.231 | 1.570 | tNET | FF | 1 | R35C32[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_3_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | R35C32[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_3_s1/CLK |
| 8.541 | -0.035 | tSu | 1 | R35C32[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_3_s1 |
Path Statistics:
| Clock Skew | -0.018 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.261, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path23
Path Summary:
| Slack | 2.311 |
| Data Arrival Time | 6.231 |
| Data Required Time | 8.541 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_4_s1 |
| Launch Clk | sdrc_clk:[F] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | sdrc_clk | ||||
| 4.167 | 0.000 | tCL | FF | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 4.428 | 0.261 | tNET | FF | 1 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK |
| 4.660 | 0.232 | tC2Q | FF | 75 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q |
| 6.231 | 1.570 | tNET | FF | 1 | R35C32[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_4_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | R35C32[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_4_s1/CLK |
| 8.541 | -0.035 | tSu | 1 | R35C32[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_4_s1 |
Path Statistics:
| Clock Skew | -0.018 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.261, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path24
Path Summary:
| Slack | 2.311 |
| Data Arrival Time | 6.231 |
| Data Required Time | 8.541 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_5_s1 |
| Launch Clk | sdrc_clk:[F] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | sdrc_clk | ||||
| 4.167 | 0.000 | tCL | FF | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 4.428 | 0.261 | tNET | FF | 1 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK |
| 4.660 | 0.232 | tC2Q | FF | 75 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q |
| 6.231 | 1.570 | tNET | FF | 1 | R35C34[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_5_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | R35C34[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_5_s1/CLK |
| 8.541 | -0.035 | tSu | 1 | R35C34[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_5_s1 |
Path Statistics:
| Clock Skew | -0.018 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.261, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Path25
Path Summary:
| Slack | 2.311 |
| Data Arrival Time | 6.231 |
| Data Required Time | 8.541 |
| From | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_6_s1 |
| Launch Clk | sdrc_clk:[F] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 4.167 | 4.167 | active clock edge time | ||||
| 4.167 | 0.000 | sdrc_clk | ||||
| 4.167 | 0.000 | tCL | FF | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 4.428 | 0.261 | tNET | FF | 1 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK |
| 4.660 | 0.232 | tC2Q | FF | 75 | R34C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/Q |
| 6.231 | 1.570 | tNET | FF | 1 | R35C33[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_6_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 8.333 | 8.333 | active clock edge time | ||||
| 8.333 | 0.000 | sdrc_clk | ||||
| 8.333 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.576 | 0.243 | tNET | RR | 1 | R35C33[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_6_s1/CLK |
| 8.541 | -0.035 | tSu | 1 | R35C33[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Equal.rptr_6_s1 |
Path Statistics:
| Clock Skew | -0.018 |
| Setup Relationship | 4.166 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.261, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.570, 87.127%; tC2Q: 0.232, 12.873% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.243, 100.000% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 0.937 |
| Data Arrival Time | 1.132 |
| Data Required Time | 0.195 |
| From | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IDLE_s4 |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 296 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q |
| 1.132 | 0.746 | tNET | RR | 1 | R27C28[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IDLE_s4/PRESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R27C28[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IDLE_s4/CLK |
| 0.195 | 0.011 | tHld | 1 | R27C28[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IDLE_s4 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.746, 78.688%; tC2Q: 0.202, 21.312% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path2
Path Summary:
| Slack | 0.937 |
| Data Arrival Time | 1.132 |
| Data Required Time | 0.195 |
| From | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0 |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 296 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q |
| 1.132 | 0.746 | tNET | RR | 1 | R27C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R27C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R27C28[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_IFF0_WRITE_DDR_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.746, 78.688%; tC2Q: 0.202, 21.312% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path3
Path Summary:
| Slack | 0.937 |
| Data Arrival Time | 1.132 |
| Data Required Time | 0.195 |
| From | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_OFF0_READ_DDR_s0 |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 296 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q |
| 1.132 | 0.746 | tNET | RR | 1 | R20C28[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_OFF0_READ_DDR_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R20C28[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_OFF0_READ_DDR_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R20C28[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_OFF0_READ_DDR_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.746, 78.688%; tC2Q: 0.202, 21.312% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path4
Path Summary:
| Slack | 0.937 |
| Data Arrival Time | 1.132 |
| Data Required Time | 0.195 |
| From | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0 |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 296 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q |
| 1.132 | 0.746 | tNET | RR | 1 | R29C28[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R29C28[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R29C28[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u_dma_bus_arbiter/current_state.ST_RDY_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.746, 78.688%; tC2Q: 0.202, 21.312% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path5
Path Summary:
| Slack | 0.937 |
| Data Arrival Time | 1.132 |
| Data Required Time | 0.195 |
| From | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_rd_baseaddr_19_s0 |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 296 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q |
| 1.132 | 0.746 | tNET | RR | 1 | R26C34[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_rd_baseaddr_19_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R26C34[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_rd_baseaddr_19_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R26C34[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_rd_baseaddr_19_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.746, 78.688%; tC2Q: 0.202, 21.312% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path6
Path Summary:
| Slack | 0.937 |
| Data Arrival Time | 1.132 |
| Data Required Time | 0.195 |
| From | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_rd_baseaddr_20_s0 |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 296 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q |
| 1.132 | 0.746 | tNET | RR | 1 | R26C34[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_rd_baseaddr_20_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R26C34[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_rd_baseaddr_20_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R26C34[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_rd_baseaddr_20_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.746, 78.688%; tC2Q: 0.202, 21.312% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path7
Path Summary:
| Slack | 0.937 |
| Data Arrival Time | 1.132 |
| Data Required Time | 0.195 |
| From | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_wr_baseaddr_19_s0 |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 296 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q |
| 1.132 | 0.746 | tNET | RR | 1 | R26C34[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_wr_baseaddr_19_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R26C34[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_wr_baseaddr_19_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R26C34[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_wr_baseaddr_19_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.746, 78.688%; tC2Q: 0.202, 21.312% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path8
Path Summary:
| Slack | 0.937 |
| Data Arrival Time | 1.132 |
| Data Required Time | 0.195 |
| From | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_wr_baseaddr_20_s0 |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 296 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q |
| 1.132 | 0.746 | tNET | RR | 1 | R26C34[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_wr_baseaddr_20_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R26C34[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_wr_baseaddr_20_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R26C34[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/dma_wr_baseaddr_20_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.746, 78.688%; tC2Q: 0.202, 21.312% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path9
Path Summary:
| Slack | 0.937 |
| Data Arrival Time | 1.132 |
| Data Required Time | 0.195 |
| From | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/rd_ptr_0_s0 |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 296 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q |
| 1.132 | 0.746 | tNET | RR | 1 | R27C34[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/rd_ptr_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R27C34[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/rd_ptr_0_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R27C34[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/rd_ptr_0_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.746, 78.688%; tC2Q: 0.202, 21.312% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path10
Path Summary:
| Slack | 0.937 |
| Data Arrival Time | 1.132 |
| Data Required Time | 0.195 |
| From | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/rd_ptr_1_s0 |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 296 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q |
| 1.132 | 0.746 | tNET | RR | 1 | R27C34[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/rd_ptr_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R27C34[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/rd_ptr_1_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R27C34[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/rd_ptr_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.746, 78.688%; tC2Q: 0.202, 21.312% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path11
Path Summary:
| Slack | 0.937 |
| Data Arrival Time | 1.132 |
| Data Required Time | 0.195 |
| From | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/wr_ptr_0_s0 |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 296 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q |
| 1.132 | 0.746 | tNET | RR | 1 | R26C34[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/wr_ptr_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R26C34[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/wr_ptr_0_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R26C34[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/wr_ptr_0_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.746, 78.688%; tC2Q: 0.202, 21.312% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path12
Path Summary:
| Slack | 0.937 |
| Data Arrival Time | 1.132 |
| Data Required Time | 0.195 |
| From | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/wr_ptr_1_s0 |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 296 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q |
| 1.132 | 0.746 | tNET | RR | 1 | R27C34[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/wr_ptr_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R27C34[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/wr_ptr_1_s0/CLK |
| 0.195 | 0.011 | tHld | 1 | R27C34[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/wr_ptr_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.746, 78.688%; tC2Q: 0.202, 21.312% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path13
Path Summary:
| Slack | 0.937 |
| Data Arrival Time | 1.132 |
| Data Required Time | 0.195 |
| From | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_req_o_s5 |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 296 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q |
| 1.132 | 0.746 | tNET | RR | 1 | R22C32[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_req_o_s5/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R22C32[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_req_o_s5/CLK |
| 0.195 | 0.011 | tHld | 1 | R22C32[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_req_o_s5 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.746, 78.688%; tC2Q: 0.202, 21.312% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path14
Path Summary:
| Slack | 0.937 |
| Data Arrival Time | 1.132 |
| Data Required Time | 0.195 |
| From | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_0_s1 |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 296 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q |
| 1.132 | 0.746 | tNET | RR | 1 | R18C30[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_0_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R18C30[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_0_s1/CLK |
| 0.195 | 0.011 | tHld | 1 | R18C30[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_0_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.746, 78.688%; tC2Q: 0.202, 21.312% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path15
Path Summary:
| Slack | 0.937 |
| Data Arrival Time | 1.132 |
| Data Required Time | 0.195 |
| From | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_1_s1 |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 296 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q |
| 1.132 | 0.746 | tNET | RR | 1 | R18C30[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_1_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R18C30[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_1_s1/CLK |
| 0.195 | 0.011 | tHld | 1 | R18C30[0][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_1_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.746, 78.688%; tC2Q: 0.202, 21.312% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path16
Path Summary:
| Slack | 0.937 |
| Data Arrival Time | 1.132 |
| Data Required Time | 0.195 |
| From | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_2_s1 |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 296 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q |
| 1.132 | 0.746 | tNET | RR | 1 | R18C30[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_2_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R18C30[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_2_s1/CLK |
| 0.195 | 0.011 | tHld | 1 | R18C30[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/cmd_cnt_2_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.746, 78.688%; tC2Q: 0.202, 21.312% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path17
Path Summary:
| Slack | 0.937 |
| Data Arrival Time | 1.132 |
| Data Required Time | 0.195 |
| From | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_0_s1 |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 296 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q |
| 1.132 | 0.746 | tNET | RR | 1 | R20C32[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_0_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R20C32[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_0_s1/CLK |
| 0.195 | 0.011 | tHld | 1 | R20C32[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_0_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.746, 78.688%; tC2Q: 0.202, 21.312% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path18
Path Summary:
| Slack | 0.937 |
| Data Arrival Time | 1.132 |
| Data Required Time | 0.195 |
| From | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_1_s1 |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 296 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q |
| 1.132 | 0.746 | tNET | RR | 1 | R20C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_1_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R20C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_1_s1/CLK |
| 0.195 | 0.011 | tHld | 1 | R20C33[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_1_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.746, 78.688%; tC2Q: 0.202, 21.312% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path19
Path Summary:
| Slack | 0.937 |
| Data Arrival Time | 1.132 |
| Data Required Time | 0.195 |
| From | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_2_s1 |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 296 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q |
| 1.132 | 0.746 | tNET | RR | 1 | R20C31[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_2_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R20C31[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_2_s1/CLK |
| 0.195 | 0.011 | tHld | 1 | R20C31[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_2_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.746, 78.688%; tC2Q: 0.202, 21.312% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path20
Path Summary:
| Slack | 0.937 |
| Data Arrival Time | 1.132 |
| Data Required Time | 0.195 |
| From | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_3_s1 |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 296 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q |
| 1.132 | 0.746 | tNET | RR | 1 | R20C31[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_3_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R20C31[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_3_s1/CLK |
| 0.195 | 0.011 | tHld | 1 | R20C31[2][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_3_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.746, 78.688%; tC2Q: 0.202, 21.312% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path21
Path Summary:
| Slack | 0.937 |
| Data Arrival Time | 1.132 |
| Data Required Time | 0.195 |
| From | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_4_s1 |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 296 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q |
| 1.132 | 0.746 | tNET | RR | 1 | R18C31[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_4_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R18C31[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_4_s1/CLK |
| 0.195 | 0.011 | tHld | 1 | R18C31[2][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_4_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.746, 78.688%; tC2Q: 0.202, 21.312% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path22
Path Summary:
| Slack | 0.937 |
| Data Arrival Time | 1.132 |
| Data Required Time | 0.195 |
| From | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_5_s1 |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 296 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q |
| 1.132 | 0.746 | tNET | RR | 1 | R18C31[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_5_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R18C31[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_5_s1/CLK |
| 0.195 | 0.011 | tHld | 1 | R18C31[0][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_5_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.746, 78.688%; tC2Q: 0.202, 21.312% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path23
Path Summary:
| Slack | 0.937 |
| Data Arrival Time | 1.132 |
| Data Required Time | 0.195 |
| From | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_6_s1 |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 296 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q |
| 1.132 | 0.746 | tNET | RR | 1 | R18C31[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_6_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R18C31[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_6_s1/CLK |
| 0.195 | 0.011 | tHld | 1 | R18C31[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_6_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.746, 78.688%; tC2Q: 0.202, 21.312% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path24
Path Summary:
| Slack | 0.937 |
| Data Arrival Time | 1.132 |
| Data Required Time | 0.195 |
| From | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_7_s1 |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 296 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q |
| 1.132 | 0.746 | tNET | RR | 1 | R20C30[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_7_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R20C30[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_7_s1/CLK |
| 0.195 | 0.011 | tHld | 1 | R20C30[1][B] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_7_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.746, 78.688%; tC2Q: 0.202, 21.312% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Path25
Path Summary:
| Slack | 0.937 |
| Data Arrival Time | 1.132 |
| Data Required Time | 0.195 |
| From | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0 |
| To | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_8_s1 |
| Launch Clk | sdrc_clk:[R] |
| Latch Clk | sdrc_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/CLK |
| 0.386 | 0.202 | tC2Q | RR | 296 | R18C19[2][A] | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/sdrc_init_done_done_s0/Q |
| 1.132 | 0.746 | tNET | RR | 1 | R20C29[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_8_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | sdrc_clk | ||||
| 0.000 | 0.000 | tCL | RR | 616 | PLL_L[1] | gw_rpll_inst/rpll_inst/CLKOUTP |
| 0.184 | 0.184 | tNET | RR | 1 | R20C29[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_8_s1/CLK |
| 0.195 | 0.011 | tHld | 1 | R20C29[1][A] | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_addr_8_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.746, 78.688%; tC2Q: 0.202, 21.312% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.184, 100.000% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
| Slack: | 3.089 |
| Actual Width: | 4.089 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | sdrc_clk |
| Objects: | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d0_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 4.167 | 0.000 | active clock edge time | ||
| 4.167 | 0.000 | sdrc_clk | ||
| 4.167 | 0.000 | tCL | FF | gw_rpll_inst/rpll_inst/CLKOUTP |
| 4.428 | 0.261 | tNET | FF | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d0_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 8.333 | 0.000 | active clock edge time | ||
| 8.333 | 0.000 | sdrc_clk | ||
| 8.333 | 0.000 | tCL | RR | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.517 | 0.184 | tNET | RR | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d0_s0/CLK |
MPW2
MPW Summary:
| Slack: | 3.089 |
| Actual Width: | 4.089 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | sdrc_clk |
| Objects: | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d1_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 4.167 | 0.000 | active clock edge time | ||
| 4.167 | 0.000 | sdrc_clk | ||
| 4.167 | 0.000 | tCL | FF | gw_rpll_inst/rpll_inst/CLKOUTP |
| 4.428 | 0.261 | tNET | FF | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d1_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 8.333 | 0.000 | active clock edge time | ||
| 8.333 | 0.000 | sdrc_clk | ||
| 8.333 | 0.000 | tCL | RR | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.517 | 0.184 | tNET | RR | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d1_s0/CLK |
MPW3
MPW Summary:
| Slack: | 3.089 |
| Actual Width: | 4.089 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | sdrc_clk |
| Objects: | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_end_o_s1 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 4.167 | 0.000 | active clock edge time | ||
| 4.167 | 0.000 | sdrc_clk | ||
| 4.167 | 0.000 | tCL | FF | gw_rpll_inst/rpll_inst/CLKOUTP |
| 4.428 | 0.261 | tNET | FF | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_end_o_s1/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 8.333 | 0.000 | active clock edge time | ||
| 8.333 | 0.000 | sdrc_clk | ||
| 8.333 | 0.000 | tCL | RR | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.517 | 0.184 | tNET | RR | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_end_o_s1/CLK |
MPW4
MPW Summary:
| Slack: | 3.089 |
| Actual Width: | 4.089 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | sdrc_clk |
| Objects: | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_6_s1 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 4.167 | 0.000 | active clock edge time | ||
| 4.167 | 0.000 | sdrc_clk | ||
| 4.167 | 0.000 | tCL | FF | gw_rpll_inst/rpll_inst/CLKOUTP |
| 4.428 | 0.261 | tNET | FF | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_6_s1/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 8.333 | 0.000 | active clock edge time | ||
| 8.333 | 0.000 | sdrc_clk | ||
| 8.333 | 0.000 | tCL | RR | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.517 | 0.184 | tNET | RR | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_6_s1/CLK |
MPW5
MPW Summary:
| Slack: | 3.089 |
| Actual Width: | 4.089 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | sdrc_clk |
| Objects: | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_5_s1 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 4.167 | 0.000 | active clock edge time | ||
| 4.167 | 0.000 | sdrc_clk | ||
| 4.167 | 0.000 | tCL | FF | gw_rpll_inst/rpll_inst/CLKOUTP |
| 4.428 | 0.261 | tNET | FF | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_5_s1/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 8.333 | 0.000 | active clock edge time | ||
| 8.333 | 0.000 | sdrc_clk | ||
| 8.333 | 0.000 | tCL | RR | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.517 | 0.184 | tNET | RR | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_5_s1/CLK |
MPW6
MPW Summary:
| Slack: | 3.089 |
| Actual Width: | 4.089 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | sdrc_clk |
| Objects: | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_4_s1 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 4.167 | 0.000 | active clock edge time | ||
| 4.167 | 0.000 | sdrc_clk | ||
| 4.167 | 0.000 | tCL | FF | gw_rpll_inst/rpll_inst/CLKOUTP |
| 4.428 | 0.261 | tNET | FF | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_4_s1/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 8.333 | 0.000 | active clock edge time | ||
| 8.333 | 0.000 | sdrc_clk | ||
| 8.333 | 0.000 | tCL | RR | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.517 | 0.184 | tNET | RR | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_4_s1/CLK |
MPW7
MPW Summary:
| Slack: | 3.089 |
| Actual Width: | 4.089 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | sdrc_clk |
| Objects: | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_20_s1 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 4.167 | 0.000 | active clock edge time | ||
| 4.167 | 0.000 | sdrc_clk | ||
| 4.167 | 0.000 | tCL | FF | gw_rpll_inst/rpll_inst/CLKOUTP |
| 4.428 | 0.261 | tNET | FF | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_20_s1/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 8.333 | 0.000 | active clock edge time | ||
| 8.333 | 0.000 | sdrc_clk | ||
| 8.333 | 0.000 | tCL | RR | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.517 | 0.184 | tNET | RR | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_20_s1/CLK |
MPW8
MPW Summary:
| Slack: | 3.089 |
| Actual Width: | 4.089 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | sdrc_clk |
| Objects: | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_18_s1 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 4.167 | 0.000 | active clock edge time | ||
| 4.167 | 0.000 | sdrc_clk | ||
| 4.167 | 0.000 | tCL | FF | gw_rpll_inst/rpll_inst/CLKOUTP |
| 4.428 | 0.261 | tNET | FF | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_18_s1/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 8.333 | 0.000 | active clock edge time | ||
| 8.333 | 0.000 | sdrc_clk | ||
| 8.333 | 0.000 | tCL | RR | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.517 | 0.184 | tNET | RR | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_18_s1/CLK |
MPW9
MPW Summary:
| Slack: | 3.089 |
| Actual Width: | 4.089 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | sdrc_clk |
| Objects: | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_17_s1 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 4.167 | 0.000 | active clock edge time | ||
| 4.167 | 0.000 | sdrc_clk | ||
| 4.167 | 0.000 | tCL | FF | gw_rpll_inst/rpll_inst/CLKOUTP |
| 4.428 | 0.261 | tNET | FF | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_17_s1/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 8.333 | 0.000 | active clock edge time | ||
| 8.333 | 0.000 | sdrc_clk | ||
| 8.333 | 0.000 | tCL | RR | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.517 | 0.184 | tNET | RR | Video_Frame_Buffer_Top_inst/vfb_sdram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_addr_17_s1/CLK |
MPW10
MPW Summary:
| Slack: | 3.089 |
| Actual Width: | 4.089 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | sdrc_clk |
| Objects: | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/Sdrc_addr_i_9_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 4.167 | 0.000 | active clock edge time | ||
| 4.167 | 0.000 | sdrc_clk | ||
| 4.167 | 0.000 | tCL | FF | gw_rpll_inst/rpll_inst/CLKOUTP |
| 4.428 | 0.261 | tNET | FF | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/Sdrc_addr_i_9_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 8.333 | 0.000 | active clock edge time | ||
| 8.333 | 0.000 | sdrc_clk | ||
| 8.333 | 0.000 | tCL | RR | gw_rpll_inst/rpll_inst/CLKOUTP |
| 8.517 | 0.184 | tNET | RR | SDRAM_controller_top_SIP_inst/sdrc_top_inst/U1/Sdrc_addr_i_9_s0/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
| FANOUT | NET NAME | WORST SLACK | MAX DELAY |
|---|---|---|---|
| 616 | sdrc_clk | 0.379 | 0.261 |
| 339 | I_clk_d | 9.561 | 1.455 |
| 296 | O_led_d_0[0] | 0.710 | 1.594 |
| 162 | O_clk_d | 7.021 | 0.427 |
| 75 | reset_r[1] | 1.908 | 1.570 |
| 64 | Ctrl_wr_data_valid | 6.838 | 1.356 |
| 63 | reset_r[1] | 5.229 | 1.792 |
| 57 | User_model_state.STATE_IDLE | 5.327 | 0.951 |
| 56 | next_state.ST_IFF0_WRITE_DDR | 0.706 | 1.008 |
| 51 | allian_cnt[0] | 17.460 | 1.348 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
| GRID LOC | ROUTE CONGESTIONS |
|---|---|
| R24C21 | 83.33% |
| R34C23 | 83.33% |
| R34C24 | 83.33% |
| R26C23 | 83.33% |
| R24C22 | 81.94% |
| R35C24 | 80.56% |
| R33C34 | 80.56% |
| R21C30 | 79.17% |
| R22C18 | 79.17% |
| R24C18 | 79.17% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
| SDC Command Type | State | Detail Command |
|---|---|---|
| TC_CLOCK | Actived | create_clock -name O_clk -period 15.385 -waveform {0 7.692} [get_ports {O_clk}] -add |
| TC_CLOCK | Actived | create_clock -name I_clk -period 20 -waveform {0 10} [get_ports {I_clk}] -add |
| TC_CLOCK | Actived | create_clock -name O_sdram_clk -period 8.333 -waveform {0 4.167} [get_ports {O_sdram_clk}] -add |
| TC_CLOCK | Actived | create_clock -name sdrc_clk -period 8.333 -waveform {0 4.167} [get_nets {sdrc_clk}] -add |
| TC_FALSE_PATH | Actived | set_false_path -from [get_clocks {sdrc_clk}] -to [get_clocks {I_clk}] |
| TC_FALSE_PATH | Actived | set_false_path -from [get_clocks {sdrc_clk}] -to [get_clocks {O_clk}] |
| TC_FALSE_PATH | Actived | set_false_path -from [get_clocks {I_clk}] -to [get_clocks {sdrc_clk}] |
| TC_FALSE_PATH | Actived | set_false_path -from [get_clocks {O_clk}] -to [get_clocks {sdrc_clk}] |