Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\DVI_TX\data\dvi_tx_top.v C:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\DVI_TX\data\rgb2dvi.vp |
| GowinSynthesis Constraints File | --- |
| Version | GowinSynthesis V1.9.8.01 |
| Part Number | GW1NSR-LV4CQN48PC7/I6 |
| Device | GW1NSR-4C |
| Created Time | Mon Oct 11 17:40:29 2021 |
| Legal Announcement | Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | DVI_TX_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.204s, Peak memory usage = 42.422MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 42.422MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 42.422MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 42.422MB Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 42.422MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 42.422MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 42.422MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 42.422MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 42.422MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 42.422MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 42.422MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 42.422MB Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 55.676MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.067s, Peak memory usage = 55.676MB Generate output files: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 55.676MB |
| Total Time and Memory Usage | CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 55.676MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 38 |
| I/O Buf | 34 |
| IBUF | 30 |
| TLVDS_OBUF | 4 |
| Register | 73 |
| DFFP | 3 |
| DFFC | 70 |
| LUT | 213 |
| LUT2 | 29 |
| LUT3 | 50 |
| LUT4 | 134 |
| ALU | 68 |
| ALU | 68 |
| INV | 4 |
| INV | 4 |
| IOLOGIC | 4 |
| OSER10 | 4 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 285(217 LUTs, 68 ALUs) / 4608 | 6% |
| Register | 73 / 3570 | 2% |
| --Register as Latch | 0 / 3570 | 0% |
| --Register as FF | 73 / 3570 | 2% |
| BSRAM | 0 / 10 | 0% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| I_rgb_clk | Base | 20.000 | 50.0 | 0.000 | 10.000 | I_rgb_clk_ibuf/I | ||
| I_serial_clk | Base | 20.000 | 50.0 | 0.000 | 10.000 | I_serial_clk_ibuf/I |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | I_rgb_clk | 50.0(MHz) | 83.2(MHz) | 12 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 7.986 |
| Data Arrival Time | 12.714 |
| Data Required Time | 20.700 |
| From | rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0 |
| To | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0 |
| Launch Clk | I_rgb_clk[R] |
| Latch Clk | I_rgb_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_rgb_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_rgb_clk_ibuf/I |
| 0.728 | 0.728 | tINS | RR | 77 | I_rgb_clk_ibuf/O |
| 0.997 | 0.269 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0/CLK |
| 1.336 | 0.340 | tC2Q | RF | 5 | rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0/Q |
| 1.692 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n658_s3/I1 |
| 2.506 | 0.814 | tINS | FF | 2 | rgb2dvi_inst/TMDS8b10b_inst_r/n658_s3/F |
| 2.862 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n658_s4/I3 |
| 3.326 | 0.464 | tINS | FF | 5 | rgb2dvi_inst/TMDS8b10b_inst_r/n658_s4/F |
| 3.681 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s15/I0 |
| 4.446 | 0.765 | tINS | FF | 4 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s15/F |
| 4.802 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n605_s2/I0 |
| 5.567 | 0.765 | tINS | FF | 5 | rgb2dvi_inst/TMDS8b10b_inst_r/n605_s2/F |
| 5.922 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_3_s11/I1 |
| 6.737 | 0.814 | tINS | FF | 5 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_3_s11/F |
| 7.092 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15/I2 |
| 7.701 | 0.609 | tINS | FF | 4 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15/F |
| 8.057 | 0.356 | tNET | FF | 2 | rgb2dvi_inst/TMDS8b10b_inst_r/n237_s5/I1 |
| 8.831 | 0.774 | tINS | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n237_s5/COUT |
| 8.831 | 0.000 | tNET | FF | 2 | rgb2dvi_inst/TMDS8b10b_inst_r/n236_s4/CIN |
| 9.249 | 0.417 | tINS | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n236_s4/SUM |
| 9.604 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n578_s6/I3 |
| 10.068 | 0.464 | tINS | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n578_s6/F |
| 10.424 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n578_s3/I0 |
| 11.189 | 0.765 | tINS | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n578_s3/F |
| 11.544 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n578_s1/I1 |
| 12.359 | 0.814 | tINS | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n578_s1/F |
| 12.714 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | I_rgb_clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | I_rgb_clk_ibuf/I |
| 20.728 | 0.728 | tINS | RR | 77 | I_rgb_clk_ibuf/O |
| 20.997 | 0.269 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0/CLK |
| 20.700 | -0.296 | tSu | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 12 |
| Arrival Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
| Arrival Data Path Delay: | cell: 7.466, 63.712%; route: 3.912, 33.390%; tC2Q: 0.340, 2.898% |
| Required Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Path 2
Path Summary:| Slack | 9.426 |
| Data Arrival Time | 11.274 |
| Data Required Time | 20.700 |
| From | rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0 |
| To | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0 |
| Launch Clk | I_rgb_clk[R] |
| Latch Clk | I_rgb_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_rgb_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_rgb_clk_ibuf/I |
| 0.728 | 0.728 | tINS | RR | 77 | I_rgb_clk_ibuf/O |
| 0.997 | 0.269 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0/CLK |
| 1.336 | 0.340 | tC2Q | RF | 5 | rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0/Q |
| 1.692 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n658_s3/I1 |
| 2.506 | 0.814 | tINS | FF | 2 | rgb2dvi_inst/TMDS8b10b_inst_r/n658_s3/F |
| 2.862 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n658_s4/I3 |
| 3.326 | 0.464 | tINS | FF | 5 | rgb2dvi_inst/TMDS8b10b_inst_r/n658_s4/F |
| 3.681 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s15/I0 |
| 4.446 | 0.765 | tINS | FF | 4 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s15/F |
| 4.802 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n605_s2/I0 |
| 5.567 | 0.765 | tINS | FF | 5 | rgb2dvi_inst/TMDS8b10b_inst_r/n605_s2/F |
| 5.922 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_3_s11/I1 |
| 6.737 | 0.814 | tINS | FF | 5 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_3_s11/F |
| 7.092 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15/I2 |
| 7.701 | 0.609 | tINS | FF | 4 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15/F |
| 8.057 | 0.356 | tNET | FF | 2 | rgb2dvi_inst/TMDS8b10b_inst_r/n365_s3/I1 |
| 8.578 | 0.521 | tINS | FF | 2 | rgb2dvi_inst/TMDS8b10b_inst_r/n365_s3/SUM |
| 8.934 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n579_s3/I1 |
| 9.748 | 0.814 | tINS | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n579_s3/F |
| 10.104 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n579_s1/I1 |
| 10.918 | 0.814 | tINS | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n579_s1/F |
| 11.274 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | I_rgb_clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | I_rgb_clk_ibuf/I |
| 20.728 | 0.728 | tINS | RR | 77 | I_rgb_clk_ibuf/O |
| 20.997 | 0.269 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0/CLK |
| 20.700 | -0.296 | tSu | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 10 |
| Arrival Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
| Arrival Data Path Delay: | cell: 6.381, 62.086%; route: 3.557, 34.609%; tC2Q: 0.340, 3.305% |
| Required Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Path 3
Path Summary:| Slack | 9.681 |
| Data Arrival Time | 11.019 |
| Data Required Time | 20.700 |
| From | rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0 |
| To | rgb2dvi_inst/TMDS8b10b_inst_r/dout_0_s0 |
| Launch Clk | I_rgb_clk[R] |
| Latch Clk | I_rgb_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_rgb_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_rgb_clk_ibuf/I |
| 0.728 | 0.728 | tINS | RR | 77 | I_rgb_clk_ibuf/O |
| 0.997 | 0.269 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0/CLK |
| 1.336 | 0.340 | tC2Q | RF | 5 | rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0/Q |
| 1.692 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n658_s3/I1 |
| 2.506 | 0.814 | tINS | FF | 2 | rgb2dvi_inst/TMDS8b10b_inst_r/n658_s3/F |
| 2.862 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n658_s4/I3 |
| 3.326 | 0.464 | tINS | FF | 5 | rgb2dvi_inst/TMDS8b10b_inst_r/n658_s4/F |
| 3.681 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s15/I0 |
| 4.446 | 0.765 | tINS | FF | 4 | rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s15/F |
| 4.802 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n605_s1/I1 |
| 5.616 | 0.814 | tINS | FF | 2 | rgb2dvi_inst/TMDS8b10b_inst_r/n605_s1/F |
| 5.972 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n628_s1/I1 |
| 6.786 | 0.814 | tINS | FF | 6 | rgb2dvi_inst/TMDS8b10b_inst_r/n628_s1/F |
| 7.142 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n628_s3/I0 |
| 7.907 | 0.765 | tINS | FF | 2 | rgb2dvi_inst/TMDS8b10b_inst_r/n628_s3/F |
| 8.262 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n654_s1/I1 |
| 9.077 | 0.814 | tINS | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n654_s1/F |
| 9.432 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n654_s0/I0 |
| 9.543 | 0.110 | tINS | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n654_s0/O |
| 9.898 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n664_s0/I0 |
| 10.663 | 0.765 | tINS | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/n664_s0/F |
| 11.019 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/dout_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | I_rgb_clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | I_rgb_clk_ibuf/I |
| 20.728 | 0.728 | tINS | RR | 77 | I_rgb_clk_ibuf/O |
| 20.997 | 0.269 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/dout_0_s0/CLK |
| 20.700 | -0.296 | tSu | 1 | rgb2dvi_inst/TMDS8b10b_inst_r/dout_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
| Arrival Data Path Delay: | cell: 6.126, 61.122%; route: 3.557, 35.489%; tC2Q: 0.340, 3.389% |
| Required Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Path 4
Path Summary:| Slack | 9.770 |
| Data Arrival Time | 10.930 |
| Data Required Time | 20.700 |
| From | rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0 |
| To | rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0 |
| Launch Clk | I_rgb_clk[R] |
| Latch Clk | I_rgb_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_rgb_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_rgb_clk_ibuf/I |
| 0.728 | 0.728 | tINS | RR | 77 | I_rgb_clk_ibuf/O |
| 0.997 | 0.269 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0/CLK |
| 1.336 | 0.340 | tC2Q | RF | 17 | rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0/Q |
| 1.692 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s21/I1 |
| 2.506 | 0.814 | tINS | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s21/F |
| 2.862 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s18/I0 |
| 3.627 | 0.765 | tINS | FF | 2 | rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s18/F |
| 3.982 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/I1 |
| 4.797 | 0.814 | tINS | FF | 3 | rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/F |
| 5.152 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s15/I0 |
| 5.917 | 0.765 | tINS | FF | 4 | rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_2_s15/F |
| 6.273 | 0.356 | tNET | FF | 2 | rgb2dvi_inst/TMDS8b10b_inst_b/n237_s5/I1 |
| 7.047 | 0.774 | tINS | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/n237_s5/COUT |
| 7.047 | 0.000 | tNET | FF | 2 | rgb2dvi_inst/TMDS8b10b_inst_b/n236_s4/CIN |
| 7.464 | 0.417 | tINS | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/n236_s4/SUM |
| 7.820 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/n578_s5/I3 |
| 8.284 | 0.464 | tINS | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/n578_s5/F |
| 8.639 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/n578_s3/I0 |
| 9.404 | 0.765 | tINS | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/n578_s3/F |
| 9.760 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/n578_s1/I1 |
| 10.574 | 0.814 | tINS | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/n578_s1/F |
| 10.930 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | I_rgb_clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | I_rgb_clk_ibuf/I |
| 20.728 | 0.728 | tINS | RR | 77 | I_rgb_clk_ibuf/O |
| 20.997 | 0.269 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0/CLK |
| 20.700 | -0.296 | tSu | 1 | rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 10 |
| Arrival Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
| Arrival Data Path Delay: | cell: 6.393, 64.355%; route: 3.201, 32.226%; tC2Q: 0.340, 3.419% |
| Required Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
Path 5
Path Summary:| Slack | 9.876 |
| Data Arrival Time | 10.824 |
| Data Required Time | 20.700 |
| From | rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0 |
| To | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0 |
| Launch Clk | I_rgb_clk[R] |
| Latch Clk | I_rgb_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_rgb_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_rgb_clk_ibuf/I |
| 0.728 | 0.728 | tINS | RR | 77 | I_rgb_clk_ibuf/O |
| 0.997 | 0.269 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0/CLK |
| 1.336 | 0.340 | tC2Q | RF | 7 | rgb2dvi_inst/TMDS8b10b_inst_g/din_d_3_s0/Q |
| 1.692 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n658_s3/I1 |
| 2.506 | 0.814 | tINS | FF | 2 | rgb2dvi_inst/TMDS8b10b_inst_g/n658_s3/F |
| 2.862 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_2_s21/I1 |
| 3.676 | 0.814 | tINS | FF | 4 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_2_s21/F |
| 4.032 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s18/I1 |
| 4.846 | 0.814 | tINS | FF | 2 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s18/F |
| 5.202 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s19/I3 |
| 5.666 | 0.464 | tINS | FF | 4 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s19/F |
| 6.022 | 0.356 | tNET | FF | 2 | rgb2dvi_inst/TMDS8b10b_inst_g/n238_s5/I1 |
| 6.796 | 0.774 | tINS | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n238_s5/COUT |
| 6.796 | 0.000 | tNET | FF | 2 | rgb2dvi_inst/TMDS8b10b_inst_g/n237_s5/CIN |
| 7.213 | 0.417 | tINS | FF | 2 | rgb2dvi_inst/TMDS8b10b_inst_g/n237_s5/SUM |
| 7.569 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n578_s5/I2 |
| 8.178 | 0.609 | tINS | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n578_s5/F |
| 8.534 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n578_s3/I0 |
| 9.298 | 0.765 | tINS | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n578_s3/F |
| 9.654 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n578_s1/I1 |
| 10.468 | 0.814 | tINS | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/n578_s1/F |
| 10.824 | 0.356 | tNET | FF | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | I_rgb_clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | I_rgb_clk_ibuf/I |
| 20.728 | 0.728 | tINS | RR | 77 | I_rgb_clk_ibuf/O |
| 20.997 | 0.269 | tNET | RR | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0/CLK |
| 20.700 | -0.296 | tSu | 1 | rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 10 |
| Arrival Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |
| Arrival Data Path Delay: | cell: 6.287, 63.971%; route: 3.201, 32.573%; tC2Q: 0.340, 3.456% |
| Required Clock Path Delay: | cell: 0.728, 73.009%; route: 0.269, 26.991% |