Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_Scaler_RefDesign\Gowin_Scaler_Live_RefDesign\project\src\adv7513_iic_init.v E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_Scaler_RefDesign\Gowin_Scaler_Live_RefDesign\project\src\ddr3_memory_interface\ddr3_memory_interface.v E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_Scaler_RefDesign\Gowin_Scaler_Live_RefDesign\project\src\gowin_rpll\ddr3_rpll.v E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_Scaler_RefDesign\Gowin_Scaler_Live_RefDesign\project\src\gowin_rpll\pix_rpll.v E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_Scaler_RefDesign\Gowin_Scaler_Live_RefDesign\project\src\i2c_master\i2c_master.v E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_Scaler_RefDesign\Gowin_Scaler_Live_RefDesign\project\src\key_debounceN.v E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_Scaler_RefDesign\Gowin_Scaler_Live_RefDesign\project\src\line_buffer\fifo_top\fifo_read.v E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_Scaler_RefDesign\Gowin_Scaler_Live_RefDesign\project\src\line_buffer\vlb_top.v E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_Scaler_RefDesign\Gowin_Scaler_Live_RefDesign\project\src\scaler\scaler.v E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_Scaler_RefDesign\Gowin_Scaler_Live_RefDesign\project\src\scaler_test_top.v E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_Scaler_RefDesign\Gowin_Scaler_Live_RefDesign\project\src\syn_code\syn_gen.v E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_Scaler_RefDesign\Gowin_Scaler_Live_RefDesign\project\src\testpattern.v E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_Scaler_RefDesign\Gowin_Scaler_Live_RefDesign\project\src\video_frame_buffer\video_frame_buffer.v |
| GowinSynthesis Constraints File | --- |
| Version | V1.9.9 Beta-6 |
| Part Number | GW2A-LV18PG484C8/I7 |
| Device | GW2A-18 |
| Device Version | C |
| Created Time | Mon Oct 30 16:12:10 2023 |
| Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | scaler_test_top |
| Synthesis Process | Running parser: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 181.715MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.279s, Peak memory usage = 181.715MB Optimizing Phase 1: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.2s, Peak memory usage = 181.715MB Optimizing Phase 2: CPU time = 0h 0m 0.437s, Elapsed time = 0h 0m 0.441s, Peak memory usage = 181.715MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.135s, Peak memory usage = 181.715MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 181.715MB Inferring Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.052s, Peak memory usage = 181.715MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 181.715MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.338s, Peak memory usage = 181.715MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.13s, Peak memory usage = 181.715MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.091s, Peak memory usage = 181.715MB Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 181.793MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.437s, Elapsed time = 0h 0m 0.465s, Peak memory usage = 181.793MB Generate output files: CPU time = 0h 0m 0.671s, Elapsed time = 0h 0m 0.679s, Peak memory usage = 202.969MB |
| Total Time and Memory Usage | CPU time = 0h 0m 7s, Elapsed time = 0h 0m 7s, Peak memory usage = 202.969MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 83 |
| I/O Buf | 80 |
| IBUF | 2 |
| OBUF | 55 |
| TBUF | 2 |
| IOBUF | 18 |
| ELVDS_OBUF | 1 |
| ELVDS_IOBUF | 2 |
| Register | 4894 |
| DFF | 128 |
| DFFE | 5 |
| DFFS | 9 |
| DFFR | 38 |
| DFFP | 112 |
| DFFPE | 13 |
| DFFC | 3018 |
| DFFCE | 1567 |
| DFFNP | 4 |
| LUT | 4691 |
| LUT2 | 979 |
| LUT3 | 1672 |
| LUT4 | 2040 |
| ALU | 622 |
| ALU | 622 |
| SSRAM | 122 |
| RAM16S4 | 52 |
| RAM16SDP1 | 2 |
| RAM16SDP4 | 68 |
| INV | 73 |
| INV | 73 |
| IOLOGIC | 75 |
| IDES8_MEM | 16 |
| OSER8 | 23 |
| OSER8_MEM | 20 |
| IODELAY | 16 |
| DSP | |
| MULT18X18 | 12 |
| BSRAM | 31 |
| SDPB | 24 |
| SDPX9B | 7 |
| CLOCK | 6 |
| CLKDIV | 1 |
| DQS | 2 |
| DHCEN | 1 |
| rPLL | 2 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 6118(4764 LUT, 622 ALU, 122 RAM16) / 20736 | 30% |
| Register | 4894 / 16509 | 30% |
| --Register as Latch | 0 / 16509 | 0% |
| --Register as FF | 4894 / 16509 | 30% |
| BSRAM | 31 / 46 | 68% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| I_clk | Base | 20.000 | 50.0 | 0.000 | 10.000 | I_clk_ibuf/I | ||
| Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n32_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n32_s2/O | ||
| Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n37_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n37_s2/O | ||
| Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n38_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n38_s2/O | ||
| DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/n1851_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/u_ddr_init/n1851_s2/O | ||
| pix_rpll_inst/rpll_inst/CLKOUT.default_gen_clk | Generated | 9.286 | 107.7 | 0.000 | 4.643 | I_clk_ibuf/I | I_clk | pix_rpll_inst/rpll_inst/CLKOUT |
| pix_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk | Generated | 9.286 | 107.7 | 0.000 | 4.643 | I_clk_ibuf/I | I_clk | pix_rpll_inst/rpll_inst/CLKOUTP |
| pix_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk | Generated | 18.571 | 53.8 | 0.000 | 9.286 | I_clk_ibuf/I | I_clk | pix_rpll_inst/rpll_inst/CLKOUTD |
| pix_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 27.857 | 35.9 | 0.000 | 13.929 | I_clk_ibuf/I | I_clk | pix_rpll_inst/rpll_inst/CLKOUTD3 |
| ddr3_rpll_inst/rpll_inst/CLKOUT.default_gen_clk | Generated | 3.333 | 300.0 | 0.000 | 1.667 | I_clk_ibuf/I | I_clk | ddr3_rpll_inst/rpll_inst/CLKOUT |
| ddr3_rpll_inst/rpll_inst/CLKOUTP.default_gen_clk | Generated | 3.333 | 300.0 | 0.000 | 1.667 | I_clk_ibuf/I | I_clk | ddr3_rpll_inst/rpll_inst/CLKOUTP |
| ddr3_rpll_inst/rpll_inst/CLKOUTD.default_gen_clk | Generated | 6.667 | 150.0 | 0.000 | 3.333 | I_clk_ibuf/I | I_clk | ddr3_rpll_inst/rpll_inst/CLKOUTD |
| ddr3_rpll_inst/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 10.000 | 100.0 | 0.000 | 5.000 | I_clk_ibuf/I | I_clk | ddr3_rpll_inst/rpll_inst/CLKOUTD3 |
| DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | Generated | 13.333 | 75.0 | 0.000 | 6.667 | ddr3_rpll_inst/rpll_inst/CLKOUT | ddr3_rpll_inst/rpll_inst/CLKOUT.default_gen_clk | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | I_clk | 50.0(MHz) | 191.4(MHz) | 8 | TOP |
| 2 | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n32_6 | 100.0(MHz) | 1984.1(MHz) | 1 | TOP |
| 3 | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n37_6 | 100.0(MHz) | 1984.1(MHz) | 1 | TOP |
| 4 | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n38_6 | 100.0(MHz) | 1984.1(MHz) | 1 | TOP |
| 5 | pix_rpll_inst/rpll_inst/CLKOUT.default_gen_clk | 107.7(MHz) | 190.2(MHz) | 9 | TOP |
| 6 | ddr3_rpll_inst/rpll_inst/CLKOUT.default_gen_clk | 300.0(MHz) | 1364.3(MHz) | 1 | TOP |
| 7 | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | 75.0(MHz) | 154.5(MHz) | 8 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -1.160 |
| Data Arrival Time | 308.107 |
| Data Required Time | 306.947 |
| From | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_0_s1 |
| To | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_0_s1 |
| Launch Clk | pix_rpll_inst/rpll_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 306.429 | 0.000 | pix_rpll_inst/rpll_inst/CLKOUT.default_gen_clk | |||
| 307.458 | 1.029 | tCL | RR | 164 | pix_rpll_inst/rpll_inst/CLKOUT |
| 307.638 | 0.180 | tNET | RR | 1 | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_0_s1/CLK |
| 307.870 | 0.232 | tC2Q | RF | 1 | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_0_s1/Q |
| 308.107 | 0.237 | tNET | FF | 1 | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_0_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 306.667 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 306.837 | 0.170 | tCL | RR | 3188 | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 307.017 | 0.180 | tNET | RR | 1 | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_0_s1/CLK |
| 306.982 | -0.035 | tUnc | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_0_s1 | ||
| 306.947 | -0.035 | tSu | 1 | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_0_s1 |
| Clock Skew: | -0.859 |
| Setup Relationship: | 0.238 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.237, 50.533%; tC2Q: 0.232, 49.467% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path 2
Path Summary:| Slack | -1.160 |
| Data Arrival Time | 308.107 |
| Data Required Time | 306.947 |
| From | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_1_s1 |
| To | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_1_s1 |
| Launch Clk | pix_rpll_inst/rpll_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 306.429 | 0.000 | pix_rpll_inst/rpll_inst/CLKOUT.default_gen_clk | |||
| 307.458 | 1.029 | tCL | RR | 164 | pix_rpll_inst/rpll_inst/CLKOUT |
| 307.638 | 0.180 | tNET | RR | 1 | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_1_s1/CLK |
| 307.870 | 0.232 | tC2Q | RF | 1 | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_1_s1/Q |
| 308.107 | 0.237 | tNET | FF | 1 | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_1_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 306.667 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 306.837 | 0.170 | tCL | RR | 3188 | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 307.017 | 0.180 | tNET | RR | 1 | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_1_s1/CLK |
| 306.982 | -0.035 | tUnc | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_1_s1 | ||
| 306.947 | -0.035 | tSu | 1 | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_1_s1 |
| Clock Skew: | -0.859 |
| Setup Relationship: | 0.238 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.237, 50.533%; tC2Q: 0.232, 49.467% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path 3
Path Summary:| Slack | -1.160 |
| Data Arrival Time | 308.107 |
| Data Required Time | 306.947 |
| From | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_2_s1 |
| To | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_2_s1 |
| Launch Clk | pix_rpll_inst/rpll_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 306.429 | 0.000 | pix_rpll_inst/rpll_inst/CLKOUT.default_gen_clk | |||
| 307.458 | 1.029 | tCL | RR | 164 | pix_rpll_inst/rpll_inst/CLKOUT |
| 307.638 | 0.180 | tNET | RR | 1 | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_2_s1/CLK |
| 307.870 | 0.232 | tC2Q | RF | 1 | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_2_s1/Q |
| 308.107 | 0.237 | tNET | FF | 1 | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_2_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 306.667 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 306.837 | 0.170 | tCL | RR | 3188 | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 307.017 | 0.180 | tNET | RR | 1 | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_2_s1/CLK |
| 306.982 | -0.035 | tUnc | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_2_s1 | ||
| 306.947 | -0.035 | tSu | 1 | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_2_s1 |
| Clock Skew: | -0.859 |
| Setup Relationship: | 0.238 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.237, 50.533%; tC2Q: 0.232, 49.467% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path 4
Path Summary:| Slack | -1.160 |
| Data Arrival Time | 308.107 |
| Data Required Time | 306.947 |
| From | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_3_s1 |
| To | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_3_s1 |
| Launch Clk | pix_rpll_inst/rpll_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 306.429 | 0.000 | pix_rpll_inst/rpll_inst/CLKOUT.default_gen_clk | |||
| 307.458 | 1.029 | tCL | RR | 164 | pix_rpll_inst/rpll_inst/CLKOUT |
| 307.638 | 0.180 | tNET | RR | 1 | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_3_s1/CLK |
| 307.870 | 0.232 | tC2Q | RF | 1 | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_3_s1/Q |
| 308.107 | 0.237 | tNET | FF | 1 | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_3_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 306.667 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 306.837 | 0.170 | tCL | RR | 3188 | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 307.017 | 0.180 | tNET | RR | 1 | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_3_s1/CLK |
| 306.982 | -0.035 | tUnc | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_3_s1 | ||
| 306.947 | -0.035 | tSu | 1 | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_3_s1 |
| Clock Skew: | -0.859 |
| Setup Relationship: | 0.238 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.237, 50.533%; tC2Q: 0.232, 49.467% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path 5
Path Summary:| Slack | -1.160 |
| Data Arrival Time | 308.107 |
| Data Required Time | 306.947 |
| From | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_4_s1 |
| To | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_4_s1 |
| Launch Clk | pix_rpll_inst/rpll_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 306.429 | 0.000 | pix_rpll_inst/rpll_inst/CLKOUT.default_gen_clk | |||
| 307.458 | 1.029 | tCL | RR | 164 | pix_rpll_inst/rpll_inst/CLKOUT |
| 307.638 | 0.180 | tNET | RR | 1 | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_4_s1/CLK |
| 307.870 | 0.232 | tC2Q | RF | 1 | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_4_s1/Q |
| 308.107 | 0.237 | tNET | FF | 1 | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_4_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 306.667 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk | |||
| 306.837 | 0.170 | tCL | RR | 3188 | DDR3_Memory_Interface_Top_inst/gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT |
| 307.017 | 0.180 | tNET | RR | 1 | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_4_s1/CLK |
| 306.982 | -0.035 | tUnc | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_4_s1 | ||
| 306.947 | -0.035 | tSu | 1 | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_4_s1 |
| Clock Skew: | -0.859 |
| Setup Relationship: | 0.238 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.237, 50.533%; tC2Q: 0.232, 49.467% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |