Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.7.01Beta\IDE\ipcore\DVI_RX\data\dvi_rx_top.v
D:\Gowin\Gowin_V1.9.7.01Beta\IDE\ipcore\DVI_RX\data\dvi2rgb.vp
GowinSynthesis Constraints File ---
GowinSynthesis Verision GowinSynthesis V1.9.7.01Beta
Created Time Thu Oct 29 17:33:58 2020
Legal Announcement Copyright (C)2014-2020 Gowin Semiconductor Corporation. ALL rights reserved.

Design Settings

Top Level Module: DVI_RX_Top
Part Number: GW2A-LV18PG484C8/I7
Device: GW2A-18C

Resource

Resource Usage Summary

I/O Port 37
I/O Buf 33
    IBUF 1
    OBUF 28
    TLVDS_IBUF 4
Register 232
    DFFC 122
    DFFCE 110
LUT 500
    LUT2 35
    LUT3 190
    LUT4 275
INV 1
    INV 1
IOLOGIC 6
    IDES10 3
    IODELAY 3
CLOCK 2
    CLKDIV 1
    rPLL 1

Resource Utilization Summary

Logic 501(501 LUTs, 0 ALUs) / 20736 2%
Register 232 / 16512 1%
BSRAM 0 / 46 0%


Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
I_tmds_clk_p Base 25.000 40.0 0.000 12.500 dvi2rgb_inst/u_HDMI_CK/I
dvi2rgb_inst/rPLL_inst/CLKOUT.default_gen_clk Generated 5.000 200.0 0.000 2.500 dvi2rgb_inst/u_HDMI_CK/I I_tmds_clk_p dvi2rgb_inst/rPLL_inst/CLKOUT
dvi2rgb_inst/rPLL_inst/CLKOUTP.default_gen_clk Generated 5.000 200.0 1.563 4.063 dvi2rgb_inst/u_HDMI_CK/I I_tmds_clk_p dvi2rgb_inst/rPLL_inst/CLKOUTP
dvi2rgb_inst/rPLL_inst/CLKOUTD.default_gen_clk Generated 5.000 200.0 0.000 2.500 dvi2rgb_inst/u_HDMI_CK/I I_tmds_clk_p dvi2rgb_inst/rPLL_inst/CLKOUTD
dvi2rgb_inst/rPLL_inst/CLKOUTD3.default_gen_clk Generated 15.000 66.7 0.000 7.500 dvi2rgb_inst/u_HDMI_CK/I I_tmds_clk_p dvi2rgb_inst/rPLL_inst/CLKOUTD3
dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk Generated 25.000 40.0 1.563 14.063 dvi2rgb_inst/rPLL_inst/CLKOUTP dvi2rgb_inst/rPLL_inst/CLKOUTP.default_gen_clk dvi2rgb_inst/u_clkdiv5/CLKOUT

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk 40.0(MHz) 224.4(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 20.543
Data Arrival Time 6.300
Data Required Time 26.843
From dvi2rgb_inst/u_data_align/B_align_17_s0
To dvi2rgb_inst/u_data_align/tmds_r_d1_0_s1
Launch Clk dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk[R]
Latch Clk dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk[R]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
1.733 0.170 tCL RR 236 dvi2rgb_inst/u_clkdiv5/CLKOUT
1.913 0.18 tNET RR 1 dvi2rgb_inst/u_data_align/B_align_17_s0/CLK
2.145 0.232 tC2Q RF 7 dvi2rgb_inst/u_data_align/B_align_17_s0/Q
2.382 0.237 tNET FF 1 dvi2rgb_inst/u_data_align/align_cnt_3_s38/I1
2.937 0.555 tINS FF 2 dvi2rgb_inst/u_data_align/align_cnt_3_s38/F
3.174 0.237 tNET FF 1 dvi2rgb_inst/u_data_align/align_cnt_3_s20/I1
3.729 0.555 tINS FF 1 dvi2rgb_inst/u_data_align/align_cnt_3_s20/F
3.966 0.237 tNET FF 1 dvi2rgb_inst/u_data_align/align_cnt_3_s10/I1
4.521 0.555 tINS FF 2 dvi2rgb_inst/u_data_align/align_cnt_3_s10/F
4.758 0.237 tNET FF 1 dvi2rgb_inst/u_data_align/align_cnt_3_s5/I1
5.313 0.555 tINS FF 2 dvi2rgb_inst/u_data_align/align_cnt_3_s5/F
5.55 0.237 tNET FF 1 dvi2rgb_inst/u_data_align/tmds_b_d1_9_s4/I1
6.12 0.57 tINS FR 30 dvi2rgb_inst/u_data_align/tmds_b_d1_9_s4/F
6.3 0.18 tNET RR 1 dvi2rgb_inst/u_data_align/tmds_r_d1_0_s1/CE

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
1.733 0.170 tCL RR 236 dvi2rgb_inst/u_clkdiv5/CLKOUT
1.913 0.18 tNET RR 1 dvi2rgb_inst/u_data_align/tmds_r_d1_0_s1/CLK

Path Statistic:
Clock Skew: 0.000
Setup Relationship: 25.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%
Arrival Data Path Delay: cell: 2.790, 63.597%; route: 1.365, 31.115%; tC2Q: 0.232, 5.288%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.180, 100.000%

Path 2

Path Summary:
Slack 20.543
Data Arrival Time 6.300
Data Required Time 26.843
From dvi2rgb_inst/u_data_align/B_align_17_s0
To dvi2rgb_inst/u_data_align/tmds_r_d1_1_s1
Launch Clk dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk[R]
Latch Clk dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk[R]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
1.733 0.170 tCL RR 236 dvi2rgb_inst/u_clkdiv5/CLKOUT
1.913 0.18 tNET RR 1 dvi2rgb_inst/u_data_align/B_align_17_s0/CLK
2.145 0.232 tC2Q RF 7 dvi2rgb_inst/u_data_align/B_align_17_s0/Q
2.382 0.237 tNET FF 1 dvi2rgb_inst/u_data_align/align_cnt_3_s38/I1
2.937 0.555 tINS FF 2 dvi2rgb_inst/u_data_align/align_cnt_3_s38/F
3.174 0.237 tNET FF 1 dvi2rgb_inst/u_data_align/align_cnt_3_s20/I1
3.729 0.555 tINS FF 1 dvi2rgb_inst/u_data_align/align_cnt_3_s20/F
3.966 0.237 tNET FF 1 dvi2rgb_inst/u_data_align/align_cnt_3_s10/I1
4.521 0.555 tINS FF 2 dvi2rgb_inst/u_data_align/align_cnt_3_s10/F
4.758 0.237 tNET FF 1 dvi2rgb_inst/u_data_align/align_cnt_3_s5/I1
5.313 0.555 tINS FF 2 dvi2rgb_inst/u_data_align/align_cnt_3_s5/F
5.55 0.237 tNET FF 1 dvi2rgb_inst/u_data_align/tmds_b_d1_9_s4/I1
6.12 0.57 tINS FR 30 dvi2rgb_inst/u_data_align/tmds_b_d1_9_s4/F
6.3 0.18 tNET RR 1 dvi2rgb_inst/u_data_align/tmds_r_d1_1_s1/CE

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
1.733 0.170 tCL RR 236 dvi2rgb_inst/u_clkdiv5/CLKOUT
1.913 0.18 tNET RR 1 dvi2rgb_inst/u_data_align/tmds_r_d1_1_s1/CLK

Path Statistic:
Clock Skew: 0.000
Setup Relationship: 25.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 5.580, 65.324%; route: 2.730, 31.960%; tC2Q: 0.232, 2.716%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 3

Path Summary:
Slack 20.543
Data Arrival Time 6.300
Data Required Time 26.843
From dvi2rgb_inst/u_data_align/B_align_17_s0
To dvi2rgb_inst/u_data_align/tmds_r_d1_2_s1
Launch Clk dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk[R]
Latch Clk dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk[R]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
1.733 0.170 tCL RR 236 dvi2rgb_inst/u_clkdiv5/CLKOUT
1.913 0.18 tNET RR 1 dvi2rgb_inst/u_data_align/B_align_17_s0/CLK
2.145 0.232 tC2Q RF 7 dvi2rgb_inst/u_data_align/B_align_17_s0/Q
2.382 0.237 tNET FF 1 dvi2rgb_inst/u_data_align/align_cnt_3_s38/I1
2.937 0.555 tINS FF 2 dvi2rgb_inst/u_data_align/align_cnt_3_s38/F
3.174 0.237 tNET FF 1 dvi2rgb_inst/u_data_align/align_cnt_3_s20/I1
3.729 0.555 tINS FF 1 dvi2rgb_inst/u_data_align/align_cnt_3_s20/F
3.966 0.237 tNET FF 1 dvi2rgb_inst/u_data_align/align_cnt_3_s10/I1
4.521 0.555 tINS FF 2 dvi2rgb_inst/u_data_align/align_cnt_3_s10/F
4.758 0.237 tNET FF 1 dvi2rgb_inst/u_data_align/align_cnt_3_s5/I1
5.313 0.555 tINS FF 2 dvi2rgb_inst/u_data_align/align_cnt_3_s5/F
5.55 0.237 tNET FF 1 dvi2rgb_inst/u_data_align/tmds_b_d1_9_s4/I1
6.12 0.57 tINS FR 30 dvi2rgb_inst/u_data_align/tmds_b_d1_9_s4/F
6.3 0.18 tNET RR 1 dvi2rgb_inst/u_data_align/tmds_r_d1_2_s1/CE

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
1.733 0.170 tCL RR 236 dvi2rgb_inst/u_clkdiv5/CLKOUT
1.913 0.18 tNET RR 1 dvi2rgb_inst/u_data_align/tmds_r_d1_2_s1/CLK

Path Statistic:
Clock Skew: 0.000
Setup Relationship: 25.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.540, 100.000%
Arrival Data Path Delay: cell: 8.370, 65.921%; route: 4.095, 32.252%; tC2Q: 0.232, 1.827%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.540, 100.000%

Path 4

Path Summary:
Slack 20.543
Data Arrival Time 6.300
Data Required Time 26.843
From dvi2rgb_inst/u_data_align/B_align_17_s0
To dvi2rgb_inst/u_data_align/tmds_r_d1_3_s1
Launch Clk dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk[R]
Latch Clk dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk[R]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
1.733 0.170 tCL RR 236 dvi2rgb_inst/u_clkdiv5/CLKOUT
1.913 0.18 tNET RR 1 dvi2rgb_inst/u_data_align/B_align_17_s0/CLK
2.145 0.232 tC2Q RF 7 dvi2rgb_inst/u_data_align/B_align_17_s0/Q
2.382 0.237 tNET FF 1 dvi2rgb_inst/u_data_align/align_cnt_3_s38/I1
2.937 0.555 tINS FF 2 dvi2rgb_inst/u_data_align/align_cnt_3_s38/F
3.174 0.237 tNET FF 1 dvi2rgb_inst/u_data_align/align_cnt_3_s20/I1
3.729 0.555 tINS FF 1 dvi2rgb_inst/u_data_align/align_cnt_3_s20/F
3.966 0.237 tNET FF 1 dvi2rgb_inst/u_data_align/align_cnt_3_s10/I1
4.521 0.555 tINS FF 2 dvi2rgb_inst/u_data_align/align_cnt_3_s10/F
4.758 0.237 tNET FF 1 dvi2rgb_inst/u_data_align/align_cnt_3_s5/I1
5.313 0.555 tINS FF 2 dvi2rgb_inst/u_data_align/align_cnt_3_s5/F
5.55 0.237 tNET FF 1 dvi2rgb_inst/u_data_align/tmds_b_d1_9_s4/I1
6.12 0.57 tINS FR 30 dvi2rgb_inst/u_data_align/tmds_b_d1_9_s4/F
6.3 0.18 tNET RR 1 dvi2rgb_inst/u_data_align/tmds_r_d1_3_s1/CE

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
1.733 0.170 tCL RR 236 dvi2rgb_inst/u_clkdiv5/CLKOUT
1.913 0.18 tNET RR 1 dvi2rgb_inst/u_data_align/tmds_r_d1_3_s1/CLK

Path Statistic:
Clock Skew: 0.000
Setup Relationship: 25.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.720, 100.000%
Arrival Data Path Delay: cell: 11.160, 66.224%; route: 5.460, 32.400%; tC2Q: 0.232, 1.377%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.720, 100.000%

Path 5

Path Summary:
Slack 20.543
Data Arrival Time 6.300
Data Required Time 26.843
From dvi2rgb_inst/u_data_align/B_align_17_s0
To dvi2rgb_inst/u_data_align/tmds_r_d1_4_s1
Launch Clk dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk[R]
Latch Clk dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk[R]

Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
1.733 0.170 tCL RR 236 dvi2rgb_inst/u_clkdiv5/CLKOUT
1.913 0.18 tNET RR 1 dvi2rgb_inst/u_data_align/B_align_17_s0/CLK
2.145 0.232 tC2Q RF 7 dvi2rgb_inst/u_data_align/B_align_17_s0/Q
2.382 0.237 tNET FF 1 dvi2rgb_inst/u_data_align/align_cnt_3_s38/I1
2.937 0.555 tINS FF 2 dvi2rgb_inst/u_data_align/align_cnt_3_s38/F
3.174 0.237 tNET FF 1 dvi2rgb_inst/u_data_align/align_cnt_3_s20/I1
3.729 0.555 tINS FF 1 dvi2rgb_inst/u_data_align/align_cnt_3_s20/F
3.966 0.237 tNET FF 1 dvi2rgb_inst/u_data_align/align_cnt_3_s10/I1
4.521 0.555 tINS FF 2 dvi2rgb_inst/u_data_align/align_cnt_3_s10/F
4.758 0.237 tNET FF 1 dvi2rgb_inst/u_data_align/align_cnt_3_s5/I1
5.313 0.555 tINS FF 2 dvi2rgb_inst/u_data_align/align_cnt_3_s5/F
5.55 0.237 tNET FF 1 dvi2rgb_inst/u_data_align/tmds_b_d1_9_s4/I1
6.12 0.57 tINS FR 30 dvi2rgb_inst/u_data_align/tmds_b_d1_9_s4/F
6.3 0.18 tNET RR 1 dvi2rgb_inst/u_data_align/tmds_r_d1_4_s1/CE

Data Required Path:
AT DELAY TYPE RF FANOUT NODE
1.733 0.170 tCL RR 236 dvi2rgb_inst/u_clkdiv5/CLKOUT
1.913 0.18 tNET RR 1 dvi2rgb_inst/u_data_align/tmds_r_d1_4_s1/CLK

Path Statistic:
Clock Skew: 0.000
Setup Relationship: 25.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.900, 100.000%
Arrival Data Path Delay: cell: 13.950, 66.406%; route: 6.825, 32.489%; tC2Q: 0.232, 1.104%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.900, 100.000%

Synthesis completed successfully!
Process took 0h:0m:4s realtime, 0h:0m:4s cputime
Memory peak: 52.4MB