Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_DVI_TX_RefDesign\project\src\dvi_tx\dvi_tx.v E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_DVI_TX_RefDesign\project\src\gowin_rpll\TMDS_rPLL.v E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_DVI_TX_RefDesign\project\src\testpattern.v E:\myWork\IP\releaseVerify\RefDesign\1.9.9Beta-6\refDesign\Gowin_DVI_TX_RefDesign\project\src\video_top.v |
| GowinSynthesis Constraints File | --- |
| Version | V1.9.9 Beta-6 |
| Part Number | GW2A-LV18PG484C8/I7 |
| Device | GW2A-18 |
| Device Version | C |
| Created Time | Fri Oct 27 11:06:10 2023 |
| Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | video_top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.266s, Peak memory usage = 83.934MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 83.934MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 83.934MB Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 83.934MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 83.934MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 83.934MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 83.934MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 83.934MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.032s, Peak memory usage = 83.934MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 83.934MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 83.934MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 99.570MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.096s, Peak memory usage = 99.570MB Generate output files: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.06s, Peak memory usage = 99.570MB |
| Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 99.570MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 14 |
| I/O Buf | 10 |
| IBUF | 2 |
| OBUF | 4 |
| TLVDS_OBUF | 4 |
| Register | 280 |
| DFF | 1 |
| DFFP | 13 |
| DFFC | 176 |
| DFFCE | 90 |
| LUT | 568 |
| LUT2 | 98 |
| LUT3 | 122 |
| LUT4 | 348 |
| ALU | 78 |
| ALU | 78 |
| INV | 7 |
| INV | 7 |
| IOLOGIC | 4 |
| OSER10 | 4 |
| CLOCK | 2 |
| CLKDIV | 1 |
| rPLL | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 653(575 LUT, 78 ALU) / 20736 | 4% |
| Register | 280 / 16509 | 2% |
| --Register as Latch | 0 / 16509 | 0% |
| --Register as FF | 280 / 16509 | 2% |
| BSRAM | 0 / 46 | 0% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| I_clk | Base | 20.000 | 50.0 | 0.000 | 10.000 | I_clk_ibuf/I | ||
| u_tmds_rpll/rpll_inst/CLKOUT.default_gen_clk | Generated | 2.692 | 371.4 | 0.000 | 1.346 | I_clk_ibuf/I | I_clk | u_tmds_rpll/rpll_inst/CLKOUT |
| u_tmds_rpll/rpll_inst/CLKOUTP.default_gen_clk | Generated | 2.692 | 371.4 | 0.000 | 1.346 | I_clk_ibuf/I | I_clk | u_tmds_rpll/rpll_inst/CLKOUTP |
| u_tmds_rpll/rpll_inst/CLKOUTD.default_gen_clk | Generated | 5.385 | 185.7 | 0.000 | 2.692 | I_clk_ibuf/I | I_clk | u_tmds_rpll/rpll_inst/CLKOUTD |
| u_tmds_rpll/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 8.077 | 123.8 | 0.000 | 4.038 | I_clk_ibuf/I | I_clk | u_tmds_rpll/rpll_inst/CLKOUTD3 |
| u_clkdiv/CLKOUT.default_gen_clk | Generated | 13.462 | 74.3 | 0.000 | 6.731 | u_tmds_rpll/rpll_inst/CLKOUT | u_tmds_rpll/rpll_inst/CLKOUT.default_gen_clk | u_clkdiv/CLKOUT |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | I_clk | 50.0(MHz) | 275.2(MHz) | 5 | TOP |
| 2 | u_clkdiv/CLKOUT.default_gen_clk | 74.3(MHz) | 128.9(MHz) | 11 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 5.707 |
| Data Arrival Time | 8.071 |
| Data Required Time | 13.777 |
| From | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_1_s0 |
| To | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0 |
| Launch Clk | u_clkdiv/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_clkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | |||
| 0.170 | 0.170 | tCL | RR | 258 | u_clkdiv/CLKOUT |
| 0.350 | 0.180 | tNET | RR | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_1_s0/CLK |
| 0.582 | 0.232 | tC2Q | RF | 7 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_1_s0/Q |
| 0.819 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n688_s1/I1 |
| 1.375 | 0.555 | tINS | FF | 5 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n688_s1/F |
| 1.612 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s13/I1 |
| 2.167 | 0.555 | tINS | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s13/F |
| 2.404 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s12/I1 |
| 2.959 | 0.555 | tINS | FF | 4 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s12/F |
| 3.196 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n630_s1/I2 |
| 3.649 | 0.453 | tINS | FF | 3 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n630_s1/F |
| 3.886 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_2_s16/I0 |
| 4.403 | 0.517 | tINS | FF | 4 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_2_s16/F |
| 4.640 | 0.237 | tNET | FF | 2 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n237_s5/I1 |
| 5.210 | 0.570 | tINS | FR | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n237_s5/COUT |
| 5.210 | 0.000 | tNET | RR | 2 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n236_s4/CIN |
| 5.680 | 0.470 | tINS | RF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n236_s4/SUM |
| 5.917 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n603_s6/I3 |
| 6.287 | 0.371 | tINS | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n603_s6/F |
| 6.524 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n603_s3/I0 |
| 7.042 | 0.517 | tINS | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n603_s3/F |
| 7.279 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n603_s1/I1 |
| 7.833 | 0.555 | tINS | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n603_s1/F |
| 8.071 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 13.462 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | |||
| 13.632 | 0.170 | tCL | RR | 258 | u_clkdiv/CLKOUT |
| 13.812 | 0.180 | tNET | RR | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0/CLK |
| 13.777 | -0.035 | tSu | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 13.462 |
| Logic Level: | 11 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay: | cell: 5.118, 66.296%; route: 2.370, 30.699%; tC2Q: 0.232, 3.005% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path 2
Path Summary:| Slack | 6.353 |
| Data Arrival Time | 7.424 |
| Data Required Time | 13.777 |
| From | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0 |
| To | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0 |
| Launch Clk | u_clkdiv/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_clkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | |||
| 0.170 | 0.170 | tCL | RR | 258 | u_clkdiv/CLKOUT |
| 0.350 | 0.180 | tNET | RR | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0/CLK |
| 0.582 | 0.232 | tC2Q | RF | 20 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0/Q |
| 0.819 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s20/I1 |
| 1.375 | 0.555 | tINS | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s20/F |
| 1.612 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s18/I1 |
| 2.167 | 0.555 | tINS | FF | 2 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s18/F |
| 2.404 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/I2 |
| 2.857 | 0.453 | tINS | FF | 4 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/F |
| 3.094 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s14/I0 |
| 3.611 | 0.517 | tINS | FF | 4 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s14/F |
| 3.848 | 0.237 | tNET | FF | 2 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n238_s5/I1 |
| 4.418 | 0.570 | tINS | FR | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n238_s5/COUT |
| 4.418 | 0.000 | tNET | RR | 2 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n237_s5/CIN |
| 4.887 | 0.470 | tINS | RF | 2 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n237_s5/SUM |
| 5.124 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n603_s6/I0 |
| 5.641 | 0.517 | tINS | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n603_s6/F |
| 5.878 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n603_s3/I0 |
| 6.396 | 0.517 | tINS | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n603_s3/F |
| 6.633 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n603_s1/I1 |
| 7.188 | 0.555 | tINS | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n603_s1/F |
| 7.424 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 13.462 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | |||
| 13.632 | 0.170 | tCL | RR | 258 | u_clkdiv/CLKOUT |
| 13.812 | 0.180 | tNET | RR | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0/CLK |
| 13.777 | -0.035 | tSu | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 13.462 |
| Logic Level: | 10 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay: | cell: 4.709, 66.567%; route: 2.133, 30.153%; tC2Q: 0.232, 3.280% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path 3
Path Summary:| Slack | 6.359 |
| Data Arrival Time | 7.418 |
| Data Required Time | 13.777 |
| From | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0 |
| To | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0 |
| Launch Clk | u_clkdiv/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_clkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | |||
| 0.170 | 0.170 | tCL | RR | 258 | u_clkdiv/CLKOUT |
| 0.350 | 0.180 | tNET | RR | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0/CLK |
| 0.582 | 0.232 | tC2Q | RF | 5 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_2_s0/Q |
| 0.819 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s19/I1 |
| 1.375 | 0.555 | tINS | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s19/F |
| 1.612 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s18/I1 |
| 2.167 | 0.555 | tINS | FF | 5 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s18/F |
| 2.404 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s17/I1 |
| 2.959 | 0.555 | tINS | FF | 2 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s17/F |
| 3.196 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15/I1 |
| 3.751 | 0.555 | tINS | FF | 5 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15/F |
| 3.988 | 0.237 | tNET | FF | 2 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n237_s5/I1 |
| 4.558 | 0.570 | tINS | FR | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n237_s5/COUT |
| 4.558 | 0.000 | tNET | RR | 2 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n236_s4/CIN |
| 5.028 | 0.470 | tINS | RF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n236_s4/SUM |
| 5.265 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n603_s6/I3 |
| 5.635 | 0.371 | tINS | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n603_s6/F |
| 5.872 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n603_s3/I0 |
| 6.390 | 0.517 | tINS | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n603_s3/F |
| 6.627 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n603_s1/I1 |
| 7.181 | 0.555 | tINS | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n603_s1/F |
| 7.418 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 13.462 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | |||
| 13.632 | 0.170 | tCL | RR | 258 | u_clkdiv/CLKOUT |
| 13.812 | 0.180 | tNET | RR | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0/CLK |
| 13.777 | -0.035 | tSu | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 13.462 |
| Logic Level: | 10 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay: | cell: 4.703, 66.540%; route: 2.133, 30.178%; tC2Q: 0.232, 3.282% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path 4
Path Summary:| Slack | 6.762 |
| Data Arrival Time | 7.015 |
| Data Required Time | 13.777 |
| From | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_1_s0 |
| To | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_3_s0 |
| Launch Clk | u_clkdiv/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_clkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | |||
| 0.170 | 0.170 | tCL | RR | 258 | u_clkdiv/CLKOUT |
| 0.350 | 0.180 | tNET | RR | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_1_s0/CLK |
| 0.582 | 0.232 | tC2Q | RF | 7 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_1_s0/Q |
| 0.819 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n688_s1/I1 |
| 1.375 | 0.555 | tINS | FF | 5 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n688_s1/F |
| 1.612 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s13/I1 |
| 2.167 | 0.555 | tINS | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s13/F |
| 2.404 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s12/I1 |
| 2.959 | 0.555 | tINS | FF | 4 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s12/F |
| 3.196 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n630_s1/I2 |
| 3.649 | 0.453 | tINS | FF | 3 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n630_s1/F |
| 3.886 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_2_s16/I0 |
| 4.403 | 0.517 | tINS | FF | 4 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_2_s16/F |
| 4.640 | 0.237 | tNET | FF | 2 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n237_s5/I1 |
| 5.194 | 0.555 | tINS | FF | 2 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n237_s5/SUM |
| 5.431 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n604_s3/I1 |
| 5.986 | 0.555 | tINS | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n604_s3/F |
| 6.223 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n604_s1/I1 |
| 6.778 | 0.555 | tINS | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n604_s1/F |
| 7.015 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_3_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 13.462 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | |||
| 13.632 | 0.170 | tCL | RR | 258 | u_clkdiv/CLKOUT |
| 13.812 | 0.180 | tNET | RR | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_3_s0/CLK |
| 13.777 | -0.035 | tSu | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_3_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 13.462 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay: | cell: 4.300, 64.516%; route: 2.133, 32.003%; tC2Q: 0.232, 3.481% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path 5
Path Summary:| Slack | 6.902 |
| Data Arrival Time | 6.876 |
| Data Required Time | 13.777 |
| From | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0 |
| To | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_3_s0 |
| Launch Clk | u_clkdiv/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_clkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | |||
| 0.170 | 0.170 | tCL | RR | 258 | u_clkdiv/CLKOUT |
| 0.350 | 0.180 | tNET | RR | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0/CLK |
| 0.582 | 0.232 | tC2Q | RF | 20 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0/Q |
| 0.819 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s20/I1 |
| 1.375 | 0.555 | tINS | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s20/F |
| 1.612 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s18/I1 |
| 2.167 | 0.555 | tINS | FF | 2 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s18/F |
| 2.404 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/I2 |
| 2.857 | 0.453 | tINS | FF | 4 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/F |
| 3.094 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s14/I0 |
| 3.611 | 0.517 | tINS | FF | 4 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s14/F |
| 3.848 | 0.237 | tNET | FF | 2 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n238_s5/I1 |
| 4.403 | 0.555 | tINS | FF | 3 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n238_s5/SUM |
| 4.640 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n604_s4/I0 |
| 5.157 | 0.517 | tINS | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n604_s4/F |
| 5.394 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n604_s3/I2 |
| 5.847 | 0.453 | tINS | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n604_s3/F |
| 6.084 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n604_s1/I1 |
| 6.639 | 0.555 | tINS | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n604_s1/F |
| 6.876 | 0.237 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_3_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 13.462 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | |||
| 13.632 | 0.170 | tCL | RR | 258 | u_clkdiv/CLKOUT |
| 13.812 | 0.180 | tNET | RR | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_3_s0/CLK |
| 13.777 | -0.035 | tSu | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_3_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 13.462 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay: | cell: 4.160, 63.754%; route: 2.133, 32.690%; tC2Q: 0.232, 3.556% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |