Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\EDID_PROM\data\edid_prom_top.v D:\Gowin\Gowin_V1.9.12.01_x64\IDE\ipcore\EDID_PROM\data\i2c_slave_wrapper.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12.01 (64-bit) |
| Part Number | GW2A-LV18PG484C8/I7 |
| Device | GW2A-18 |
| Device Version | C |
| Created Time | Fri Dec 26 15:40:59 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | EDID_PROM_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.083s, Peak memory usage = 176.145MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 176.145MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 176.145MB Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 176.145MB Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 176.145MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 176.145MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 176.145MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 176.145MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 176.145MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 176.145MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 176.145MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 176.145MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.671s, Elapsed time = 0h 0m 0.676s, Peak memory usage = 176.145MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 176.145MB Generate output files: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 176.145MB |
| Total Time and Memory Usage | CPU time = 0h 0m 0.824s, Elapsed time = 0h 0m 0.811s, Peak memory usage = 176.145MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 4 |
| I/O Buf | 4 |
| IBUF | 3 |
| IOBUF | 1 |
| Register | 70 |
| DFF | 2 |
| DFFE | 24 |
| DFFR | 3 |
| DFFP | 4 |
| DFFC | 8 |
| DFFCE | 29 |
| LUT | 157 |
| LUT2 | 16 |
| LUT3 | 36 |
| LUT4 | 105 |
| INV | 2 |
| INV | 2 |
| BSRAM | 1 |
| SDPB | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 159(159 LUT, 0 ALU) / 20736 | <1% |
| Register | 70 / 16512 | <1% |
| --Register as Latch | 0 / 16512 | 0% |
| --Register as FF | 70 / 16512 | <1% |
| BSRAM | 1 / 46 | 3% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | I_clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | I_clk_ibuf/I |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | I_clk | 100.000(MHz) | 176.087(MHz) | 6 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 4.321 |
| Data Arrival Time | 6.004 |
| Data Required Time | 10.325 |
| From | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_1_s0 |
| To | i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_0_s0 |
| Launch Clk | I_clk[R] |
| Latch Clk | I_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 71 | I_clk_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 1 | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_1_s0/CLK |
| 0.592 | 0.232 | tC2Q | RF | 10 | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_1_s0/Q |
| 1.066 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/n417_s6/I1 |
| 1.621 | 0.555 | tINS | FF | 10 | i2c_slave_wrapper_inst/u_i2c_slave/n417_s6/F |
| 2.095 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/word_add_flag_s5/I1 |
| 2.650 | 0.555 | tINS | FF | 2 | i2c_slave_wrapper_inst/u_i2c_slave/word_add_flag_s5/F |
| 3.124 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/word_address_7_s7/I1 |
| 3.679 | 0.555 | tINS | FF | 4 | i2c_slave_wrapper_inst/u_i2c_slave/word_address_7_s7/F |
| 4.153 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/addr_len_reg_8_s5/I1 |
| 4.708 | 0.555 | tINS | FF | 10 | i2c_slave_wrapper_inst/u_i2c_slave/addr_len_reg_8_s5/F |
| 5.182 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/n2252_s0/I2 |
| 5.644 | 0.462 | tINS | FR | 8 | i2c_slave_wrapper_inst/u_i2c_slave/n2252_s0/F |
| 6.004 | 0.360 | tNET | RR | 1 | i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_0_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 71 | I_clk_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_0_s0/CLK |
| 10.325 | -0.035 | tSu | 1 | i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 2.682, 47.519%; route: 2.730, 48.370%; tC2Q: 0.232, 4.111% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 2
Path Summary:| Slack | 4.321 |
| Data Arrival Time | 6.004 |
| Data Required Time | 10.325 |
| From | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_1_s0 |
| To | i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_1_s0 |
| Launch Clk | I_clk[R] |
| Latch Clk | I_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 71 | I_clk_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 1 | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_1_s0/CLK |
| 0.592 | 0.232 | tC2Q | RF | 10 | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_1_s0/Q |
| 1.066 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/n417_s6/I1 |
| 1.621 | 0.555 | tINS | FF | 10 | i2c_slave_wrapper_inst/u_i2c_slave/n417_s6/F |
| 2.095 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/word_add_flag_s5/I1 |
| 2.650 | 0.555 | tINS | FF | 2 | i2c_slave_wrapper_inst/u_i2c_slave/word_add_flag_s5/F |
| 3.124 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/word_address_7_s7/I1 |
| 3.679 | 0.555 | tINS | FF | 4 | i2c_slave_wrapper_inst/u_i2c_slave/word_address_7_s7/F |
| 4.153 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/addr_len_reg_8_s5/I1 |
| 4.708 | 0.555 | tINS | FF | 10 | i2c_slave_wrapper_inst/u_i2c_slave/addr_len_reg_8_s5/F |
| 5.182 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/n2252_s0/I2 |
| 5.644 | 0.462 | tINS | FR | 8 | i2c_slave_wrapper_inst/u_i2c_slave/n2252_s0/F |
| 6.004 | 0.360 | tNET | RR | 1 | i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_1_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 71 | I_clk_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_1_s0/CLK |
| 10.325 | -0.035 | tSu | 1 | i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_1_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 2.682, 47.519%; route: 2.730, 48.370%; tC2Q: 0.232, 4.111% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 3
Path Summary:| Slack | 4.321 |
| Data Arrival Time | 6.004 |
| Data Required Time | 10.325 |
| From | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_1_s0 |
| To | i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_2_s0 |
| Launch Clk | I_clk[R] |
| Latch Clk | I_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 71 | I_clk_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 1 | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_1_s0/CLK |
| 0.592 | 0.232 | tC2Q | RF | 10 | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_1_s0/Q |
| 1.066 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/n417_s6/I1 |
| 1.621 | 0.555 | tINS | FF | 10 | i2c_slave_wrapper_inst/u_i2c_slave/n417_s6/F |
| 2.095 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/word_add_flag_s5/I1 |
| 2.650 | 0.555 | tINS | FF | 2 | i2c_slave_wrapper_inst/u_i2c_slave/word_add_flag_s5/F |
| 3.124 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/word_address_7_s7/I1 |
| 3.679 | 0.555 | tINS | FF | 4 | i2c_slave_wrapper_inst/u_i2c_slave/word_address_7_s7/F |
| 4.153 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/addr_len_reg_8_s5/I1 |
| 4.708 | 0.555 | tINS | FF | 10 | i2c_slave_wrapper_inst/u_i2c_slave/addr_len_reg_8_s5/F |
| 5.182 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/n2252_s0/I2 |
| 5.644 | 0.462 | tINS | FR | 8 | i2c_slave_wrapper_inst/u_i2c_slave/n2252_s0/F |
| 6.004 | 0.360 | tNET | RR | 1 | i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_2_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 71 | I_clk_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_2_s0/CLK |
| 10.325 | -0.035 | tSu | 1 | i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_2_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 2.682, 47.519%; route: 2.730, 48.370%; tC2Q: 0.232, 4.111% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 4
Path Summary:| Slack | 4.321 |
| Data Arrival Time | 6.004 |
| Data Required Time | 10.325 |
| From | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_1_s0 |
| To | i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_3_s0 |
| Launch Clk | I_clk[R] |
| Latch Clk | I_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 71 | I_clk_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 1 | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_1_s0/CLK |
| 0.592 | 0.232 | tC2Q | RF | 10 | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_1_s0/Q |
| 1.066 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/n417_s6/I1 |
| 1.621 | 0.555 | tINS | FF | 10 | i2c_slave_wrapper_inst/u_i2c_slave/n417_s6/F |
| 2.095 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/word_add_flag_s5/I1 |
| 2.650 | 0.555 | tINS | FF | 2 | i2c_slave_wrapper_inst/u_i2c_slave/word_add_flag_s5/F |
| 3.124 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/word_address_7_s7/I1 |
| 3.679 | 0.555 | tINS | FF | 4 | i2c_slave_wrapper_inst/u_i2c_slave/word_address_7_s7/F |
| 4.153 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/addr_len_reg_8_s5/I1 |
| 4.708 | 0.555 | tINS | FF | 10 | i2c_slave_wrapper_inst/u_i2c_slave/addr_len_reg_8_s5/F |
| 5.182 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/n2252_s0/I2 |
| 5.644 | 0.462 | tINS | FR | 8 | i2c_slave_wrapper_inst/u_i2c_slave/n2252_s0/F |
| 6.004 | 0.360 | tNET | RR | 1 | i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_3_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 71 | I_clk_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_3_s0/CLK |
| 10.325 | -0.035 | tSu | 1 | i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_3_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 2.682, 47.519%; route: 2.730, 48.370%; tC2Q: 0.232, 4.111% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 5
Path Summary:| Slack | 4.321 |
| Data Arrival Time | 6.004 |
| Data Required Time | 10.325 |
| From | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_1_s0 |
| To | i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_4_s0 |
| Launch Clk | I_clk[R] |
| Latch Clk | I_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 71 | I_clk_ibuf/O |
| 0.360 | 0.360 | tNET | RR | 1 | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_1_s0/CLK |
| 0.592 | 0.232 | tC2Q | RF | 10 | i2c_slave_wrapper_inst/u_i2c_slave/bit_counter_1_s0/Q |
| 1.066 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/n417_s6/I1 |
| 1.621 | 0.555 | tINS | FF | 10 | i2c_slave_wrapper_inst/u_i2c_slave/n417_s6/F |
| 2.095 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/word_add_flag_s5/I1 |
| 2.650 | 0.555 | tINS | FF | 2 | i2c_slave_wrapper_inst/u_i2c_slave/word_add_flag_s5/F |
| 3.124 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/word_address_7_s7/I1 |
| 3.679 | 0.555 | tINS | FF | 4 | i2c_slave_wrapper_inst/u_i2c_slave/word_address_7_s7/F |
| 4.153 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/addr_len_reg_8_s5/I1 |
| 4.708 | 0.555 | tINS | FF | 10 | i2c_slave_wrapper_inst/u_i2c_slave/addr_len_reg_8_s5/F |
| 5.182 | 0.474 | tNET | FF | 1 | i2c_slave_wrapper_inst/u_i2c_slave/n2252_s0/I2 |
| 5.644 | 0.462 | tINS | FR | 8 | i2c_slave_wrapper_inst/u_i2c_slave/n2252_s0/F |
| 6.004 | 0.360 | tNET | RR | 1 | i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_4_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_clk_ibuf/I |
| 10.000 | 0.000 | tINS | RR | 71 | I_clk_ibuf/O |
| 10.360 | 0.360 | tNET | RR | 1 | i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_4_s0/CLK |
| 10.325 | -0.035 | tSu | 1 | i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_4_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 2.682, 47.519%; route: 2.730, 48.370%; tC2Q: 0.232, 4.111% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |