Timing Messages

Report Title	Timing Analysis Report
Design File	D:\proj\Gowin_DVI_RX_RefDesign\project\impl\gwsynthesis\dk_video.vg
Physical Constraints File	D:\proj\Gowin_DVI_RX_RefDesign\project\src\dk_video.cst
Timing Constraint File	D:\proj\Gowin_DVI_RX_RefDesign\project\src\dk_video.sdc
Tool Version	V1.9.12.01 (64-bit)
Part Number	GW2A-LV18PG484C8/I7
Device	GW2A-18
Device Version	C
Created Time	Fri Dec 26 16:24:14 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.95V 85C C8/I7
Hold Delay Model	Fast 1.05V 0C C8/I7
Numbers of Paths Analyzed	1490
Numbers of Endpoints Analyzed	1376
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	I_tmds_clk_p	Base	13.468	74.250	0.000	6.734			I_tmds_clk_p
2	hclkx5	Base	2.694	371.195	0.000	1.347			DVI_RX_Top_inst/dvi2rgb_inst/hclkx5
3	I_clk	Base	20.000	50.000	0.000	10.000			I_clk
4	rx0_pclk	Base	13.468	74.250	0.000	6.734			rx0_pclk
5	DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUT.default_gen_clk	Generated	2.694	371.250	0.000	1.347	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I	I_tmds_clk_p	DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUT
6	DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUTD.default_gen_clk	Generated	13.468	74.250	0.000	6.734	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I	I_tmds_clk_p	DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUTD
7	DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUTD3.default_gen_clk	Generated	8.081	123.750	0.000	4.040	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I	I_tmds_clk_p	DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUTD3
8	u_tmds_rpll/rpll_inst/CLKOUT.default_gen_clk	Generated	2.694	371.250	0.000	1.347	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT	rx0_pclk	u_tmds_rpll/rpll_inst/CLKOUT
9	u_tmds_rpll/rpll_inst/CLKOUTP.default_gen_clk	Generated	2.694	371.250	0.000	1.347	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT	rx0_pclk	u_tmds_rpll/rpll_inst/CLKOUTP
10	u_tmds_rpll/rpll_inst/CLKOUTD.default_gen_clk	Generated	5.387	185.625	0.000	2.694	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT	rx0_pclk	u_tmds_rpll/rpll_inst/CLKOUTD
11	u_tmds_rpll/rpll_inst/CLKOUTD3.default_gen_clk	Generated	8.081	123.750	0.000	4.040	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT	rx0_pclk	u_tmds_rpll/rpll_inst/CLKOUTD3

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	I_tmds_clk_p	74.250(MHz)	326.647(MHz)	4	TOP
2	I_clk	50.000(MHz)	186.767(MHz)	6	TOP
3	rx0_pclk	74.250(MHz)	111.072(MHz)	10	TOP

No timing paths to get frequency of hclkx5!

No timing paths to get frequency of DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUT.default_gen_clk!

No timing paths to get frequency of DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUTD.default_gen_clk!

No timing paths to get frequency of DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUTD3.default_gen_clk!

No timing paths to get frequency of u_tmds_rpll/rpll_inst/CLKOUT.default_gen_clk!

No timing paths to get frequency of u_tmds_rpll/rpll_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of u_tmds_rpll/rpll_inst/CLKOUTD.default_gen_clk!

No timing paths to get frequency of u_tmds_rpll/rpll_inst/CLKOUTD3.default_gen_clk!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
I_tmds_clk_p	Setup	0.000	0
I_tmds_clk_p	Hold	0.000	0
hclkx5	Setup	0.000	0
hclkx5	Hold	0.000	0
I_clk	Setup	0.000	0
I_clk	Hold	0.000	0
rx0_pclk	Setup	0.000	0
rx0_pclk	Hold	0.000	0
DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUT.default_gen_clk	Setup	0.000	0
DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUT.default_gen_clk	Hold	0.000	0
DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUTD.default_gen_clk	Setup	0.000	0
DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUTD.default_gen_clk	Hold	0.000	0
DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUTD3.default_gen_clk	Setup	0.000	0
DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUTD3.default_gen_clk	Hold	0.000	0
u_tmds_rpll/rpll_inst/CLKOUT.default_gen_clk	Setup	0.000	0
u_tmds_rpll/rpll_inst/CLKOUT.default_gen_clk	Hold	0.000	0
u_tmds_rpll/rpll_inst/CLKOUTP.default_gen_clk	Setup	0.000	0
u_tmds_rpll/rpll_inst/CLKOUTP.default_gen_clk	Hold	0.000	0
u_tmds_rpll/rpll_inst/CLKOUTD.default_gen_clk	Setup	0.000	0
u_tmds_rpll/rpll_inst/CLKOUTD.default_gen_clk	Hold	0.000	0
u_tmds_rpll/rpll_inst/CLKOUTD3.default_gen_clk	Setup	0.000	0
u_tmds_rpll/rpll_inst/CLKOUTD3.default_gen_clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	4.465	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/search_dog_cnt_12_s0/Q	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_3_s1/D	rx0_pclk:[R]	rx0_pclk:[R]	13.468	0.000	8.968
2	4.524	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/search_dog_cnt_12_s0/Q	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_1_s1/D	rx0_pclk:[R]	rx0_pclk:[R]	13.468	0.000	8.909
3	4.673	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/search_dog_cnt_12_s0/Q	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_0_s1/D	rx0_pclk:[R]	rx0_pclk:[R]	13.468	0.000	8.760
4	4.772	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/search_dog_cnt_12_s0/Q	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_2_s1/D	rx0_pclk:[R]	rx0_pclk:[R]	13.468	0.000	8.661
5	5.018	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_2_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0/D	rx0_pclk:[R]	rx0_pclk:[R]	13.468	0.000	8.415
6	5.393	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Gali_15_s0/Q	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_1_s1/CE	rx0_pclk:[R]	rx0_pclk:[R]	13.468	0.000	8.040
7	5.393	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Gali_15_s0/Q	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_2_s1/CE	rx0_pclk:[R]	rx0_pclk:[R]	13.468	0.000	8.040
8	5.396	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Gali_15_s0/Q	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/seam_cnt_0_s1/D	rx0_pclk:[R]	rx0_pclk:[R]	13.468	0.000	8.037
9	5.396	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Gali_15_s0/Q	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/seam_cnt_1_s1/D	rx0_pclk:[R]	rx0_pclk:[R]	13.468	0.000	8.037
10	5.438	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_1_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0/D	rx0_pclk:[R]	rx0_pclk:[R]	13.468	0.000	7.995
11	5.450	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Gali_15_s0/Q	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_0_s1/D	rx0_pclk:[R]	rx0_pclk:[R]	13.468	0.000	7.983
12	5.491	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Gali_15_s0/Q	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/seam_cnt_2_s1/D	rx0_pclk:[R]	rx0_pclk:[R]	13.468	0.000	7.942
13	5.665	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_1_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0/D	rx0_pclk:[R]	rx0_pclk:[R]	13.468	0.000	7.768
14	6.029	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Gali_11_s0/Q	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s1/D	rx0_pclk:[R]	rx0_pclk:[R]	13.468	0.000	7.404
15	6.144	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0/D	rx0_pclk:[R]	rx0_pclk:[R]	13.468	0.000	7.289
16	6.172	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_2_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_3_s0/D	rx0_pclk:[R]	rx0_pclk:[R]	13.468	0.000	7.261
17	6.495	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_2_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_2_s0/D	rx0_pclk:[R]	rx0_pclk:[R]	13.468	0.000	6.938
18	6.549	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_2_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_1_s0/D	rx0_pclk:[R]	rx0_pclk:[R]	13.468	0.000	6.884
19	6.623	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_3_s0/D	rx0_pclk:[R]	rx0_pclk:[R]	13.468	0.000	6.810
20	6.646	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_1_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_2_s0/D	rx0_pclk:[R]	rx0_pclk:[R]	13.468	0.000	6.787
21	6.782	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_1_s1/Q	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_7_s3/D	rx0_pclk:[R]	rx0_pclk:[R]	13.468	0.000	6.651
22	6.855	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_2_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_1_s0/D	rx0_pclk:[R]	rx0_pclk:[R]	13.468	0.000	6.578
23	6.887	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/search_dog_cnt_1_s0/Q	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/search_dog_cnt_29_s0/D	rx0_pclk:[R]	rx0_pclk:[R]	13.468	0.000	6.546
24	6.932	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_1_s1/Q	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_17_s1/D	rx0_pclk:[R]	rx0_pclk:[R]	13.468	0.000	6.501
25	6.939	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_5_s0/D	rx0_pclk:[R]	rx0_pclk:[R]	13.468	0.000	6.494

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.205	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_7_s0/Q	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/sdpb_inst_0/ADB[10]	I_clk:[R]	I_clk:[R]	0.000	0.000	0.323
2	0.205	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_3_s0/Q	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/sdpb_inst_0/ADB[6]	I_clk:[R]	I_clk:[R]	0.000	0.000	0.323
3	0.324	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/wre_reg_s0/Q	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/rom_out_reg_4_s0/CE	I_clk:[R]	I_clk:[R]	0.000	0.000	0.335
4	0.324	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/wre_reg_s0/Q	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/rom_out_reg_5_s0/CE	I_clk:[R]	I_clk:[R]	0.000	0.000	0.335
5	0.324	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/wre_reg_s0/Q	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/rom_out_reg_7_s0/CE	I_clk:[R]	I_clk:[R]	0.000	0.000	0.335
6	0.329	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_0_s0/Q	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/sdpb_inst_0/ADB[3]	I_clk:[R]	I_clk:[R]	0.000	0.000	0.447
7	0.333	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_5_s0/Q	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/sdpb_inst_0/ADB[8]	I_clk:[R]	I_clk:[R]	0.000	0.000	0.451
8	0.344	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_6_s0/Q	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/sdpb_inst_0/ADB[9]	I_clk:[R]	I_clk:[R]	0.000	0.000	0.462
9	0.344	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_4_s0/Q	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/sdpb_inst_0/ADB[7]	I_clk:[R]	I_clk:[R]	0.000	0.000	0.462
10	0.344	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_2_s0/Q	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/sdpb_inst_0/ADB[5]	I_clk:[R]	I_clk:[R]	0.000	0.000	0.462
11	0.344	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_1_s0/Q	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/sdpb_inst_0/ADB[4]	I_clk:[R]	I_clk:[R]	0.000	0.000	0.462
12	0.425	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_8_s0/Q	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_8_s0/D	I_tmds_clk_p:[R]	I_tmds_clk_p:[R]	0.000	0.000	0.436
13	0.425	DVI_RX_Top_inst/dvi2rgb_inst/u_tmds_b/ctrl1_s4/Q	DVI_RX_Top_inst/dvi2rgb_inst/u_tmds_b/ctrl1_s4/D	rx0_pclk:[R]	rx0_pclk:[R]	0.000	0.000	0.436
14	0.425	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_11_s3/Q	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_11_s3/D	rx0_pclk:[R]	rx0_pclk:[R]	0.000	0.000	0.436
15	0.425	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_16_s3/Q	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_16_s3/D	rx0_pclk:[R]	rx0_pclk:[R]	0.000	0.000	0.436
16	0.425	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/r_chk_cnt_0_s3/Q	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/r_chk_cnt_0_s3/D	rx0_pclk:[R]	rx0_pclk:[R]	0.000	0.000	0.436
17	0.425	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/phase_lock_s3/Q	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/phase_lock_s3/D	rx0_pclk:[R]	rx0_pclk:[R]	0.000	0.000	0.436
18	0.425	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_17_s1/Q	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_17_s1/D	rx0_pclk:[R]	rx0_pclk:[R]	0.000	0.000	0.436
19	0.425	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/r_chk_cnt_1_s1/Q	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/r_chk_cnt_1_s1/D	rx0_pclk:[R]	rx0_pclk:[R]	0.000	0.000	0.436
20	0.425	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/r_code_clk_cnt_6_s1/Q	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/r_code_clk_cnt_6_s1/D	rx0_pclk:[R]	rx0_pclk:[R]	0.000	0.000	0.436
21	0.425	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_chk_cnt_0_s1/Q	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_chk_cnt_0_s1/D	rx0_pclk:[R]	rx0_pclk:[R]	0.000	0.000	0.436
22	0.425	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_chk_cnt_2_s1/Q	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_chk_cnt_2_s1/D	rx0_pclk:[R]	rx0_pclk:[R]	0.000	0.000	0.436
23	0.425	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_code_clk_cnt_3_s1/Q	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_code_clk_cnt_3_s1/D	rx0_pclk:[R]	rx0_pclk:[R]	0.000	0.000	0.436
24	0.425	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_code_clk_cnt_5_s1/Q	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_code_clk_cnt_5_s1/D	rx0_pclk:[R]	rx0_pclk:[R]	0.000	0.000	0.436
25	0.425	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_code_clk_cnt_6_s1/Q	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_code_clk_cnt_6_s1/D	rx0_pclk:[R]	rx0_pclk:[R]	0.000	0.000	0.436

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	10.795	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/ides10_rst_s0/Q	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_R_DATA/RESET	rx0_pclk:[R]	rx0_pclk:[R]	13.468	0.000	2.556
2	10.795	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/ides10_rst_s0/Q	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_G_DATA/RESET	rx0_pclk:[R]	rx0_pclk:[R]	13.468	0.000	2.556
3	10.795	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/ides10_rst_s0/Q	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_B_DATA/RESET	rx0_pclk:[R]	rx0_pclk:[R]	13.468	0.000	2.556

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	1.626	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/ides10_rst_s0/Q	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_R_DATA/RESET	rx0_pclk:[R]	rx0_pclk:[R]	0.000	0.000	1.736
2	1.626	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/ides10_rst_s0/Q	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_G_DATA/RESET	rx0_pclk:[R]	rx0_pclk:[R]	0.000	0.000	1.736
3	1.626	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/ides10_rst_s0/Q	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_B_DATA/RESET	rx0_pclk:[R]	rx0_pclk:[R]	0.000	0.000	1.736

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	3.675	4.675	1.000	Low Pulse Width	I_tmds_clk_p	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_11_s0
2	3.675	4.675	1.000	Low Pulse Width	I_tmds_clk_p	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_10_s0
3	3.675	4.675	1.000	Low Pulse Width	I_tmds_clk_p	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_9_s0
4	3.675	4.675	1.000	Low Pulse Width	I_tmds_clk_p	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_8_s0
5	3.675	4.675	1.000	Low Pulse Width	I_tmds_clk_p	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_7_s0
6	3.675	4.675	1.000	Low Pulse Width	I_tmds_clk_p	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_3_s0
7	3.675	4.675	1.000	Low Pulse Width	I_tmds_clk_p	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_2_s0
8	3.675	4.675	1.000	Low Pulse Width	I_tmds_clk_p	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pll_rerst_s0
9	3.675	4.675	1.000	Low Pulse Width	I_tmds_clk_p	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_1_s0
10	3.675	4.675	1.000	Low Pulse Width	I_tmds_clk_p	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_0_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	4.465
Data Arrival Time	11.239
Data Required Time	15.704
From	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/search_dog_cnt_12_s0
To	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_3_s1
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
2.271	2.271	tNET	RR	1	R30C17[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/search_dog_cnt_12_s0/CLK
2.503	0.232	tC2Q	RF	4	R30C17[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/search_dog_cnt_12_s0/Q
3.320	0.817	tNET	FF	1	R26C17[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n12_s9/I3
3.837	0.517	tINS	FF	1	R26C17[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n12_s9/F
4.327	0.490	tNET	FF	1	R29C17[3][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n12_s6/I1
4.897	0.570	tINS	FR	1	R29C17[3][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n12_s6/F
4.898	0.001	tNET	RR	1	R29C17[2][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n12_s4/I0
5.415	0.517	tINS	RF	5	R29C17[2][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n12_s4/F
6.538	1.122	tNET	FF	1	R29C28[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n13_s6/I2
7.093	0.555	tINS	FF	2	R29C28[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n13_s6/F
7.494	0.401	tNET	FF	1	R29C29[2][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n14_s2/I0
8.011	0.517	tINS	FF	2	R29C29[2][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n14_s2/F
8.433	0.422	tNET	FF	1	R30C28[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_next_1_s22/I0
9.003	0.570	tINS	FR	1	R30C28[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_next_1_s22/F
9.176	0.172	tNET	RR	2	R30C27[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n8_s0/I1
9.746	0.570	tINS	RR	1	R30C27[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n8_s0/COUT
9.746	0.000	tNET	RR	2	R30C27[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n9_s0/CIN
9.781	0.035	tINS	RF	1	R30C27[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n9_s0/COUT
9.781	0.000	tNET	FF	2	R30C27[2][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n10_s0/CIN
9.816	0.035	tINS	FF	4	R30C27[2][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n10_s0/COUT
10.868	1.052	tNET	FF	1	R29C28[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n12_s0/I3
11.239	0.371	tINS	FF	1	R29C28[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n12_s0/F
11.239	0.000	tNET	FF	1	R29C28[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.468	13.468					active clock edge time
13.468	0.000					rx0_pclk
13.468	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
15.739	2.271	tNET	RR	1	R29C28[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_3_s1/CLK
15.704	-0.035	tSu		1	R29C28[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_3_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.468
Logic Level	10
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 4.257, 47.473%; route: 4.479, 49.940%; tC2Q: 0.232, 2.587%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path2

Path Summary:

Slack	4.524
Data Arrival Time	11.181
Data Required Time	15.704
From	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/search_dog_cnt_12_s0
To	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_1_s1
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
2.271	2.271	tNET	RR	1	R30C17[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/search_dog_cnt_12_s0/CLK
2.503	0.232	tC2Q	RF	4	R30C17[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/search_dog_cnt_12_s0/Q
3.320	0.817	tNET	FF	1	R26C17[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n12_s9/I3
3.837	0.517	tINS	FF	1	R26C17[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n12_s9/F
4.327	0.490	tNET	FF	1	R29C17[3][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n12_s6/I1
4.897	0.570	tINS	FR	1	R29C17[3][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n12_s6/F
4.898	0.001	tNET	RR	1	R29C17[2][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n12_s4/I0
5.415	0.517	tINS	RF	5	R29C17[2][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n12_s4/F
6.538	1.122	tNET	FF	1	R29C28[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n13_s6/I2
7.093	0.555	tINS	FF	2	R29C28[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n13_s6/F
7.494	0.401	tNET	FF	1	R29C29[2][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n14_s2/I0
8.011	0.517	tINS	FF	2	R29C29[2][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n14_s2/F
8.433	0.422	tNET	FF	1	R30C28[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_next_1_s22/I0
9.003	0.570	tINS	FR	1	R30C28[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_next_1_s22/F
9.176	0.172	tNET	RR	2	R30C27[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n8_s0/I1
9.746	0.570	tINS	RR	1	R30C27[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n8_s0/COUT
9.746	0.000	tNET	RR	2	R30C27[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n9_s0/CIN
9.781	0.035	tINS	RF	1	R30C27[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n9_s0/COUT
9.781	0.000	tNET	FF	2	R30C27[2][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n10_s0/CIN
9.816	0.035	tINS	FF	4	R30C27[2][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n10_s0/COUT
10.719	0.902	tNET	FF	1	R29C28[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n14_s0/I3
11.181	0.462	tINS	FR	1	R29C28[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n14_s0/F
11.181	0.000	tNET	RR	1	R29C28[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.468	13.468					active clock edge time
13.468	0.000					rx0_pclk
13.468	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
15.739	2.271	tNET	RR	1	R29C28[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_1_s1/CLK
15.704	-0.035	tSu		1	R29C28[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_1_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.468
Logic Level	10
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 4.348, 48.808%; route: 4.329, 48.588%; tC2Q: 0.232, 2.604%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path3

Path Summary:

Slack	4.673
Data Arrival Time	11.031
Data Required Time	15.704
From	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/search_dog_cnt_12_s0
To	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_0_s1
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
2.271	2.271	tNET	RR	1	R30C17[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/search_dog_cnt_12_s0/CLK
2.503	0.232	tC2Q	RF	4	R30C17[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/search_dog_cnt_12_s0/Q
3.320	0.817	tNET	FF	1	R26C17[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n12_s9/I3
3.837	0.517	tINS	FF	1	R26C17[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n12_s9/F
4.327	0.490	tNET	FF	1	R29C17[3][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n12_s6/I1
4.897	0.570	tINS	FR	1	R29C17[3][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n12_s6/F
4.898	0.001	tNET	RR	1	R29C17[2][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n12_s4/I0
5.415	0.517	tINS	RF	5	R29C17[2][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n12_s4/F
6.538	1.122	tNET	FF	1	R29C28[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n13_s6/I2
7.093	0.555	tINS	FF	2	R29C28[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n13_s6/F
7.494	0.401	tNET	FF	1	R29C29[2][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n14_s2/I0
8.011	0.517	tINS	FF	2	R29C29[2][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n14_s2/F
8.433	0.422	tNET	FF	1	R30C28[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_next_1_s22/I0
9.003	0.570	tINS	FR	1	R30C28[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_next_1_s22/F
9.176	0.172	tNET	RR	2	R30C27[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n8_s0/I1
9.746	0.570	tINS	RR	1	R30C27[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n8_s0/COUT
9.746	0.000	tNET	RR	2	R30C27[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n9_s0/CIN
9.781	0.035	tINS	RF	1	R30C27[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n9_s0/COUT
9.781	0.000	tNET	FF	2	R30C27[2][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n10_s0/CIN
9.816	0.035	tINS	FF	4	R30C27[2][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n10_s0/COUT
10.461	0.645	tNET	FF	1	R30C26[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n15_s0/I2
11.031	0.570	tINS	FR	1	R30C26[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n15_s0/F
11.031	0.000	tNET	RR	1	R30C26[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.468	13.468					active clock edge time
13.468	0.000					rx0_pclk
13.468	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
15.739	2.271	tNET	RR	1	R30C26[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_0_s1/CLK
15.704	-0.035	tSu		1	R30C26[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_0_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.468
Logic Level	10
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 4.456, 50.874%; route: 4.071, 46.478%; tC2Q: 0.232, 2.648%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path4

Path Summary:

Slack	4.772
Data Arrival Time	10.932
Data Required Time	15.704
From	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/search_dog_cnt_12_s0
To	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_2_s1
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
2.271	2.271	tNET	RR	1	R30C17[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/search_dog_cnt_12_s0/CLK
2.503	0.232	tC2Q	RF	4	R30C17[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/search_dog_cnt_12_s0/Q
3.320	0.817	tNET	FF	1	R26C17[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n12_s9/I3
3.837	0.517	tINS	FF	1	R26C17[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n12_s9/F
4.327	0.490	tNET	FF	1	R29C17[3][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n12_s6/I1
4.897	0.570	tINS	FR	1	R29C17[3][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n12_s6/F
4.898	0.001	tNET	RR	1	R29C17[2][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n12_s4/I0
5.415	0.517	tINS	RF	5	R29C17[2][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n12_s4/F
6.538	1.122	tNET	FF	1	R29C28[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n13_s6/I2
7.093	0.555	tINS	FF	2	R29C28[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n13_s6/F
7.494	0.401	tNET	FF	1	R29C29[2][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n14_s2/I0
8.011	0.517	tINS	FF	2	R29C29[2][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n14_s2/F
8.433	0.422	tNET	FF	1	R30C28[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_next_1_s22/I0
9.003	0.570	tINS	FR	1	R30C28[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_next_1_s22/F
9.176	0.172	tNET	RR	2	R30C27[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n8_s0/I1
9.746	0.570	tINS	RR	1	R30C27[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n8_s0/COUT
9.746	0.000	tNET	RR	2	R30C27[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n9_s0/CIN
9.781	0.035	tINS	RF	1	R30C27[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n9_s0/COUT
9.781	0.000	tNET	FF	2	R30C27[2][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n10_s0/CIN
9.816	0.035	tINS	FF	4	R30C27[2][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n10_s0/COUT
10.470	0.654	tNET	FF	1	R30C28[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n13_s0/I3
10.932	0.462	tINS	FR	1	R30C28[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n13_s0/F
10.932	0.000	tNET	RR	1	R30C28[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.468	13.468					active clock edge time
13.468	0.000					rx0_pclk
13.468	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
15.739	2.271	tNET	RR	1	R30C28[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_2_s1/CLK
15.704	-0.035	tSu		1	R30C28[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_2_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.468
Logic Level	10
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 4.348, 50.208%; route: 4.080, 47.114%; tC2Q: 0.232, 2.679%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path5

Path Summary:

Slack	5.018
Data Arrival Time	10.686
Data Required Time	15.704
From	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_2_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
2.271	2.271	tNET	RR	1	R18C20[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_2_s0/CLK
2.503	0.232	tC2Q	RF	5	R18C20[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_2_s0/Q
3.182	0.679	tNET	FF	1	R17C17[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s4/I0
3.737	0.555	tINS	FF	4	R17C17[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s4/F
4.390	0.653	tNET	FF	1	R18C18[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s17/I2
4.761	0.371	tINS	FF	3	R18C18[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s17/F
5.257	0.496	tNET	FF	1	R17C19[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s12/I2
5.812	0.555	tINS	FF	4	R17C19[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s12/F
6.009	0.198	tNET	FF	1	R17C20[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n630_s1/I2
6.558	0.549	tINS	FR	3	R17C20[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n630_s1/F
6.561	0.003	tNET	RR	1	R17C20[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_2_s16/I0
6.932	0.371	tINS	RF	4	R17C20[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_2_s16/F
7.598	0.666	tNET	FF	2	R18C23[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n559_s0/I1
7.969	0.371	tINS	FF	1	R18C23[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n559_s0/COUT
8.443	0.474	tNET	FF	1	R18C23[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n603_s7/I2
9.013	0.570	tINS	FR	1	R18C23[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n603_s7/F
9.186	0.172	tNET	RR	1	R18C22[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n603_s2/I0
9.703	0.517	tINS	RF	1	R18C22[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n603_s2/F
10.116	0.413	tNET	FF	1	R17C23[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n603_s1/I0
10.686	0.570	tINS	FR	1	R17C23[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n603_s1/F
10.686	0.000	tNET	RR	1	R17C23[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.468	13.468					active clock edge time
13.468	0.000					rx0_pclk
13.468	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
15.739	2.271	tNET	RR	1	R17C23[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0/CLK
15.704	-0.035	tSu		1	R17C23[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.468
Logic Level	10
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 4.429, 52.634%; route: 3.754, 44.609%; tC2Q: 0.232, 2.757%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path6

Path Summary:

Slack	5.393
Data Arrival Time	10.311
Data Required Time	15.704
From	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Gali_15_s0
To	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_1_s1
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
2.271	2.271	tNET	RR	1	R9C18[0][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Gali_15_s0/CLK
2.503	0.232	tC2Q	RF	7	R9C18[0][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Gali_15_s0/Q
4.280	1.777	tNET	FF	1	R24C22[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s120/I1
4.835	0.555	tINS	FF	4	R24C22[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s120/F
5.737	0.902	tNET	FF	1	R24C27[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s88/I3
6.307	0.570	tINS	FR	1	R24C27[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s88/F
6.451	0.144	tNET	RR	1	R24C27[2][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s40/I3
6.968	0.517	tINS	RF	1	R24C27[2][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s40/F
7.365	0.397	tNET	FF	1	R26C27[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s16/I1
7.914	0.549	tINS	FR	1	R26C27[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s16/F
7.915	0.001	tNET	RR	1	R26C27[0][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s7/I3
8.368	0.453	tINS	RF	2	R26C27[0][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s7/F
8.980	0.612	tNET	FF	1	R26C33[2][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s4/I0
9.529	0.549	tINS	FR	2	R26C33[2][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s4/F
9.705	0.176	tNET	RR	1	R25C33[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_2_s4/I0
10.167	0.462	tINS	RR	2	R25C33[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_2_s4/F
10.311	0.144	tNET	RR	1	R25C33[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_1_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.468	13.468					active clock edge time
13.468	0.000					rx0_pclk
13.468	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
15.739	2.271	tNET	RR	1	R25C33[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_1_s1/CLK
15.704	-0.035	tSu		1	R25C33[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_1_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.468
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.655, 45.460%; route: 4.153, 51.654%; tC2Q: 0.232, 2.886%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path7

Path Summary:

Slack	5.393
Data Arrival Time	10.311
Data Required Time	15.704
From	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Gali_15_s0
To	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_2_s1
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
2.271	2.271	tNET	RR	1	R9C18[0][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Gali_15_s0/CLK
2.503	0.232	tC2Q	RF	7	R9C18[0][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Gali_15_s0/Q
4.280	1.777	tNET	FF	1	R24C22[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s120/I1
4.835	0.555	tINS	FF	4	R24C22[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s120/F
5.737	0.902	tNET	FF	1	R24C27[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s88/I3
6.307	0.570	tINS	FR	1	R24C27[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s88/F
6.451	0.144	tNET	RR	1	R24C27[2][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s40/I3
6.968	0.517	tINS	RF	1	R24C27[2][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s40/F
7.365	0.397	tNET	FF	1	R26C27[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s16/I1
7.914	0.549	tINS	FR	1	R26C27[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s16/F
7.915	0.001	tNET	RR	1	R26C27[0][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s7/I3
8.368	0.453	tINS	RF	2	R26C27[0][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s7/F
8.980	0.612	tNET	FF	1	R26C33[2][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s4/I0
9.529	0.549	tINS	FR	2	R26C33[2][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s4/F
9.705	0.176	tNET	RR	1	R25C33[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_2_s4/I0
10.167	0.462	tINS	RR	2	R25C33[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_2_s4/F
10.311	0.144	tNET	RR	1	R25C33[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_2_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.468	13.468					active clock edge time
13.468	0.000					rx0_pclk
13.468	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
15.739	2.271	tNET	RR	1	R25C33[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_2_s1/CLK
15.704	-0.035	tSu		1	R25C33[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_2_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.468
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.655, 45.460%; route: 4.153, 51.654%; tC2Q: 0.232, 2.886%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path8

Path Summary:

Slack	5.396
Data Arrival Time	10.308
Data Required Time	15.704
From	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Gali_15_s0
To	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/seam_cnt_0_s1
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
2.271	2.271	tNET	RR	1	R9C18[0][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Gali_15_s0/CLK
2.503	0.232	tC2Q	RF	7	R9C18[0][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Gali_15_s0/Q
4.280	1.777	tNET	FF	1	R24C22[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s120/I1
4.835	0.555	tINS	FF	4	R24C22[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s120/F
5.737	0.902	tNET	FF	1	R24C27[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s88/I3
6.307	0.570	tINS	FR	1	R24C27[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s88/F
6.451	0.144	tNET	RR	1	R24C27[2][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s40/I3
6.968	0.517	tINS	RF	1	R24C27[2][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s40/F
7.365	0.397	tNET	FF	1	R26C27[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s16/I1
7.914	0.549	tINS	FR	1	R26C27[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s16/F
7.915	0.001	tNET	RR	1	R26C27[0][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s7/I3
8.368	0.453	tINS	RF	2	R26C27[0][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s7/F
9.207	0.839	tNET	FF	1	R26C33[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1912_s2/I0
9.669	0.462	tINS	FR	3	R26C33[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1912_s2/F
9.846	0.177	tNET	RR	1	R26C34[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1912_s1/I1
10.308	0.462	tINS	RR	1	R26C34[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1912_s1/F
10.308	0.000	tNET	RR	1	R26C34[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/seam_cnt_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.468	13.468					active clock edge time
13.468	0.000					rx0_pclk
13.468	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
15.739	2.271	tNET	RR	1	R26C34[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/seam_cnt_0_s1/CLK
15.704	-0.035	tSu		1	R26C34[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/seam_cnt_0_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.468
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.568, 44.397%; route: 4.237, 52.717%; tC2Q: 0.232, 2.887%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path9

Path Summary:

Slack	5.396
Data Arrival Time	10.308
Data Required Time	15.704
From	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Gali_15_s0
To	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/seam_cnt_1_s1
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
2.271	2.271	tNET	RR	1	R9C18[0][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Gali_15_s0/CLK
2.503	0.232	tC2Q	RF	7	R9C18[0][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Gali_15_s0/Q
4.280	1.777	tNET	FF	1	R24C22[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s120/I1
4.835	0.555	tINS	FF	4	R24C22[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s120/F
5.737	0.902	tNET	FF	1	R24C27[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s88/I3
6.307	0.570	tINS	FR	1	R24C27[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s88/F
6.451	0.144	tNET	RR	1	R24C27[2][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s40/I3
6.968	0.517	tINS	RF	1	R24C27[2][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s40/F
7.365	0.397	tNET	FF	1	R26C27[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s16/I1
7.914	0.549	tINS	FR	1	R26C27[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s16/F
7.915	0.001	tNET	RR	1	R26C27[0][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s7/I3
8.368	0.453	tINS	RF	2	R26C27[0][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s7/F
9.207	0.839	tNET	FF	1	R26C33[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1912_s2/I0
9.669	0.462	tINS	FR	3	R26C33[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1912_s2/F
9.846	0.177	tNET	RR	1	R26C34[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1911_s1/I0
10.308	0.462	tINS	RR	1	R26C34[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1911_s1/F
10.308	0.000	tNET	RR	1	R26C34[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/seam_cnt_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.468	13.468					active clock edge time
13.468	0.000					rx0_pclk
13.468	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
15.739	2.271	tNET	RR	1	R26C34[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/seam_cnt_1_s1/CLK
15.704	-0.035	tSu		1	R26C34[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/seam_cnt_1_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.468
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.568, 44.397%; route: 4.237, 52.717%; tC2Q: 0.232, 2.887%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path10

Path Summary:

Slack	5.438
Data Arrival Time	10.266
Data Required Time	15.704
From	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_1_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
2.271	2.271	tNET	RR	1	R18C32[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_1_s0/CLK
2.503	0.232	tC2Q	RF	7	R18C32[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_1_s0/Q
2.939	0.436	tNET	FF	1	R18C34[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n688_s1/I1
3.488	0.549	tINS	FR	4	R18C34[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n688_s1/F
3.667	0.178	tNET	RR	1	R17C34[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n683_s2/I3
4.120	0.453	tINS	RF	3	R17C34[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n683_s2/F
4.697	0.578	tNET	FF	1	R18C35[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s16/I3
5.068	0.371	tINS	FF	5	R18C35[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s16/F
5.501	0.432	tNET	FF	1	R17C36[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15/I2
6.056	0.555	tINS	FF	5	R17C36[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15/F
7.210	1.155	tNET	FF	2	R20C39[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n237_s5/I1
7.581	0.371	tINS	FF	1	R20C39[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n237_s5/COUT
7.581	0.000	tNET	FF	2	R20C39[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n236_s4/CIN
8.051	0.470	tINS	FF	1	R20C39[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n236_s4/SUM
8.707	0.656	tNET	FF	1	R18C36[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n603_s6/I3
9.078	0.371	tINS	FF	1	R18C36[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n603_s6/F
9.083	0.004	tNET	FF	1	R18C36[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n603_s3/I0
9.545	0.462	tINS	FR	1	R18C36[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n603_s3/F
9.717	0.172	tNET	RR	1	R17C36[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n603_s1/I1
10.266	0.549	tINS	RR	1	R17C36[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n603_s1/F
10.266	0.000	tNET	RR	1	R17C36[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.468	13.468					active clock edge time
13.468	0.000					rx0_pclk
13.468	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
15.739	2.271	tNET	RR	1	R17C36[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0/CLK
15.704	-0.035	tSu		1	R17C36[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.468
Logic Level	10
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 4.151, 51.921%; route: 3.612, 45.178%; tC2Q: 0.232, 2.902%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path11

Path Summary:

Slack	5.450
Data Arrival Time	10.254
Data Required Time	15.704
From	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Gali_15_s0
To	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_0_s1
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
2.271	2.271	tNET	RR	1	R9C18[0][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Gali_15_s0/CLK
2.503	0.232	tC2Q	RF	7	R9C18[0][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Gali_15_s0/Q
4.280	1.777	tNET	FF	1	R24C22[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s120/I1
4.835	0.555	tINS	FF	4	R24C22[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s120/F
5.737	0.902	tNET	FF	1	R24C27[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s88/I3
6.307	0.570	tINS	FR	1	R24C27[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s88/F
6.451	0.144	tNET	RR	1	R24C27[2][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s40/I3
6.968	0.517	tINS	RF	1	R24C27[2][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s40/F
7.365	0.397	tNET	FF	1	R26C27[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s16/I1
7.914	0.549	tINS	FR	1	R26C27[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s16/F
7.915	0.001	tNET	RR	1	R26C27[0][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s7/I3
8.368	0.453	tINS	RF	2	R26C27[0][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s7/F
8.980	0.612	tNET	FF	1	R26C33[2][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s4/I0
9.529	0.549	tINS	FR	2	R26C33[2][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s4/F
9.705	0.176	tNET	RR	1	R25C33[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s2/I2
10.254	0.549	tINS	RR	1	R25C33[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s2/F
10.254	0.000	tNET	RR	1	R25C33[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.468	13.468					active clock edge time
13.468	0.000					rx0_pclk
13.468	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
15.739	2.271	tNET	RR	1	R25C33[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_0_s1/CLK
15.704	-0.035	tSu		1	R25C33[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_0_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.468
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.742, 46.876%; route: 4.009, 50.218%; tC2Q: 0.232, 2.906%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path12

Path Summary:

Slack	5.491
Data Arrival Time	10.214
Data Required Time	15.704
From	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Gali_15_s0
To	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/seam_cnt_2_s1
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
2.271	2.271	tNET	RR	1	R9C18[0][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Gali_15_s0/CLK
2.503	0.232	tC2Q	RF	7	R9C18[0][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Gali_15_s0/Q
4.280	1.777	tNET	FF	1	R24C22[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s120/I1
4.835	0.555	tINS	FF	4	R24C22[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s120/F
5.737	0.902	tNET	FF	1	R24C27[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s88/I3
6.307	0.570	tINS	FR	1	R24C27[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s88/F
6.451	0.144	tNET	RR	1	R24C27[2][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s40/I3
6.968	0.517	tINS	RF	1	R24C27[2][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s40/F
7.365	0.397	tNET	FF	1	R26C27[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s16/I1
7.914	0.549	tINS	FR	1	R26C27[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s16/F
7.915	0.001	tNET	RR	1	R26C27[0][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s7/I3
8.368	0.453	tINS	RF	2	R26C27[0][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s7/F
9.207	0.839	tNET	FF	1	R26C33[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1912_s2/I0
9.669	0.462	tINS	FR	3	R26C33[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1912_s2/F
9.843	0.174	tNET	RR	1	R26C34[0][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1910_s1/I0
10.214	0.371	tINS	RF	1	R26C34[0][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1910_s1/F
10.214	0.000	tNET	FF	1	R26C34[0][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/seam_cnt_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.468	13.468					active clock edge time
13.468	0.000					rx0_pclk
13.468	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
15.739	2.271	tNET	RR	1	R26C34[0][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/seam_cnt_2_s1/CLK
15.704	-0.035	tSu		1	R26C34[0][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/seam_cnt_2_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.468
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.477, 43.777%; route: 4.233, 53.302%; tC2Q: 0.232, 2.921%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path13

Path Summary:

Slack	5.665
Data Arrival Time	10.039
Data Required Time	15.704
From	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_1_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
2.271	2.271	tNET	RR	1	R18C32[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_1_s0/CLK
2.503	0.232	tC2Q	RF	7	R18C32[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_1_s0/Q
2.939	0.436	tNET	FF	1	R18C34[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n688_s1/I1
3.488	0.549	tINS	FR	4	R18C34[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n688_s1/F
3.667	0.178	tNET	RR	1	R17C34[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n683_s2/I3
4.120	0.453	tINS	RF	3	R17C34[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n683_s2/F
4.697	0.578	tNET	FF	1	R18C35[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s16/I3
5.068	0.371	tINS	FF	5	R18C35[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s16/F
5.252	0.184	tNET	FF	1	R17C35[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s20/I3
5.769	0.517	tINS	FF	4	R17C35[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s20/F
6.922	1.153	tNET	FF	2	R20C39[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n238_s5/I1
7.293	0.371	tINS	FF	1	R20C39[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n238_s5/COUT
7.293	0.000	tNET	FF	2	R20C39[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n237_s5/CIN
7.763	0.470	tINS	FF	2	R20C39[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n237_s5/SUM
8.501	0.738	tNET	FF	1	R18C36[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n604_s3/I1
9.056	0.555	tINS	FF	1	R18C36[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n604_s3/F
9.469	0.413	tNET	FF	1	R17C37[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n604_s1/I1
10.039	0.570	tINS	FR	1	R17C37[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n604_s1/F
10.039	0.000	tNET	RR	1	R17C37[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.468	13.468					active clock edge time
13.468	0.000					rx0_pclk
13.468	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
15.739	2.271	tNET	RR	1	R17C37[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0/CLK
15.704	-0.035	tSu		1	R17C37[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.468
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.856, 49.639%; route: 3.680, 47.375%; tC2Q: 0.232, 2.987%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path14

Path Summary:

Slack	6.029
Data Arrival Time	9.675
Data Required Time	15.704
From	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Gali_11_s0
To	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s1
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
2.271	2.271	tNET	RR	1	R8C18[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Gali_11_s0/CLK
2.503	0.232	tC2Q	RF	13	R8C18[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Gali_11_s0/Q
4.782	2.279	tNET	FF	1	R24C25[2][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s122/I0
5.352	0.570	tINS	FR	4	R24C25[2][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s122/F
5.497	0.146	tNET	RR	1	R24C25[0][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s97/I3
6.052	0.555	tINS	RF	2	R24C25[0][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s97/F
6.979	0.927	tNET	FF	1	R27C30[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s47/I0
7.350	0.371	tINS	FF	1	R27C30[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s47/F
7.521	0.170	tNET	FF	1	R27C31[2][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s18/I2
7.892	0.371	tINS	FF	1	R27C31[2][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s18/F
8.062	0.170	tNET	FF	1	R26C31[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s8/I1
8.579	0.517	tINS	FF	3	R26C31[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1941_s8/F
8.838	0.259	tNET	FF	1	R26C33[2][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1938_s6/I1
9.209	0.371	tINS	FF	1	R26C33[2][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1938_s6/F
9.213	0.004	tNET	FF	1	R26C33[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1938_s3/I2
9.675	0.462	tINS	FR	1	R26C33[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n1938_s3/F
9.675	0.000	tNET	RR	1	R26C33[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.468	13.468					active clock edge time
13.468	0.000					rx0_pclk
13.468	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
15.739	2.271	tNET	RR	1	R26C33[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s1/CLK
15.704	-0.035	tSu		1	R26C33[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_cnt_3_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.468
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.217, 43.451%; route: 3.955, 53.415%; tC2Q: 0.232, 3.134%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path15

Path Summary:

Slack	6.144
Data Arrival Time	9.561
Data Required Time	15.704
From	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
2.271	2.271	tNET	RR	1	R20C25[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/CLK
2.503	0.232	tC2Q	RF	6	R20C25[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/Q
3.009	0.506	tNET	FF	1	R17C25[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n683_s3/I1
3.579	0.570	tINS	FR	2	R17C25[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n683_s3/F
3.755	0.176	tNET	RR	1	R18C25[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n683_s4/I3
4.272	0.517	tINS	RF	5	R18C25[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n683_s4/F
4.850	0.578	tNET	FF	1	R17C27[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s21/I1
5.312	0.462	tINS	FR	3	R17C27[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s21/F
5.489	0.177	tNET	RR	1	R17C28[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s14/I2
5.860	0.371	tINS	RF	4	R17C28[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s14/F
6.527	0.667	tNET	FF	2	R18C31[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n560_s0/I1
6.898	0.371	tINS	FF	1	R18C31[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n560_s0/COUT
6.898	0.000	tNET	FF	2	R18C31[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n559_s0/CIN
7.368	0.470	tINS	FF	2	R18C31[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n559_s0/SUM
7.548	0.179	tNET	FF	1	R18C30[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n603_s7/I3
8.118	0.570	tINS	FR	1	R18C30[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n603_s7/F
8.290	0.172	tNET	RR	1	R18C29[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n603_s2/I0
8.839	0.549	tINS	RR	1	R18C29[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n603_s2/F
9.012	0.172	tNET	RR	1	R17C29[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n603_s1/I0
9.561	0.549	tINS	RR	1	R17C29[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n603_s1/F
9.561	0.000	tNET	RR	1	R17C29[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.468	13.468					active clock edge time
13.468	0.000					rx0_pclk
13.468	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
15.739	2.271	tNET	RR	1	R17C29[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0/CLK
15.704	-0.035	tSu		1	R17C29[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.468
Logic Level	10
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 4.429, 60.761%; route: 2.628, 36.056%; tC2Q: 0.232, 3.183%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path16

Path Summary:

Slack	6.172
Data Arrival Time	9.532
Data Required Time	15.704
From	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_2_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_3_s0
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
2.271	2.271	tNET	RR	1	R18C20[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_2_s0/CLK
2.503	0.232	tC2Q	RF	5	R18C20[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_2_s0/Q
3.182	0.679	tNET	FF	1	R17C17[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s4/I0
3.737	0.555	tINS	FF	4	R17C17[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s4/F
4.390	0.653	tNET	FF	1	R18C18[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s2/I2
4.939	0.549	tINS	FR	3	R18C18[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s2/F
4.942	0.003	tNET	RR	1	R18C18[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s15/I3
5.459	0.517	tINS	RF	5	R18C18[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s15/F
5.706	0.247	tNET	FF	1	R18C19[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s21/I0
6.159	0.453	tINS	FF	4	R18C19[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s21/F
7.312	1.153	tNET	FF	2	R17C23[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n134_s/I1
7.683	0.371	tINS	FF	1	R17C23[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n134_s/COUT
7.683	0.000	tNET	FF	2	R17C23[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n133_s/CIN
8.153	0.470	tINS	FF	2	R17C23[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n133_s/SUM
8.328	0.175	tNET	FF	1	R17C24[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n604_s3/I0
8.790	0.462	tINS	FR	1	R17C24[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n604_s3/F
8.962	0.172	tNET	RR	1	R18C24[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n604_s1/I1
9.532	0.570	tINS	RR	1	R18C24[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n604_s1/F
9.532	0.000	tNET	RR	1	R18C24[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.468	13.468					active clock edge time
13.468	0.000					rx0_pclk
13.468	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
15.739	2.271	tNET	RR	1	R18C24[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_3_s0/CLK
15.704	-0.035	tSu		1	R18C24[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.468
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.947, 54.360%; route: 3.082, 42.444%; tC2Q: 0.232, 3.195%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path17

Path Summary:

Slack	6.495
Data Arrival Time	9.209
Data Required Time	15.704
From	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_2_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_2_s0
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
2.271	2.271	tNET	RR	1	R18C20[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_2_s0/CLK
2.503	0.232	tC2Q	RF	5	R18C20[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_2_s0/Q
3.182	0.679	tNET	FF	1	R17C17[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s4/I0
3.737	0.555	tINS	FF	4	R17C17[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s4/F
4.390	0.653	tNET	FF	1	R18C18[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s2/I2
4.939	0.549	tINS	FR	3	R18C18[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s2/F
4.942	0.003	tNET	RR	1	R18C18[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s15/I3
5.459	0.517	tINS	RF	5	R18C18[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s15/F
5.706	0.247	tNET	FF	1	R18C19[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s21/I0
6.159	0.453	tINS	FF	4	R18C19[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s21/F
7.312	1.153	tNET	FF	2	R17C23[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n134_s/I1
7.683	0.371	tINS	FF	1	R17C23[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n134_s/SUM
7.687	0.004	tNET	FF	1	R17C23[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n605_s3/I0
8.242	0.555	tINS	FF	1	R17C23[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n605_s3/F
8.639	0.397	tNET	FF	1	R17C21[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n605_s1/I1
9.209	0.570	tINS	FR	1	R17C21[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n605_s1/F
9.209	0.000	tNET	RR	1	R17C21[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.468	13.468					active clock edge time
13.468	0.000					rx0_pclk
13.468	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
15.739	2.271	tNET	RR	1	R17C21[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_2_s0/CLK
15.704	-0.035	tSu		1	R17C21[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.468
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.570, 51.457%; route: 3.136, 45.199%; tC2Q: 0.232, 3.344%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path18

Path Summary:

Slack	6.549
Data Arrival Time	9.155
Data Required Time	15.704
From	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_2_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_1_s0
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
2.271	2.271	tNET	RR	1	R18C20[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_2_s0/CLK
2.503	0.232	tC2Q	RF	5	R18C20[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_2_s0/Q
3.182	0.679	tNET	FF	1	R17C17[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s4/I0
3.737	0.555	tINS	FF	4	R17C17[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s4/F
4.390	0.653	tNET	FF	1	R18C18[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s2/I2
4.939	0.549	tINS	FR	3	R18C18[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s2/F
4.942	0.003	tNET	RR	1	R18C18[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s15/I3
5.459	0.517	tINS	RF	5	R18C18[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s15/F
6.118	0.659	tNET	FF	1	R17C20[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n630_s2/I2
6.688	0.570	tINS	FR	2	R17C20[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n630_s2/F
6.864	0.176	tNET	RR	1	R17C21[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n653_s0/I1
7.317	0.453	tINS	RF	8	R17C21[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n653_s0/F
7.740	0.423	tNET	FF	1	R18C22[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n596_s0/I2
8.193	0.453	tINS	FF	1	R18C22[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n596_s0/F
8.606	0.413	tNET	FF	1	R17C21[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n606_s2/I1
9.155	0.549	tINS	FR	1	R17C21[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n606_s2/F
9.155	0.000	tNET	RR	1	R17C21[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.468	13.468					active clock edge time
13.468	0.000					rx0_pclk
13.468	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
15.739	2.271	tNET	RR	1	R17C21[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_1_s0/CLK
15.704	-0.035	tSu		1	R17C21[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.468
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.646, 52.966%; route: 3.006, 43.664%; tC2Q: 0.232, 3.370%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path19

Path Summary:

Slack	6.623
Data Arrival Time	9.082
Data Required Time	15.704
From	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_3_s0
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
2.271	2.271	tNET	RR	1	R20C25[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/CLK
2.503	0.232	tC2Q	RF	6	R20C25[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/Q
3.009	0.506	tNET	FF	1	R17C25[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n683_s3/I1
3.579	0.570	tINS	FR	2	R17C25[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n683_s3/F
3.755	0.176	tNET	RR	1	R18C25[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n683_s4/I3
4.272	0.517	tINS	RF	5	R18C25[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n683_s4/F
4.850	0.578	tNET	FF	1	R17C27[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s21/I1
5.312	0.462	tINS	FR	3	R17C27[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s21/F
5.489	0.177	tNET	RR	1	R17C28[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s14/I2
5.860	0.371	tINS	RF	4	R17C28[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s14/F
6.527	0.667	tNET	FF	2	R18C31[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n560_s0/I1
6.898	0.371	tINS	FF	1	R18C31[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n560_s0/COUT
6.898	0.000	tNET	FF	2	R18C31[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n559_s0/CIN
7.368	0.470	tINS	FF	2	R18C31[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n559_s0/SUM
7.790	0.422	tNET	FF	1	R18C28[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n604_s2/I1
8.339	0.549	tINS	FR	1	R18C28[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n604_s2/F
8.512	0.172	tNET	RR	1	R17C28[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n604_s1/I0
9.082	0.570	tINS	RR	1	R17C28[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n604_s1/F
9.082	0.000	tNET	RR	1	R17C28[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.468	13.468					active clock edge time
13.468	0.000					rx0_pclk
13.468	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
15.739	2.271	tNET	RR	1	R17C28[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_3_s0/CLK
15.704	-0.035	tSu		1	R17C28[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.468
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.880, 56.971%; route: 2.698, 39.622%; tC2Q: 0.232, 3.407%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path20

Path Summary:

Slack	6.646
Data Arrival Time	9.059
Data Required Time	15.704
From	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_1_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_2_s0
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
2.271	2.271	tNET	RR	1	R18C32[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_1_s0/CLK
2.503	0.232	tC2Q	RF	7	R18C32[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_1_s0/Q
2.939	0.436	tNET	FF	1	R18C34[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n688_s1/I1
3.488	0.549	tINS	FR	4	R18C34[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n688_s1/F
3.667	0.178	tNET	RR	1	R17C34[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n683_s2/I3
4.120	0.453	tINS	RF	3	R17C34[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n683_s2/F
4.697	0.578	tNET	FF	1	R18C35[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s16/I3
5.068	0.371	tINS	FF	5	R18C35[3][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s16/F
5.252	0.184	tNET	FF	1	R17C35[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s20/I3
5.769	0.517	tINS	FF	4	R17C35[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s20/F
6.922	1.153	tNET	FF	2	R20C39[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n238_s5/I1
7.293	0.371	tINS	FF	3	R20C39[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n238_s5/SUM
7.938	0.645	tNET	FF	1	R18C37[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n605_s3/I1
8.487	0.549	tINS	FR	1	R18C37[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n605_s3/F
8.489	0.001	tNET	RR	1	R18C37[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n605_s1/I1
9.059	0.570	tINS	RR	1	R18C37[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n605_s1/F
9.059	0.000	tNET	RR	1	R18C37[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.468	13.468					active clock edge time
13.468	0.000					rx0_pclk
13.468	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
15.739	2.271	tNET	RR	1	R18C37[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_2_s0/CLK
15.704	-0.035	tSu		1	R18C37[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.468
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.380, 49.798%; route: 3.175, 46.784%; tC2Q: 0.232, 3.418%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path21

Path Summary:

Slack	6.782
Data Arrival Time	8.922
Data Required Time	15.704
From	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_1_s1
To	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_7_s3
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
2.271	2.271	tNET	RR	1	R29C28[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_1_s1/CLK
2.503	0.232	tC2Q	RF	24	R29C28[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_1_s1/Q
3.581	1.078	tNET	FF	1	R25C26[2][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2727_s9/I3
4.034	0.453	tINS	FF	34	R25C26[2][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2727_s9/F
6.451	2.417	tNET	FF	1	R30C25[0][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2726_s2/I3
7.006	0.555	tINS	FF	18	R30C25[0][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2726_s2/F
8.352	1.346	tNET	FF	1	R22C28[2][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2719_s5/I2
8.922	0.570	tINS	FR	1	R22C28[2][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2719_s5/F
8.922	0.000	tNET	RR	1	R22C28[2][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_7_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.468	13.468					active clock edge time
13.468	0.000					rx0_pclk
13.468	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
15.739	2.271	tNET	RR	1	R22C28[2][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_7_s3/CLK
15.704	-0.035	tSu		1	R22C28[2][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_7_s3

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.468
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 1.578, 23.726%; route: 4.841, 72.786%; tC2Q: 0.232, 3.488%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path22

Path Summary:

Slack	6.855
Data Arrival Time	8.849
Data Required Time	15.704
From	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_2_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_1_s0
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
2.271	2.271	tNET	RR	1	R18C20[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_2_s0/CLK
2.503	0.232	tC2Q	RF	5	R18C20[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_2_s0/Q
3.182	0.679	tNET	FF	1	R17C17[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s4/I0
3.737	0.555	tINS	FF	4	R17C17[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s4/F
4.390	0.653	tNET	FF	1	R18C18[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s2/I2
4.939	0.549	tINS	FR	3	R18C18[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n683_s2/F
4.942	0.003	tNET	RR	1	R18C18[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s15/I3
5.459	0.517	tINS	RF	5	R18C18[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_1_s15/F
6.118	0.659	tNET	FF	1	R17C20[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n630_s2/I2
6.688	0.570	tINS	FR	2	R17C20[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n630_s2/F
6.864	0.176	tNET	RR	1	R17C21[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n653_s0/I1
7.317	0.453	tINS	RF	8	R17C21[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n653_s0/F
7.755	0.438	tNET	FF	1	R17C19[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n682_s1/I2
8.126	0.371	tINS	FF	2	R17C19[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n682_s1/F
8.300	0.175	tNET	FF	1	R17C18[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n688_s0/I2
8.849	0.549	tINS	FR	1	R17C18[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n688_s0/F
8.849	0.000	tNET	RR	1	R17C18[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.468	13.468					active clock edge time
13.468	0.000					rx0_pclk
13.468	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
15.739	2.271	tNET	RR	1	R17C18[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_1_s0/CLK
15.704	-0.035	tSu		1	R17C18[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/dout_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.468
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.564, 54.180%; route: 2.782, 42.293%; tC2Q: 0.232, 3.527%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path23

Path Summary:

Slack	6.887
Data Arrival Time	8.818
Data Required Time	15.704
From	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/search_dog_cnt_1_s0
To	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/search_dog_cnt_29_s0
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
2.271	2.271	tNET	RR	1	R24C17[2][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/search_dog_cnt_1_s0/CLK
2.503	0.232	tC2Q	RF	4	R24C17[2][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/search_dog_cnt_1_s0/Q
2.671	0.168	tNET	FF	1	R24C17[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n362_s2/I0
3.188	0.517	tINS	FF	2	R24C17[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n362_s2/F
3.591	0.403	tNET	FF	1	R26C17[2][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n359_s2/I3
3.962	0.371	tINS	FF	3	R26C17[2][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n359_s2/F
4.386	0.425	tNET	FF	1	R29C17[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n357_s2/I2
4.757	0.371	tINS	FF	4	R29C17[3][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n357_s2/F
5.176	0.419	tNET	FF	1	R26C17[3][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n352_s2/I1
5.693	0.517	tINS	FF	8	R26C17[3][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n352_s2/F
6.522	0.829	tNET	FF	1	R31C17[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n342_s2/I0
7.077	0.555	tINS	FF	3	R31C17[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n342_s2/F
7.486	0.408	tNET	FF	1	R33C17[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n337_s2/I2
8.041	0.555	tINS	FF	4	R33C17[1][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n337_s2/F
8.447	0.406	tNET	FF	1	R32C17[2][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n336_s1/I1
8.818	0.371	tINS	FF	1	R32C17[2][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n336_s1/F
8.818	0.000	tNET	FF	1	R32C17[2][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/search_dog_cnt_29_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.468	13.468					active clock edge time
13.468	0.000					rx0_pclk
13.468	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
15.739	2.271	tNET	RR	1	R32C17[2][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/search_dog_cnt_29_s0/CLK
15.704	-0.035	tSu		1	R32C17[2][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/search_dog_cnt_29_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.468
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.257, 49.754%; route: 3.057, 46.702%; tC2Q: 0.232, 3.544%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path24

Path Summary:

Slack	6.932
Data Arrival Time	8.772
Data Required Time	15.704
From	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_1_s1
To	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_17_s1
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
2.271	2.271	tNET	RR	1	R29C28[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_1_s1/CLK
2.503	0.232	tC2Q	RF	24	R29C28[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_1_s1/Q
3.581	1.078	tNET	FF	1	R25C26[2][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2727_s9/I3
4.034	0.453	tINS	FF	34	R25C26[2][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2727_s9/F
6.451	2.417	tNET	FF	1	R30C25[0][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2726_s2/I3
7.006	0.555	tINS	FF	18	R30C25[0][B]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2726_s2/F
8.202	1.196	tNET	FF	1	R22C28[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2709_s1/I3
8.772	0.570	tINS	FR	1	R22C28[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2709_s1/F
8.772	0.000	tNET	RR	1	R22C28[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_17_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.468	13.468					active clock edge time
13.468	0.000					rx0_pclk
13.468	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
15.739	2.271	tNET	RR	1	R22C28[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_17_s1/CLK
15.704	-0.035	tSu		1	R22C28[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_17_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.468
Logic Level	4
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 1.578, 24.273%; route: 4.691, 72.159%; tC2Q: 0.232, 3.569%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path25

Path Summary:

Slack	6.939
Data Arrival Time	8.766
Data Required Time	15.704
From	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_5_s0
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
2.271	2.271	tNET	RR	1	R20C25[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/CLK
2.503	0.232	tC2Q	RF	6	R20C25[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_3_s0/Q
3.009	0.506	tNET	FF	1	R17C25[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n683_s3/I1
3.579	0.570	tINS	FR	2	R17C25[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n683_s3/F
3.755	0.176	tNET	RR	1	R18C25[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n683_s4/I3
4.272	0.517	tINS	RF	5	R18C25[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n683_s4/F
4.700	0.428	tNET	FF	1	R17C26[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n630_s4/I1
5.249	0.549	tINS	FR	1	R17C26[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n630_s4/F
5.250	0.001	tNET	RR	1	R17C26[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n630_s1/I0
5.767	0.517	tINS	RF	2	R17C26[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n630_s1/F
6.172	0.405	tNET	FF	1	R17C28[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n653_s0/I3
6.634	0.462	tINS	FR	7	R17C28[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n653_s0/F
6.811	0.177	tNET	RR	1	R17C27[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n680_s1/I2
7.366	0.555	tINS	RF	6	R17C27[3][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n680_s1/F
8.196	0.830	tNET	FF	1	R18C25[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n684_s0/I1
8.766	0.570	tINS	FR	1	R18C25[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n684_s0/F
8.766	0.000	tNET	RR	1	R18C25[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.468	13.468					active clock edge time
13.468	0.000					rx0_pclk
13.468	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
15.739	2.271	tNET	RR	1	R18C25[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_5_s0/CLK
15.704	-0.035	tSu		1	R18C25[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.468
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 3.740, 57.589%; route: 2.522, 38.838%; tC2Q: 0.232, 3.572%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.205
Data Arrival Time	3.226
Data Required Time	3.021
From	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_7_s0
To	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/sdpb_inst_0
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOR27[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	97	IOR27[A]	I_clk_ibuf/O
2.903	1.511	tNET	RR	1	R29C35[2][A]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_7_s0/CLK
3.104	0.201	tC2Q	RF	1	R29C35[2][A]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_7_s0/Q
3.226	0.122	tNET	FF	1	BSRAM_R28[9]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/sdpb_inst_0/ADB[10]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOR27[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	97	IOR27[A]	I_clk_ibuf/O
2.903	1.511	tNET	RR	1	BSRAM_R28[9]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/sdpb_inst_0/CLKB
3.021	0.118	tHld		1	BSRAM_R28[9]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/sdpb_inst_0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path2

Path Summary:

Slack	0.205
Data Arrival Time	3.226
Data Required Time	3.021
From	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_3_s0
To	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/sdpb_inst_0
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOR27[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	97	IOR27[A]	I_clk_ibuf/O
2.903	1.511	tNET	RR	1	R29C35[0][B]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_3_s0/CLK
3.104	0.201	tC2Q	RF	1	R29C35[0][B]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_3_s0/Q
3.226	0.122	tNET	FF	1	BSRAM_R28[9]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/sdpb_inst_0/ADB[6]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOR27[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	97	IOR27[A]	I_clk_ibuf/O
2.903	1.511	tNET	RR	1	BSRAM_R28[9]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/sdpb_inst_0/CLKB
3.021	0.118	tHld		1	BSRAM_R28[9]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/sdpb_inst_0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path3

Path Summary:

Slack	0.324
Data Arrival Time	3.239
Data Required Time	2.914
From	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/wre_reg_s0
To	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/rom_out_reg_4_s0
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOR27[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	97	IOR27[A]	I_clk_ibuf/O
2.903	1.511	tNET	RR	1	R25C36[2][A]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/wre_reg_s0/CLK
3.105	0.202	tC2Q	RR	8	R25C36[2][A]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/wre_reg_s0/Q
3.239	0.133	tNET	RR	1	R25C36[1][B]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/rom_out_reg_4_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOR27[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	97	IOR27[A]	I_clk_ibuf/O
2.903	1.511	tNET	RR	1	R25C36[1][B]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/rom_out_reg_4_s0/CLK
2.914	0.011	tHld		1	R25C36[1][B]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/rom_out_reg_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.133, 39.771%; tC2Q: 0.202, 60.229%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path4

Path Summary:

Slack	0.324
Data Arrival Time	3.239
Data Required Time	2.914
From	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/wre_reg_s0
To	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/rom_out_reg_5_s0
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOR27[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	97	IOR27[A]	I_clk_ibuf/O
2.903	1.511	tNET	RR	1	R25C36[2][A]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/wre_reg_s0/CLK
3.105	0.202	tC2Q	RR	8	R25C36[2][A]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/wre_reg_s0/Q
3.239	0.133	tNET	RR	1	R25C36[1][A]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/rom_out_reg_5_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOR27[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	97	IOR27[A]	I_clk_ibuf/O
2.903	1.511	tNET	RR	1	R25C36[1][A]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/rom_out_reg_5_s0/CLK
2.914	0.011	tHld		1	R25C36[1][A]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/rom_out_reg_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.133, 39.771%; tC2Q: 0.202, 60.229%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path5

Path Summary:

Slack	0.324
Data Arrival Time	3.239
Data Required Time	2.914
From	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/wre_reg_s0
To	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/rom_out_reg_7_s0
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOR27[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	97	IOR27[A]	I_clk_ibuf/O
2.903	1.511	tNET	RR	1	R25C36[2][A]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/wre_reg_s0/CLK
3.105	0.202	tC2Q	RR	8	R25C36[2][A]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/wre_reg_s0/Q
3.239	0.133	tNET	RR	1	R25C36[0][A]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/rom_out_reg_7_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOR27[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	97	IOR27[A]	I_clk_ibuf/O
2.903	1.511	tNET	RR	1	R25C36[0][A]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/rom_out_reg_7_s0/CLK
2.914	0.011	tHld		1	R25C36[0][A]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/rom_out_reg_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.133, 39.771%; tC2Q: 0.202, 60.229%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path6

Path Summary:

Slack	0.329
Data Arrival Time	3.350
Data Required Time	3.021
From	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_0_s0
To	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/sdpb_inst_0
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOR27[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	97	IOR27[A]	I_clk_ibuf/O
2.903	1.511	tNET	RR	1	R29C35[2][B]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_0_s0/CLK
3.105	0.202	tC2Q	RR	1	R29C35[2][B]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_0_s0/Q
3.350	0.245	tNET	RR	1	BSRAM_R28[9]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/sdpb_inst_0/ADB[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOR27[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	97	IOR27[A]	I_clk_ibuf/O
2.903	1.511	tNET	RR	1	BSRAM_R28[9]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/sdpb_inst_0/CLKB
3.021	0.118	tHld		1	BSRAM_R28[9]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/sdpb_inst_0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.245, 54.832%; tC2Q: 0.202, 45.168%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path7

Path Summary:

Slack	0.333
Data Arrival Time	3.354
Data Required Time	3.021
From	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_5_s0
To	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/sdpb_inst_0
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOR27[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	97	IOR27[A]	I_clk_ibuf/O
2.903	1.511	tNET	RR	1	R29C35[1][A]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_5_s0/CLK
3.105	0.202	tC2Q	RR	1	R29C35[1][A]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_5_s0/Q
3.354	0.249	tNET	RR	1	BSRAM_R28[9]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/sdpb_inst_0/ADB[8]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOR27[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	97	IOR27[A]	I_clk_ibuf/O
2.903	1.511	tNET	RR	1	BSRAM_R28[9]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/sdpb_inst_0/CLKB
3.021	0.118	tHld		1	BSRAM_R28[9]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/sdpb_inst_0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.249, 55.230%; tC2Q: 0.202, 44.770%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path8

Path Summary:

Slack	0.344
Data Arrival Time	3.366
Data Required Time	3.021
From	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_6_s0
To	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/sdpb_inst_0
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOR27[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	97	IOR27[A]	I_clk_ibuf/O
2.903	1.511	tNET	RR	1	R29C35[1][B]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_6_s0/CLK
3.105	0.202	tC2Q	RR	1	R29C35[1][B]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_6_s0/Q
3.366	0.260	tNET	RR	1	BSRAM_R28[9]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/sdpb_inst_0/ADB[9]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOR27[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	97	IOR27[A]	I_clk_ibuf/O
2.903	1.511	tNET	RR	1	BSRAM_R28[9]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/sdpb_inst_0/CLKB
3.021	0.118	tHld		1	BSRAM_R28[9]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/sdpb_inst_0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path9

Path Summary:

Slack	0.344
Data Arrival Time	3.366
Data Required Time	3.021
From	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_4_s0
To	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/sdpb_inst_0
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOR27[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	97	IOR27[A]	I_clk_ibuf/O
2.903	1.511	tNET	RR	1	R29C36[0][A]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_4_s0/CLK
3.105	0.202	tC2Q	RR	1	R29C36[0][A]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_4_s0/Q
3.366	0.260	tNET	RR	1	BSRAM_R28[9]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/sdpb_inst_0/ADB[7]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOR27[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	97	IOR27[A]	I_clk_ibuf/O
2.903	1.511	tNET	RR	1	BSRAM_R28[9]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/sdpb_inst_0/CLKB
3.021	0.118	tHld		1	BSRAM_R28[9]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/sdpb_inst_0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path10

Path Summary:

Slack	0.344
Data Arrival Time	3.366
Data Required Time	3.021
From	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_2_s0
To	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/sdpb_inst_0
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOR27[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	97	IOR27[A]	I_clk_ibuf/O
2.903	1.511	tNET	RR	1	R29C35[0][A]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_2_s0/CLK
3.105	0.202	tC2Q	RR	1	R29C35[0][A]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_2_s0/Q
3.366	0.260	tNET	RR	1	BSRAM_R28[9]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/sdpb_inst_0/ADB[5]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOR27[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	97	IOR27[A]	I_clk_ibuf/O
2.903	1.511	tNET	RR	1	BSRAM_R28[9]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/sdpb_inst_0/CLKB
3.021	0.118	tHld		1	BSRAM_R28[9]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/sdpb_inst_0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path11

Path Summary:

Slack	0.344
Data Arrival Time	3.366
Data Required Time	3.021
From	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_1_s0
To	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/sdpb_inst_0
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOR27[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	97	IOR27[A]	I_clk_ibuf/O
2.903	1.511	tNET	RR	1	R27C35[0][A]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_1_s0/CLK
3.105	0.202	tC2Q	RR	1	R27C35[0][A]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/u_i2c_slave/ad_reg_1_s0/Q
3.366	0.260	tNET	RR	1	BSRAM_R28[9]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/sdpb_inst_0/ADB[4]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOR27[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	97	IOR27[A]	I_clk_ibuf/O
2.903	1.511	tNET	RR	1	BSRAM_R28[9]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/sdpb_inst_0/CLKB
3.021	0.118	tHld		1	BSRAM_R28[9]	EDID_PROM_Top_inst/i2c_slave_wrapper_inst/sdpb_inst_0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay	cell: 1.392, 47.946%; route: 1.511, 52.054%

Path12

Path Summary:

Slack	0.425
Data Arrival Time	4.738
Data Required Time	4.313
From	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_8_s0
To	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_8_s0
Launch Clk	I_tmds_clk_p:[R]
Latch Clk	I_tmds_clk_p:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_tmds_clk_p
0.000	0.000	tCL	RR	1	IOT22	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I
1.922	1.922	tINS	RR	14	IOT22	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O
4.302	2.380	tNET	RR	1	R27C26[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_8_s0/CLK
4.504	0.202	tC2Q	RR	3	R27C26[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_8_s0/Q
4.506	0.002	tNET	RR	1	R27C26[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n819_s1/I2
4.738	0.232	tINS	RF	1	R27C26[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n819_s1/F
4.738	0.000	tNET	FF	1	R27C26[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_tmds_clk_p
0.000	0.000	tCL	RR	1	IOT22	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I
1.922	1.922	tINS	RR	14	IOT22	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O
4.302	2.380	tNET	RR	1	R27C26[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_8_s0/CLK
4.313	0.011	tHld		1	R27C26[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_8_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.922, 44.686%; route: 2.380, 55.314%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 1.922, 44.686%; route: 2.380, 55.314%

Path13

Path Summary:

Slack	0.425
Data Arrival Time	1.948
Data Required Time	1.522
From	DVI_RX_Top_inst/dvi2rgb_inst/u_tmds_b/ctrl1_s4
To	DVI_RX_Top_inst/dvi2rgb_inst/u_tmds_b/ctrl1_s4
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
1.511	1.511	tNET	RR	1	R21C19[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_tmds_b/ctrl1_s4/CLK
1.713	0.202	tC2Q	RR	2	R21C19[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_tmds_b/ctrl1_s4/Q
1.716	0.002	tNET	RR	1	R21C19[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_tmds_b/n80_s4/I0
1.948	0.232	tINS	RF	1	R21C19[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_tmds_b/n80_s4/F
1.948	0.000	tNET	FF	1	R21C19[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_tmds_b/ctrl1_s4/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
1.511	1.511	tNET	RR	1	R21C19[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_tmds_b/ctrl1_s4/CLK
1.522	0.011	tHld		1	R21C19[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_tmds_b/ctrl1_s4

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path14

Path Summary:

Slack	0.425
Data Arrival Time	1.948
Data Required Time	1.522
From	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_11_s3
To	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_11_s3
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
1.511	1.511	tNET	RR	1	R24C27[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_11_s3/CLK
1.713	0.202	tC2Q	RR	5	R24C27[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_11_s3/Q
1.716	0.002	tNET	RR	1	R24C27[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2715_s5/I3
1.948	0.232	tINS	RF	1	R24C27[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2715_s5/F
1.948	0.000	tNET	FF	1	R24C27[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_11_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
1.511	1.511	tNET	RR	1	R24C27[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_11_s3/CLK
1.522	0.011	tHld		1	R24C27[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_11_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path15

Path Summary:

Slack	0.425
Data Arrival Time	1.948
Data Required Time	1.522
From	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_16_s3
To	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_16_s3
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
1.511	1.511	tNET	RR	1	R22C27[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_16_s3/CLK
1.713	0.202	tC2Q	RR	3	R22C27[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_16_s3/Q
1.716	0.002	tNET	RR	1	R22C27[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2710_s4/I3
1.948	0.232	tINS	RF	1	R22C27[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2710_s4/F
1.948	0.000	tNET	FF	1	R22C27[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_16_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
1.511	1.511	tNET	RR	1	R22C27[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_16_s3/CLK
1.522	0.011	tHld		1	R22C27[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_16_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path16

Path Summary:

Slack	0.425
Data Arrival Time	1.948
Data Required Time	1.522
From	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/r_chk_cnt_0_s3
To	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/r_chk_cnt_0_s3
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
1.511	1.511	tNET	RR	1	R32C23[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/r_chk_cnt_0_s3/CLK
1.713	0.202	tC2Q	RR	5	R32C23[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/r_chk_cnt_0_s3/Q
1.716	0.002	tNET	RR	1	R32C23[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2430_s3/I2
1.948	0.232	tINS	RF	1	R32C23[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2430_s3/F
1.948	0.000	tNET	FF	1	R32C23[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/r_chk_cnt_0_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
1.511	1.511	tNET	RR	1	R32C23[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/r_chk_cnt_0_s3/CLK
1.522	0.011	tHld		1	R32C23[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/r_chk_cnt_0_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path17

Path Summary:

Slack	0.425
Data Arrival Time	1.948
Data Required Time	1.522
From	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/phase_lock_s3
To	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/phase_lock_s3
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
1.511	1.511	tNET	RR	1	R32C33[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/phase_lock_s3/CLK
1.713	0.202	tC2Q	RR	2	R32C33[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/phase_lock_s3/Q
1.716	0.002	tNET	RR	1	R32C33[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n781_s4/I0
1.948	0.232	tINS	RF	1	R32C33[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n781_s4/F
1.948	0.000	tNET	FF	1	R32C33[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/phase_lock_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
1.511	1.511	tNET	RR	1	R32C33[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/phase_lock_s3/CLK
1.522	0.011	tHld		1	R32C33[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/phase_lock_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path18

Path Summary:

Slack	0.425
Data Arrival Time	1.948
Data Required Time	1.522
From	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_17_s1
To	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_17_s1
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
1.511	1.511	tNET	RR	1	R22C28[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_17_s1/CLK
1.713	0.202	tC2Q	RR	2	R22C28[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_17_s1/Q
1.716	0.002	tNET	RR	1	R22C28[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2709_s1/I2
1.948	0.232	tINS	RF	1	R22C28[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2709_s1/F
1.948	0.000	tNET	FF	1	R22C28[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_17_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
1.511	1.511	tNET	RR	1	R22C28[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_17_s1/CLK
1.522	0.011	tHld		1	R22C28[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/lock_lost_cnt_17_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path19

Path Summary:

Slack	0.425
Data Arrival Time	1.948
Data Required Time	1.522
From	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/r_chk_cnt_1_s1
To	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/r_chk_cnt_1_s1
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
1.511	1.511	tNET	RR	1	R32C23[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/r_chk_cnt_1_s1/CLK
1.713	0.202	tC2Q	RR	4	R32C23[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/r_chk_cnt_1_s1/Q
1.716	0.002	tNET	RR	1	R32C23[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2429_s1/I0
1.948	0.232	tINS	RF	1	R32C23[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2429_s1/F
1.948	0.000	tNET	FF	1	R32C23[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/r_chk_cnt_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
1.511	1.511	tNET	RR	1	R32C23[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/r_chk_cnt_1_s1/CLK
1.522	0.011	tHld		1	R32C23[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/r_chk_cnt_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path20

Path Summary:

Slack	0.425
Data Arrival Time	1.948
Data Required Time	1.522
From	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/r_code_clk_cnt_6_s1
To	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/r_code_clk_cnt_6_s1
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
1.511	1.511	tNET	RR	1	R31C19[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/r_code_clk_cnt_6_s1/CLK
1.713	0.202	tC2Q	RR	4	R31C19[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/r_code_clk_cnt_6_s1/Q
1.716	0.002	tNET	RR	1	R31C19[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2371_s2/I0
1.948	0.232	tINS	RF	1	R31C19[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2371_s2/F
1.948	0.000	tNET	FF	1	R31C19[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/r_code_clk_cnt_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
1.511	1.511	tNET	RR	1	R31C19[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/r_code_clk_cnt_6_s1/CLK
1.522	0.011	tHld		1	R31C19[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/r_code_clk_cnt_6_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path21

Path Summary:

Slack	0.425
Data Arrival Time	1.948
Data Required Time	1.522
From	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_chk_cnt_0_s1
To	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_chk_cnt_0_s1
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
1.511	1.511	tNET	RR	1	R33C27[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_chk_cnt_0_s1/CLK
1.713	0.202	tC2Q	RR	4	R33C27[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_chk_cnt_0_s1/Q
1.716	0.002	tNET	RR	1	R33C27[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2146_s1/I0
1.948	0.232	tINS	RF	1	R33C27[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2146_s1/F
1.948	0.000	tNET	FF	1	R33C27[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_chk_cnt_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
1.511	1.511	tNET	RR	1	R33C27[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_chk_cnt_0_s1/CLK
1.522	0.011	tHld		1	R33C27[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_chk_cnt_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path22

Path Summary:

Slack	0.425
Data Arrival Time	1.948
Data Required Time	1.522
From	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_chk_cnt_2_s1
To	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_chk_cnt_2_s1
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
1.511	1.511	tNET	RR	1	R33C27[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_chk_cnt_2_s1/CLK
1.713	0.202	tC2Q	RR	2	R33C27[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_chk_cnt_2_s1/Q
1.716	0.002	tNET	RR	1	R33C27[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2144_s1/I2
1.948	0.232	tINS	RF	1	R33C27[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2144_s1/F
1.948	0.000	tNET	FF	1	R33C27[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_chk_cnt_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
1.511	1.511	tNET	RR	1	R33C27[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_chk_cnt_2_s1/CLK
1.522	0.011	tHld		1	R33C27[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_chk_cnt_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path23

Path Summary:

Slack	0.425
Data Arrival Time	1.948
Data Required Time	1.522
From	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_code_clk_cnt_3_s1
To	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_code_clk_cnt_3_s1
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
1.511	1.511	tNET	RR	1	R33C26[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_code_clk_cnt_3_s1/CLK
1.713	0.202	tC2Q	RR	3	R33C26[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_code_clk_cnt_3_s1/Q
1.716	0.002	tNET	RR	1	R33C26[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2090_s1/I2
1.948	0.232	tINS	RF	1	R33C26[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2090_s1/F
1.948	0.000	tNET	FF	1	R33C26[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_code_clk_cnt_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
1.511	1.511	tNET	RR	1	R33C26[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_code_clk_cnt_3_s1/CLK
1.522	0.011	tHld		1	R33C26[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_code_clk_cnt_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path24

Path Summary:

Slack	0.425
Data Arrival Time	1.948
Data Required Time	1.522
From	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_code_clk_cnt_5_s1
To	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_code_clk_cnt_5_s1
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
1.511	1.511	tNET	RR	1	R33C26[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_code_clk_cnt_5_s1/CLK
1.713	0.202	tC2Q	RR	4	R33C26[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_code_clk_cnt_5_s1/Q
1.716	0.002	tNET	RR	1	R33C26[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2088_s1/I2
1.948	0.232	tINS	RF	1	R33C26[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2088_s1/F
1.948	0.000	tNET	FF	1	R33C26[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_code_clk_cnt_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
1.511	1.511	tNET	RR	1	R33C26[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_code_clk_cnt_5_s1/CLK
1.522	0.011	tHld		1	R33C26[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_code_clk_cnt_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path25

Path Summary:

Slack	0.425
Data Arrival Time	1.948
Data Required Time	1.522
From	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_code_clk_cnt_6_s1
To	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_code_clk_cnt_6_s1
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
1.511	1.511	tNET	RR	1	R33C28[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_code_clk_cnt_6_s1/CLK
1.713	0.202	tC2Q	RR	3	R33C28[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_code_clk_cnt_6_s1/Q
1.716	0.002	tNET	RR	1	R33C28[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2087_s3/I0
1.948	0.232	tINS	RF	1	R33C28[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2087_s3/F
1.948	0.000	tNET	FF	1	R33C28[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_code_clk_cnt_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
1.511	1.511	tNET	RR	1	R33C28[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_code_clk_cnt_6_s1/CLK
1.522	0.011	tHld		1	R33C28[1][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_code_clk_cnt_6_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	10.795
Data Arrival Time	4.827
Data Required Time	15.622
From	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/ides10_rst_s0
To	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_R_DATA
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
2.271	2.271	tNET	RR	1	R29C26[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/ides10_rst_s0/CLK
2.503	0.232	tC2Q	RF	1	R29C26[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/ides10_rst_s0/Q
3.186	0.683	tNET	FF	1	R18C26[3][B]	DVI_RX_Top_inst/dvi2rgb_inst/n36_s1/I0
3.741	0.555	tINS	FF	3	R18C26[3][B]	DVI_RX_Top_inst/dvi2rgb_inst/n36_s1/F
4.827	1.086	tNET	FF	10	IOT4[A]	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_R_DATA/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.468	13.468					active clock edge time
13.468	0.000					rx0_pclk
13.468	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
15.739	2.271	tNET	RR	1	IOT4[A]	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_R_DATA/PCLK
15.622	-0.117	tSu		1	IOT4[A]	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_R_DATA

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.468
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 0.555, 21.716%; route: 1.769, 69.207%; tC2Q: 0.232, 9.077%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path2

Path Summary:

Slack	10.795
Data Arrival Time	4.827
Data Required Time	15.622
From	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/ides10_rst_s0
To	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_G_DATA
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
2.271	2.271	tNET	RR	1	R29C26[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/ides10_rst_s0/CLK
2.503	0.232	tC2Q	RF	1	R29C26[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/ides10_rst_s0/Q
3.186	0.683	tNET	FF	1	R18C26[3][B]	DVI_RX_Top_inst/dvi2rgb_inst/n36_s1/I0
3.741	0.555	tINS	FF	3	R18C26[3][B]	DVI_RX_Top_inst/dvi2rgb_inst/n36_s1/F
4.827	1.086	tNET	FF	10	IOT2[A]	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_G_DATA/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.468	13.468					active clock edge time
13.468	0.000					rx0_pclk
13.468	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
15.739	2.271	tNET	RR	1	IOT2[A]	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_G_DATA/PCLK
15.622	-0.117	tSu		1	IOT2[A]	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_G_DATA

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.468
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 0.555, 21.716%; route: 1.769, 69.207%; tC2Q: 0.232, 9.077%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Path3

Path Summary:

Slack	10.795
Data Arrival Time	4.827
Data Required Time	15.622
From	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/ides10_rst_s0
To	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_B_DATA
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
2.271	2.271	tNET	RR	1	R29C26[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/ides10_rst_s0/CLK
2.503	0.232	tC2Q	RF	1	R29C26[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/ides10_rst_s0/Q
3.186	0.683	tNET	FF	1	R18C26[3][B]	DVI_RX_Top_inst/dvi2rgb_inst/n36_s1/I0
3.741	0.555	tINS	FF	3	R18C26[3][B]	DVI_RX_Top_inst/dvi2rgb_inst/n36_s1/F
4.827	1.086	tNET	FF	10	IOT16[A]	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_B_DATA/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
13.468	13.468					active clock edge time
13.468	0.000					rx0_pclk
13.468	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
15.739	2.271	tNET	RR	1	IOT16[A]	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_B_DATA/PCLK
15.622	-0.117	tSu		1	IOT16[A]	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_B_DATA

Path Statistics:

Clock Skew	0.000
Setup Relationship	13.468
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%
Arrival Data Path Delay	cell: 0.555, 21.716%; route: 1.769, 69.207%; tC2Q: 0.232, 9.077%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 2.271, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	1.626
Data Arrival Time	3.248
Data Required Time	1.621
From	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/ides10_rst_s0
To	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_R_DATA
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
1.511	1.511	tNET	RR	1	R29C26[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/ides10_rst_s0/CLK
1.713	0.202	tC2Q	RR	1	R29C26[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/ides10_rst_s0/Q
2.123	0.410	tNET	RR	1	R18C26[3][B]	DVI_RX_Top_inst/dvi2rgb_inst/n36_s1/I0
2.514	0.391	tINS	RR	3	R18C26[3][B]	DVI_RX_Top_inst/dvi2rgb_inst/n36_s1/F
3.248	0.734	tNET	RR	10	IOT4[A]	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_R_DATA/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
1.511	1.511	tNET	RR	1	IOT4[A]	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_R_DATA/PCLK
1.621	0.110	tHld		1	IOT4[A]	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_R_DATA

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.391, 22.518%; route: 1.143, 65.849%; tC2Q: 0.202, 11.633%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path2

Path Summary:

Slack	1.626
Data Arrival Time	3.248
Data Required Time	1.621
From	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/ides10_rst_s0
To	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_G_DATA
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
1.511	1.511	tNET	RR	1	R29C26[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/ides10_rst_s0/CLK
1.713	0.202	tC2Q	RR	1	R29C26[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/ides10_rst_s0/Q
2.123	0.410	tNET	RR	1	R18C26[3][B]	DVI_RX_Top_inst/dvi2rgb_inst/n36_s1/I0
2.514	0.391	tINS	RR	3	R18C26[3][B]	DVI_RX_Top_inst/dvi2rgb_inst/n36_s1/F
3.248	0.734	tNET	RR	10	IOT2[A]	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_G_DATA/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
1.511	1.511	tNET	RR	1	IOT2[A]	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_G_DATA/PCLK
1.621	0.110	tHld		1	IOT2[A]	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_G_DATA

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.391, 22.518%; route: 1.143, 65.849%; tC2Q: 0.202, 11.633%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Path3

Path Summary:

Slack	1.626
Data Arrival Time	3.248
Data Required Time	1.621
From	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/ides10_rst_s0
To	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_B_DATA
Launch Clk	rx0_pclk:[R]
Latch Clk	rx0_pclk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
1.511	1.511	tNET	RR	1	R29C26[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/ides10_rst_s0/CLK
1.713	0.202	tC2Q	RR	1	R29C26[0][A]	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/ides10_rst_s0/Q
2.123	0.410	tNET	RR	1	R18C26[3][B]	DVI_RX_Top_inst/dvi2rgb_inst/n36_s1/I0
2.514	0.391	tINS	RR	3	R18C26[3][B]	DVI_RX_Top_inst/dvi2rgb_inst/n36_s1/F
3.248	0.734	tNET	RR	10	IOT16[A]	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_B_DATA/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					rx0_pclk
0.000	0.000	tCL	RR	462	TOPSIDE[0]	DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
1.511	1.511	tNET	RR	1	IOT16[A]	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_B_DATA/PCLK
1.621	0.110	tHld		1	IOT16[A]	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_B_DATA

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%
Arrival Data Path Delay	cell: 0.391, 22.518%; route: 1.143, 65.849%; tC2Q: 0.202, 11.633%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 1.511, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	3.675
Actual Width:	4.675
Required Width:	1.000
Type:	Low Pulse Width
Clock:	I_tmds_clk_p
Objects:	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_11_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.734	0.000			active clock edge time
6.734	0.000			I_tmds_clk_p
6.734	0.000	tCL	FF	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I
9.223	2.489	tINS	FF	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O
13.095	3.872	tNET	FF	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_11_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
13.468	0.000			active clock edge time
13.468	0.000			I_tmds_clk_p
13.468	0.000	tCL	RR	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I
15.390	1.922	tINS	RR	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O
17.770	2.380	tNET	RR	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_11_s0/CLK

MPW2

MPW Summary:

Slack:	3.675
Actual Width:	4.675
Required Width:	1.000
Type:	Low Pulse Width
Clock:	I_tmds_clk_p
Objects:	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_10_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.734	0.000			active clock edge time
6.734	0.000			I_tmds_clk_p
6.734	0.000	tCL	FF	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I
9.223	2.489	tINS	FF	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O
13.095	3.872	tNET	FF	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_10_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
13.468	0.000			active clock edge time
13.468	0.000			I_tmds_clk_p
13.468	0.000	tCL	RR	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I
15.390	1.922	tINS	RR	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O
17.770	2.380	tNET	RR	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_10_s0/CLK

MPW3

MPW Summary:

Slack:	3.675
Actual Width:	4.675
Required Width:	1.000
Type:	Low Pulse Width
Clock:	I_tmds_clk_p
Objects:	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_9_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.734	0.000			active clock edge time
6.734	0.000			I_tmds_clk_p
6.734	0.000	tCL	FF	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I
9.223	2.489	tINS	FF	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O
13.095	3.872	tNET	FF	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_9_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
13.468	0.000			active clock edge time
13.468	0.000			I_tmds_clk_p
13.468	0.000	tCL	RR	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I
15.390	1.922	tINS	RR	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O
17.770	2.380	tNET	RR	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_9_s0/CLK

MPW4

MPW Summary:

Slack:	3.675
Actual Width:	4.675
Required Width:	1.000
Type:	Low Pulse Width
Clock:	I_tmds_clk_p
Objects:	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_8_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.734	0.000			active clock edge time
6.734	0.000			I_tmds_clk_p
6.734	0.000	tCL	FF	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I
9.223	2.489	tINS	FF	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O
13.095	3.872	tNET	FF	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_8_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
13.468	0.000			active clock edge time
13.468	0.000			I_tmds_clk_p
13.468	0.000	tCL	RR	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I
15.390	1.922	tINS	RR	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O
17.770	2.380	tNET	RR	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_8_s0/CLK

MPW5

MPW Summary:

Slack:	3.675
Actual Width:	4.675
Required Width:	1.000
Type:	Low Pulse Width
Clock:	I_tmds_clk_p
Objects:	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_7_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.734	0.000			active clock edge time
6.734	0.000			I_tmds_clk_p
6.734	0.000	tCL	FF	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I
9.223	2.489	tINS	FF	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O
13.095	3.872	tNET	FF	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_7_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
13.468	0.000			active clock edge time
13.468	0.000			I_tmds_clk_p
13.468	0.000	tCL	RR	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I
15.390	1.922	tINS	RR	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O
17.770	2.380	tNET	RR	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_7_s0/CLK

MPW6

MPW Summary:

Slack:	3.675
Actual Width:	4.675
Required Width:	1.000
Type:	Low Pulse Width
Clock:	I_tmds_clk_p
Objects:	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_3_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.734	0.000			active clock edge time
6.734	0.000			I_tmds_clk_p
6.734	0.000	tCL	FF	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I
9.223	2.489	tINS	FF	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O
13.095	3.872	tNET	FF	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_3_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
13.468	0.000			active clock edge time
13.468	0.000			I_tmds_clk_p
13.468	0.000	tCL	RR	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I
15.390	1.922	tINS	RR	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O
17.770	2.380	tNET	RR	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_3_s0/CLK

MPW7

MPW Summary:

Slack:	3.675
Actual Width:	4.675
Required Width:	1.000
Type:	Low Pulse Width
Clock:	I_tmds_clk_p
Objects:	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.734	0.000			active clock edge time
6.734	0.000			I_tmds_clk_p
6.734	0.000	tCL	FF	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I
9.223	2.489	tINS	FF	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O
13.095	3.872	tNET	FF	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
13.468	0.000			active clock edge time
13.468	0.000			I_tmds_clk_p
13.468	0.000	tCL	RR	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I
15.390	1.922	tINS	RR	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O
17.770	2.380	tNET	RR	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_2_s0/CLK

MPW8

MPW Summary:

Slack:	3.675
Actual Width:	4.675
Required Width:	1.000
Type:	Low Pulse Width
Clock:	I_tmds_clk_p
Objects:	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pll_rerst_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.734	0.000			active clock edge time
6.734	0.000			I_tmds_clk_p
6.734	0.000	tCL	FF	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I
9.223	2.489	tINS	FF	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O
13.095	3.872	tNET	FF	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pll_rerst_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
13.468	0.000			active clock edge time
13.468	0.000			I_tmds_clk_p
13.468	0.000	tCL	RR	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I
15.390	1.922	tINS	RR	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O
17.770	2.380	tNET	RR	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pll_rerst_s0/CLK

MPW9

MPW Summary:

Slack:	3.675
Actual Width:	4.675
Required Width:	1.000
Type:	Low Pulse Width
Clock:	I_tmds_clk_p
Objects:	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.734	0.000			active clock edge time
6.734	0.000			I_tmds_clk_p
6.734	0.000	tCL	FF	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I
9.223	2.489	tINS	FF	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O
13.095	3.872	tNET	FF	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
13.468	0.000			active clock edge time
13.468	0.000			I_tmds_clk_p
13.468	0.000	tCL	RR	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I
15.390	1.922	tINS	RR	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O
17.770	2.380	tNET	RR	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_1_s0/CLK

MPW10

MPW Summary:

Slack:	3.675
Actual Width:	4.675
Required Width:	1.000
Type:	Low Pulse Width
Clock:	I_tmds_clk_p
Objects:	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.734	0.000			active clock edge time
6.734	0.000			I_tmds_clk_p
6.734	0.000	tCL	FF	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I
9.223	2.489	tINS	FF	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O
13.095	3.872	tNET	FF	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
13.468	0.000			active clock edge time
13.468	0.000			I_tmds_clk_p
13.468	0.000	tCL	RR	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I
15.390	1.922	tINS	RR	DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/O
17.770	2.380	tNET	RR	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/pllrst_cnt_0_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
462	rx0_pclk	4.465	2.274
97	I_clk_d	14.646	2.274
76	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_num[2]	9.327	1.365
69	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/b_chk_cnt_2_14	9.526	1.844
66	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n143_10	8.908	1.690
60	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_num[1]	10.093	1.350
59	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/align_num[0]	8.269	1.604
42	DVI_TX_Top_inst/rgb2dvi_inst/de_d	10.048	2.645
41	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n3287_4	8.503	1.563
34	DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n2727_14	6.782	2.423

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R2C2	100.00%
R2C3	100.00%
R2C5	100.00%
R2C7	100.00%
R2C8	100.00%
R2C40	100.00%
R3C50	100.00%
R6C16	100.00%
R11C37	100.00%
R21C37	100.00%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name I_tmds_clk_p -period 13.468 -waveform {0 6.734} [get_ports {I_tmds_clk_p}] -add
TC_CLOCK	Actived	create_clock -name hclkx5 -period 2.694 -waveform {0 1.347} [get_nets {DVI_RX_Top_inst/dvi2rgb_inst/hclkx5}] -add
TC_CLOCK	Actived	create_clock -name I_clk -period 20 -waveform {0 10} [get_ports {I_clk}] -add
TC_CLOCK	Actived	create_clock -name rx0_pclk -period 13.468 -waveform {0 6.734} [get_nets {rx0_pclk}] -add
TC_CLOCK_GROUP	Actived	set_clock_groups -exclusive -group [get_clocks {rx0_pclk}] -group [get_clocks {hclkx5}] -group [get_clocks {I_tmds_clk_p}]