Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\proj\Gowin_DVI_RX_RefDesign\project\src\dvi_rx\dvi_rx.v
D:\proj\Gowin_DVI_RX_RefDesign\project\src\dvi_tx\dvi_tx.v
D:\proj\Gowin_DVI_RX_RefDesign\project\src\edid_prom\edid_prom.v
D:\proj\Gowin_DVI_RX_RefDesign\project\src\gowin_rpll\TMDS_rPLL.v
D:\proj\Gowin_DVI_RX_RefDesign\project\src\video_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.12.01 (64-bit)
Part Number GW2A-LV18PG484C8/I7
Device GW2A-18
Device Version C
Created Time Fri Dec 26 16:24:10 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module video_top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.227s, Peak memory usage = 233.336MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 233.336MB
    Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.031s, Peak memory usage = 233.336MB
    Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.031s, Peak memory usage = 233.336MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.032s, Peak memory usage = 233.336MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 233.336MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 233.336MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 233.336MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 233.336MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 233.336MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 233.336MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.312s, Peak memory usage = 260.594MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.119s, Peak memory usage = 260.594MB
Generate output files:
    CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.061s, Peak memory usage = 260.594MB
Total Time and Memory Usage CPU time = 0h 0m 0.808s, Elapsed time = 0h 0m 0.885s, Peak memory usage = 260.594MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 24
I/O Buf 16
    IBUF 3
    OBUF 4
    IOBUF 1
    TLVDS_IBUF 4
    TLVDS_OBUF 4
Register 563
    DFF 2
    DFFE 24
    DFFR 3
    DFFP 7
    DFFC 382
    DFFCE 145
LUT 1289
    LUT2 185
    LUT3 405
    LUT4 699
ALU 83
    ALU 83
INV 8
    INV 8
IOLOGIC 7
    IDES10 3
    OSER10 4
BSRAM 1
    SDPB 1
CLOCK 3
    CLKDIV 1
    rPLL 2

Resource Utilization Summary

Resource Usage Utilization
Logic 1380(1297 LUT, 83 ALU) / 20736 7%
Register 563 / 16512 4%
  --Register as Latch 0 / 16512 0%
  --Register as FF 563 / 16512 4%
BSRAM 1 / 46 3%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 I_tmds_clk_p Base 13.468 74.250 0.000 6.734 DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I
2 I_clk Base 10.000 100.000 0.000 5.000 I_clk_ibuf/I
3 DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUT.default_gen_clk Generated 2.694 371.250 0.000 1.347 DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I I_tmds_clk_p DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUT
4 DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUTP.default_gen_clk Generated 2.694 371.250 0.000 1.347 DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I I_tmds_clk_p DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUTP
5 DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUTD.default_gen_clk Generated 13.468 74.250 0.000 6.734 DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I I_tmds_clk_p DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUTD
6 DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUTD3.default_gen_clk Generated 8.081 123.750 0.000 4.040 DVI_RX_Top_inst/dvi2rgb_inst/u_HDMI_CK/I I_tmds_clk_p DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUTD3
7 DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk Generated 13.468 74.250 0.000 6.734 DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUTP DVI_RX_Top_inst/dvi2rgb_inst/rPLL_inst/CLKOUTP.default_gen_clk DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
8 u_tmds_rpll/rpll_inst/CLKOUT.default_gen_clk Generated 2.694 371.250 0.000 1.347 DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk u_tmds_rpll/rpll_inst/CLKOUT
9 u_tmds_rpll/rpll_inst/CLKOUTP.default_gen_clk Generated 2.694 371.250 0.000 1.347 DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk u_tmds_rpll/rpll_inst/CLKOUTP
10 u_tmds_rpll/rpll_inst/CLKOUTD.default_gen_clk Generated 5.387 185.625 0.000 2.694 DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk u_tmds_rpll/rpll_inst/CLKOUTD
11 u_tmds_rpll/rpll_inst/CLKOUTD3.default_gen_clk Generated 8.081 123.750 0.000 4.040 DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk u_tmds_rpll/rpll_inst/CLKOUTD3

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_tmds_clk_p 74.250(MHz) 263.852(MHz) 4 TOP
2 I_clk 100.000(MHz) 176.087(MHz) 6 TOP
3 DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk 74.250(MHz) 98.765(MHz) 11 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 3.343
Data Arrival Time 10.791
Data Required Time 14.134
From DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_1_s0
To DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0
Launch Clk DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk[R]
Latch Clk DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk
0.341 0.341 tCL RR 462 DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
0.701 0.360 tNET RR 1 DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_1_s0/CLK
0.933 0.232 tC2Q RF 7 DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_1_s0/Q
1.407 0.474 tNET FF 1 DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n688_s1/I1
1.962 0.555 tINS FF 5 DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n688_s1/F
2.436 0.474 tNET FF 1 DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s13/I1
2.991 0.555 tINS FF 1 DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s13/F
3.465 0.474 tNET FF 1 DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s12/I1
4.020 0.555 tINS FF 4 DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s12/F
4.494 0.474 tNET FF 1 DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n630_s1/I2
4.947 0.453 tINS FF 3 DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n630_s1/F
5.421 0.474 tNET FF 1 DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_2_s16/I0
5.938 0.517 tINS FF 4 DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_2_s16/F
6.412 0.474 tNET FF 2 DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n237_s5/I1
6.982 0.570 tINS FR 1 DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n237_s5/COUT
6.982 0.000 tNET RR 2 DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n236_s4/CIN
7.452 0.470 tINS RF 1 DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n236_s4/SUM
7.926 0.474 tNET FF 1 DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n603_s6/I3
8.297 0.371 tINS FF 1 DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n603_s6/F
8.771 0.474 tNET FF 1 DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n603_s3/I0
9.288 0.517 tINS FF 1 DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n603_s3/F
9.762 0.474 tNET FF 1 DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n603_s1/I1
10.317 0.555 tINS FF 1 DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n603_s1/F
10.791 0.474 tNET FF 1 DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
13.468 0.000 DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk
13.809 0.341 tCL RR 462 DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
14.169 0.360 tNET RR 1 DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0/CLK
14.134 -0.035 tSu 1 DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 13.468
Logic Level: 11
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 5.118, 50.724%; route: 4.740, 46.977%; tC2Q: 0.232, 2.299%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 2

Path Summary:
Slack 3.632
Data Arrival Time 10.502
Data Required Time 14.134
From DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_10_s0
To DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_0_s1
Launch Clk DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk[R]
Latch Clk DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk
0.341 0.341 tCL RR 462 DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
0.701 0.360 tNET RR 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_10_s0/CLK
0.933 0.232 tC2Q RF 5 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_10_s0/Q
1.407 0.474 tNET FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n14_s15/I1
1.962 0.555 tINS FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n14_s15/F
2.436 0.474 tNET FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n14_s11/I1
2.991 0.555 tINS FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n14_s11/F
3.465 0.474 tNET FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n14_s8/I0
3.982 0.517 tINS FF 3 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n14_s8/F
4.456 0.474 tNET FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_next_0_s28/I1
5.011 0.555 tINS FF 2 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_next_0_s28/F
5.485 0.474 tNET FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n13_s6/I0
6.002 0.517 tINS FF 2 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n13_s6/F
6.476 0.474 tNET FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n13_s7/I1
7.031 0.555 tINS FF 2 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n13_s7/F
7.505 0.474 tNET FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_next_2_s21/I0
8.022 0.517 tINS FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_next_2_s21/F
8.496 0.474 tNET FF 2 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n9_s0/I1
9.066 0.570 tINS FR 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n9_s0/COUT
9.066 0.000 tNET RR 2 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n10_s0/CIN
9.101 0.035 tINS RF 4 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n10_s0/COUT
9.575 0.474 tNET FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n15_s0/I2
10.028 0.453 tINS FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n15_s0/F
10.502 0.474 tNET FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_0_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
13.468 0.000 DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk
13.809 0.341 tCL RR 462 DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
14.169 0.360 tNET RR 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_0_s1/CLK
14.134 -0.035 tSu 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_0_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 13.468
Logic Level: 11
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 4.829, 49.272%; route: 4.740, 48.361%; tC2Q: 0.232, 2.367%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 3

Path Summary:
Slack 3.714
Data Arrival Time 10.420
Data Required Time 14.134
From DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_10_s0
To DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_3_s1
Launch Clk DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk[R]
Latch Clk DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk
0.341 0.341 tCL RR 462 DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
0.701 0.360 tNET RR 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_10_s0/CLK
0.933 0.232 tC2Q RF 5 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_10_s0/Q
1.407 0.474 tNET FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n14_s15/I1
1.962 0.555 tINS FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n14_s15/F
2.436 0.474 tNET FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n14_s11/I1
2.991 0.555 tINS FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n14_s11/F
3.465 0.474 tNET FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n14_s8/I0
3.982 0.517 tINS FF 3 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n14_s8/F
4.456 0.474 tNET FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_next_0_s28/I1
5.011 0.555 tINS FF 2 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_next_0_s28/F
5.485 0.474 tNET FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n13_s6/I0
6.002 0.517 tINS FF 2 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n13_s6/F
6.476 0.474 tNET FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n13_s7/I1
7.031 0.555 tINS FF 2 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n13_s7/F
7.505 0.474 tNET FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_next_2_s21/I0
8.022 0.517 tINS FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_next_2_s21/F
8.496 0.474 tNET FF 2 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n9_s0/I1
9.066 0.570 tINS FR 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n9_s0/COUT
9.066 0.000 tNET RR 2 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n10_s0/CIN
9.101 0.035 tINS RF 4 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n10_s0/COUT
9.575 0.474 tNET FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n12_s0/I3
9.946 0.371 tINS FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n12_s0/F
10.420 0.474 tNET FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_3_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
13.468 0.000 DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk
13.809 0.341 tCL RR 462 DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
14.169 0.360 tNET RR 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_3_s1/CLK
14.134 -0.035 tSu 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_3_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 13.468
Logic Level: 11
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 4.747, 48.844%; route: 4.740, 48.769%; tC2Q: 0.232, 2.387%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 4

Path Summary:
Slack 3.714
Data Arrival Time 10.420
Data Required Time 14.134
From DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_10_s0
To DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_1_s1
Launch Clk DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk[R]
Latch Clk DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk
0.341 0.341 tCL RR 462 DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
0.701 0.360 tNET RR 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_10_s0/CLK
0.933 0.232 tC2Q RF 5 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_10_s0/Q
1.407 0.474 tNET FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n14_s15/I1
1.962 0.555 tINS FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n14_s15/F
2.436 0.474 tNET FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n14_s11/I1
2.991 0.555 tINS FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n14_s11/F
3.465 0.474 tNET FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n14_s8/I0
3.982 0.517 tINS FF 3 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n14_s8/F
4.456 0.474 tNET FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_next_0_s28/I1
5.011 0.555 tINS FF 2 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_next_0_s28/F
5.485 0.474 tNET FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n13_s6/I0
6.002 0.517 tINS FF 2 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n13_s6/F
6.476 0.474 tNET FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n13_s7/I1
7.031 0.555 tINS FF 2 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n13_s7/F
7.505 0.474 tNET FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_next_2_s21/I0
8.022 0.517 tINS FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_next_2_s21/F
8.496 0.474 tNET FF 2 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n9_s0/I1
9.066 0.570 tINS FR 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n9_s0/COUT
9.066 0.000 tNET RR 2 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n10_s0/CIN
9.101 0.035 tINS RF 4 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n10_s0/COUT
9.575 0.474 tNET FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n14_s0/I3
9.946 0.371 tINS FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n14_s0/F
10.420 0.474 tNET FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_1_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
13.468 0.000 DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk
13.809 0.341 tCL RR 462 DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
14.169 0.360 tNET RR 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_1_s1/CLK
14.134 -0.035 tSu 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 13.468
Logic Level: 11
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 4.747, 48.844%; route: 4.740, 48.769%; tC2Q: 0.232, 2.387%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 5

Path Summary:
Slack 3.714
Data Arrival Time 10.420
Data Required Time 14.134
From DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_10_s0
To DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_2_s1
Launch Clk DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk[R]
Latch Clk DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk
0.341 0.341 tCL RR 462 DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
0.701 0.360 tNET RR 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_10_s0/CLK
0.933 0.232 tC2Q RF 5 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/nomatch_dog_cnt_10_s0/Q
1.407 0.474 tNET FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n14_s15/I1
1.962 0.555 tINS FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n14_s15/F
2.436 0.474 tNET FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n14_s11/I1
2.991 0.555 tINS FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n14_s11/F
3.465 0.474 tNET FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n14_s8/I0
3.982 0.517 tINS FF 3 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n14_s8/F
4.456 0.474 tNET FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_next_0_s28/I1
5.011 0.555 tINS FF 2 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_next_0_s28/F
5.485 0.474 tNET FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n13_s6/I0
6.002 0.517 tINS FF 2 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n13_s6/F
6.476 0.474 tNET FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n13_s7/I1
7.031 0.555 tINS FF 2 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n13_s7/F
7.505 0.474 tNET FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_next_2_s21/I0
8.022 0.517 tINS FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_next_2_s21/F
8.496 0.474 tNET FF 2 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n9_s0/I1
9.066 0.570 tINS FR 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n9_s0/COUT
9.066 0.000 tNET RR 2 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n10_s0/CIN
9.101 0.035 tINS RF 4 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n10_s0/COUT
9.575 0.474 tNET FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n13_s0/I3
9.946 0.371 tINS FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/n13_s0/F
10.420 0.474 tNET FF 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_2_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
13.468 0.000 DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT.default_gen_clk
13.809 0.341 tCL RR 462 DVI_RX_Top_inst/dvi2rgb_inst/u_clkdiv5/CLKOUT
14.169 0.360 tNET RR 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_2_s1/CLK
14.134 -0.035 tSu 1 DVI_RX_Top_inst/dvi2rgb_inst/u_Data_Aligning_Auto/Align_sta_2_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 13.468
Logic Level: 11
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 4.747, 48.844%; route: 4.740, 48.769%; tC2Q: 0.232, 2.387%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%