Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\MIPI_BYTE_TO_PIXEL\data\byte_to_pixel.v
D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\MIPI_BYTE_TO_PIXEL\data\byte_to_pixel_wrap.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.01 (64-bit)
Part Number GW5AST-LV138FPG676AC1/I0
Device GW5AST-138
Device Version B
Created Time Wed Mar 6 18:42:25 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Byte_to_Pixel_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.307s, Peak memory usage = 116.820MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 116.820MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 116.820MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 116.820MB
    Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 116.820MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 116.820MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 116.820MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 116.820MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 116.820MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 116.820MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 116.820MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 116.820MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.515s, Elapsed time = 0h 0m 0.561s, Peak memory usage = 140.719MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.051s, Peak memory usage = 140.719MB
Generate output files:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.067s, Peak memory usage = 140.719MB
Total Time and Memory Usage CPU time = 0h 0m 0.979s, Elapsed time = 0h 0m 1s, Peak memory usage = 140.719MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 90
I/O Buf 90
    IBUF 63
    OBUF 27
Register 393
    DFFSE 2
    DFFRE 84
    DFFPE 9
    DFFCE 298
LUT 278
    LUT2 28
    LUT3 59
    LUT4 191
ALU 20
    ALU 20
INV 6
    INV 6
BSRAM 2
    SDPB 2

Resource Utilization Summary

Resource Usage Utilization
Logic 304(284 LUT, 20 ALU) / 138240 <1%
Register 393 / 139140 <1%
  --Register as Latch 0 / 139140 0%
  --Register as FF 393 / 139140 <1%
BSRAM 2 / 340 <1%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
I_BYTE_CLK Base 10.000 100.0 0.000 5.000 I_BYTE_CLK_ibuf/I
I_PIXEL_CLK Base 10.000 100.0 0.000 5.000 I_PIXEL_CLK_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_BYTE_CLK 100.000(MHz) 196.271(MHz) 6 TOP
2 I_PIXEL_CLK 100.000(MHz) 206.186(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 4.905
Data Arrival Time 6.126
Data Required Time 11.031
From u_b2p_inst/u_mid_fifo/rRPtrWsync_3_s0
To u_b2p_inst/u_mid_fifo/rFull_s0
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.683 0.683 tINS RR 315 I_BYTE_CLK_ibuf/O
1.095 0.413 tNET RR 1 u_b2p_inst/u_mid_fifo/rRPtrWsync_3_s0/CLK
1.477 0.382 tC2Q RR 1 u_b2p_inst/u_mid_fifo/rRPtrWsync_3_s0/Q
1.890 0.413 tNET RR 1 u_b2p_inst/u_mid_fifo/wRPtrBinX_3_s0/I0
2.469 0.579 tINS RR 6 u_b2p_inst/u_mid_fifo/wRPtrBinX_3_s0/F
2.881 0.413 tNET RR 1 u_b2p_inst/u_mid_fifo/wRPtrBinX_0_s1/I0
3.460 0.579 tINS RR 1 u_b2p_inst/u_mid_fifo/wRPtrBinX_0_s1/F
3.872 0.413 tNET RR 2 u_b2p_inst/u_mid_fifo/n399_s0/I1
4.472 0.600 tINS RF 1 u_b2p_inst/u_mid_fifo/n399_s0/COUT
4.472 0.000 tNET FF 2 u_b2p_inst/u_mid_fifo/n400_s0/CIN
4.523 0.050 tINS FR 1 u_b2p_inst/u_mid_fifo/n400_s0/COUT
4.523 0.000 tNET RR 2 u_b2p_inst/u_mid_fifo/n401_s0/CIN
4.573 0.050 tINS RR 1 u_b2p_inst/u_mid_fifo/n401_s0/COUT
4.573 0.000 tNET RR 2 u_b2p_inst/u_mid_fifo/n402_s0/CIN
4.623 0.050 tINS RR 1 u_b2p_inst/u_mid_fifo/n402_s0/COUT
4.623 0.000 tNET RR 2 u_b2p_inst/u_mid_fifo/n403_s0/CIN
4.673 0.050 tINS RR 1 u_b2p_inst/u_mid_fifo/n403_s0/COUT
4.673 0.000 tNET RR 2 u_b2p_inst/u_mid_fifo/n404_s0/CIN
4.723 0.050 tINS RR 1 u_b2p_inst/u_mid_fifo/n404_s0/COUT
5.135 0.413 tNET RR 1 u_b2p_inst/u_mid_fifo/n418_s0/I0
5.714 0.579 tINS RR 1 u_b2p_inst/u_mid_fifo/n418_s0/F
6.126 0.413 tNET RR 1 u_b2p_inst/u_mid_fifo/rFull_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.682 0.683 tINS RR 315 I_BYTE_CLK_ibuf/O
11.095 0.413 tNET RR 1 u_b2p_inst/u_mid_fifo/rFull_s0/CLK
11.031 -0.064 tSu 1 u_b2p_inst/u_mid_fifo/rFull_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%
Arrival Data Path Delay: cell: 2.586, 51.404%; route: 2.062, 40.994%; tC2Q: 0.382, 7.602%
Required Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%

Path 2

Path Summary:
Slack 4.940
Data Arrival Time 5.844
Data Required Time 10.784
From u_b2p_inst/wc_cnt_dec_1_s3
To u_b2p_inst/mid_offset_4_s1
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.683 0.683 tINS RR 315 I_BYTE_CLK_ibuf/O
1.095 0.413 tNET RR 1 u_b2p_inst/wc_cnt_dec_1_s3/CLK
1.477 0.382 tC2Q RR 7 u_b2p_inst/wc_cnt_dec_1_s3/Q
1.890 0.413 tNET RR 1 u_b2p_inst/n1200_s1/I0
2.469 0.579 tINS RR 2 u_b2p_inst/n1200_s1/F
2.881 0.413 tNET RR 1 u_b2p_inst/mid_offset_3_s5/I1
3.449 0.567 tINS RR 1 u_b2p_inst/mid_offset_3_s5/F
3.861 0.413 tNET RR 1 u_b2p_inst/mid_offset_3_s7/I0
4.440 0.579 tINS RR 3 u_b2p_inst/mid_offset_3_s7/F
4.852 0.413 tNET RR 1 u_b2p_inst/mid_offset_3_s3/I0
5.431 0.579 tINS RR 3 u_b2p_inst/mid_offset_3_s3/F
5.844 0.413 tNET RR 1 u_b2p_inst/mid_offset_4_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.682 0.683 tINS RR 315 I_BYTE_CLK_ibuf/O
11.095 0.413 tNET RR 1 u_b2p_inst/mid_offset_4_s1/CLK
10.784 -0.311 tSu 1 u_b2p_inst/mid_offset_4_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%
Arrival Data Path Delay: cell: 2.304, 48.513%; route: 2.062, 43.432%; tC2Q: 0.382, 8.055%
Required Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%

Path 3

Path Summary:
Slack 4.940
Data Arrival Time 5.844
Data Required Time 10.784
From u_b2p_inst/wc_cnt_dec_1_s3
To u_b2p_inst/mid_offset_2_s1
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.683 0.683 tINS RR 315 I_BYTE_CLK_ibuf/O
1.095 0.413 tNET RR 1 u_b2p_inst/wc_cnt_dec_1_s3/CLK
1.477 0.382 tC2Q RR 7 u_b2p_inst/wc_cnt_dec_1_s3/Q
1.890 0.413 tNET RR 1 u_b2p_inst/n1200_s1/I0
2.469 0.579 tINS RR 2 u_b2p_inst/n1200_s1/F
2.881 0.413 tNET RR 1 u_b2p_inst/mid_offset_3_s5/I1
3.449 0.567 tINS RR 1 u_b2p_inst/mid_offset_3_s5/F
3.861 0.413 tNET RR 1 u_b2p_inst/mid_offset_3_s7/I0
4.440 0.579 tINS RR 3 u_b2p_inst/mid_offset_3_s7/F
4.852 0.413 tNET RR 1 u_b2p_inst/mid_offset_3_s3/I0
5.431 0.579 tINS RR 3 u_b2p_inst/mid_offset_3_s3/F
5.844 0.413 tNET RR 1 u_b2p_inst/mid_offset_2_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.682 0.683 tINS RR 315 I_BYTE_CLK_ibuf/O
11.095 0.413 tNET RR 1 u_b2p_inst/mid_offset_2_s1/CLK
10.784 -0.311 tSu 1 u_b2p_inst/mid_offset_2_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%
Arrival Data Path Delay: cell: 2.304, 48.513%; route: 2.062, 43.432%; tC2Q: 0.382, 8.055%
Required Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%

Path 4

Path Summary:
Slack 4.940
Data Arrival Time 5.844
Data Required Time 10.784
From u_b2p_inst/wc_cnt_dec_1_s3
To u_b2p_inst/mid_offset_3_s1
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.683 0.683 tINS RR 315 I_BYTE_CLK_ibuf/O
1.095 0.413 tNET RR 1 u_b2p_inst/wc_cnt_dec_1_s3/CLK
1.477 0.382 tC2Q RR 7 u_b2p_inst/wc_cnt_dec_1_s3/Q
1.890 0.413 tNET RR 1 u_b2p_inst/n1200_s1/I0
2.469 0.579 tINS RR 2 u_b2p_inst/n1200_s1/F
2.881 0.413 tNET RR 1 u_b2p_inst/mid_offset_3_s5/I1
3.449 0.567 tINS RR 1 u_b2p_inst/mid_offset_3_s5/F
3.861 0.413 tNET RR 1 u_b2p_inst/mid_offset_3_s7/I0
4.440 0.579 tINS RR 3 u_b2p_inst/mid_offset_3_s7/F
4.852 0.413 tNET RR 1 u_b2p_inst/mid_offset_3_s3/I0
5.431 0.579 tINS RR 3 u_b2p_inst/mid_offset_3_s3/F
5.844 0.413 tNET RR 1 u_b2p_inst/mid_offset_3_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.682 0.683 tINS RR 315 I_BYTE_CLK_ibuf/O
11.095 0.413 tNET RR 1 u_b2p_inst/mid_offset_3_s1/CLK
10.784 -0.311 tSu 1 u_b2p_inst/mid_offset_3_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%
Arrival Data Path Delay: cell: 2.304, 48.513%; route: 2.062, 43.432%; tC2Q: 0.382, 8.055%
Required Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%

Path 5

Path Summary:
Slack 4.951
Data Arrival Time 5.832
Data Required Time 10.784
From u_b2p_inst/wc_cnt_dec_1_s3
To u_b2p_inst/mid_offset_1_s1
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.683 0.683 tINS RR 315 I_BYTE_CLK_ibuf/O
1.095 0.413 tNET RR 1 u_b2p_inst/wc_cnt_dec_1_s3/CLK
1.477 0.382 tC2Q RR 7 u_b2p_inst/wc_cnt_dec_1_s3/Q
1.890 0.413 tNET RR 1 u_b2p_inst/n1200_s1/I0
2.469 0.579 tINS RR 2 u_b2p_inst/n1200_s1/F
2.881 0.413 tNET RR 1 u_b2p_inst/mid_offset_3_s5/I1
3.449 0.567 tINS RR 1 u_b2p_inst/mid_offset_3_s5/F
3.861 0.413 tNET RR 1 u_b2p_inst/mid_offset_3_s7/I0
4.440 0.579 tINS RR 3 u_b2p_inst/mid_offset_3_s7/F
4.852 0.413 tNET RR 1 u_b2p_inst/mid_offset_1_s3/I1
5.420 0.567 tINS RR 1 u_b2p_inst/mid_offset_1_s3/F
5.832 0.413 tNET RR 1 u_b2p_inst/mid_offset_1_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 I_BYTE_CLK
10.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
10.682 0.683 tINS RR 315 I_BYTE_CLK_ibuf/O
11.095 0.413 tNET RR 1 u_b2p_inst/mid_offset_1_s1/CLK
10.784 -0.311 tSu 1 u_b2p_inst/mid_offset_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%
Arrival Data Path Delay: cell: 2.293, 48.390%; route: 2.062, 43.536%; tC2Q: 0.382, 8.074%
Required Clock Path Delay: cell: 0.683, 62.329%; route: 0.413, 37.671%