Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_2a18\fpga_proj\src\byte_to_pixel\byte_to_pixel.v F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_2a18\fpga_proj\src\dpi_extractor.v F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_2a18\fpga_proj\src\dsi_rx\dsi_rx_top.v F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_2a18\fpga_proj\src\gowin_rpll_m49d5\gowin_rpll.v F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_2a18\fpga_proj\src\gowin_rpll_m4d3\gowin_rpll.v F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_2a18\fpga_proj\src\lvds_tx\ip_gddr71tx.v F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_2a18\fpga_proj\src\lvds_tx\lvds_7_to_1_tx.v F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_2a18\fpga_proj\src\mipi_rx_phy\mipi_rx_phy.v F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_to_LVDS_2a18\fpga_proj\src\top.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.9.01 (64-bit) |
| Part Number | GW2A-LV18PG256C8/I7 |
| Device | GW2A-18 |
| Device Version | C |
| Created Time | Wed Mar 6 18:46:30 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | Dsi2Lvds_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.313s, Peak memory usage = 602.793MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 602.793MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 602.793MB Optimizing Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.069s, Peak memory usage = 602.793MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 602.793MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 602.793MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 602.793MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 602.793MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.051s, Peak memory usage = 602.793MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 602.793MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 602.793MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.418s, Peak memory usage = 602.793MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.08s, Peak memory usage = 602.793MB Generate output files: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.132s, Peak memory usage = 602.793MB |
| Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 602.793MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 24 |
| I/O Buf | 14 |
| IBUF | 4 |
| TLVDS_IBUF | 5 |
| TLVDS_OBUF | 5 |
| Register | 1333 |
| DFF | 66 |
| DFFE | 136 |
| DFFS | 34 |
| DFFSE | 2 |
| DFFR | 38 |
| DFFRE | 136 |
| DFFP | 3 |
| DFFPE | 7 |
| DFFC | 561 |
| DFFCE | 350 |
| LUT | 1201 |
| LUT2 | 101 |
| LUT3 | 302 |
| LUT4 | 798 |
| ALU | 48 |
| ALU | 48 |
| SSRAM | 12 |
| RAM16SDP4 | 12 |
| INV | 15 |
| INV | 15 |
| IOLOGIC | 13 |
| IDES8 | 4 |
| OVIDEO | 5 |
| IODELAY | 4 |
| BSRAM | 12 |
| SDPB | 12 |
| CLOCK | 6 |
| CLKDIV | 2 |
| DHCEN | 2 |
| rPLL | 2 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 1336(1216 LUT, 48 ALU, 12 RAM16) / 20736 | 7% |
| Register | 1333 / 16173 | 9% |
| --Register as Latch | 0 / 16173 | 0% |
| --Register as FF | 1333 / 16173 | 9% |
| BSRAM | 12 / 46 | 27% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| HS_CLK_P | Base | 2.381 | 420.0 | 0.000 | 1.190 | u_mipi_dphy/DPHY_RX_INST/U0_IB/I | ||
| OSC_50M | Base | 20.000 | 50.0 | 0.000 | 10.000 | OSC_50M_ibuf/I | ||
| u_pll_2/rpll_inst/CLKOUT.default_gen_clk | Generated | 2.041 | 490.0 | 0.000 | 1.020 | OSC_50M_ibuf/I | OSC_50M | u_pll_2/rpll_inst/CLKOUT |
| u_pll_2/rpll_inst/CLKOUTP.default_gen_clk | Generated | 2.041 | 490.0 | 0.000 | 1.020 | OSC_50M_ibuf/I | OSC_50M | u_pll_2/rpll_inst/CLKOUTP |
| u_pll_2/rpll_inst/CLKOUTD.default_gen_clk | Generated | 4.082 | 245.0 | 0.000 | 2.041 | OSC_50M_ibuf/I | OSC_50M | u_pll_2/rpll_inst/CLKOUTD |
| u_pll_2/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 6.122 | 163.3 | 0.000 | 3.061 | OSC_50M_ibuf/I | OSC_50M | u_pll_2/rpll_inst/CLKOUTD3 |
| u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT.default_gen_clk | Generated | 9.524 | 105.0 | 0.000 | 4.762 | u_mipi_dphy/DPHY_RX_INST/U0_IB/I | HS_CLK_P | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
| u_clk_div_3p5/CLKOUT.default_gen_clk | Generated | 7.143 | 140.0 | 0.000 | 3.571 | u_pll_2/rpll_inst/CLKOUT | u_pll_2/rpll_inst/CLKOUT.default_gen_clk | u_clk_div_3p5/CLKOUT |
| u_pll_1/rpll_inst/CLKOUT.default_gen_clk | Generated | 7.143 | 140.0 | 0.000 | 3.571 | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT.default_gen_clk | u_pll_1/rpll_inst/CLKOUT |
| u_pll_1/rpll_inst/CLKOUTP.default_gen_clk | Generated | 7.143 | 140.0 | 0.000 | 3.571 | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT.default_gen_clk | u_pll_1/rpll_inst/CLKOUTP |
| u_pll_1/rpll_inst/CLKOUTD.default_gen_clk | Generated | 14.286 | 70.0 | 0.000 | 7.143 | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT.default_gen_clk | u_pll_1/rpll_inst/CLKOUTD |
| u_pll_1/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 21.429 | 46.7 | 0.000 | 10.714 | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT.default_gen_clk | u_pll_1/rpll_inst/CLKOUTD3 |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | HS_CLK_P | 420.000(MHz) | 294.118(MHz) | 2 | TOP |
| 2 | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT.default_gen_clk | 105.000(MHz) | 169.895(MHz) | 6 | TOP |
| 3 | u_clk_div_3p5/CLKOUT.default_gen_clk | 140.000(MHz) | 207.512(MHz) | 5 | TOP |
| 4 | u_pll_1/rpll_inst/CLKOUT.default_gen_clk | 140.000(MHz) | 207.995(MHz) | 6 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -0.510 |
| Data Arrival Time | 2.675 |
| Data Required Time | 2.166 |
| From | u_mipi_dphy/DPHY_RX_INST/u_idesx8/opensync_1_s0 |
| To | u_mipi_dphy/DPHY_RX_INST/u_idesx8/u_DHCEN |
| Launch Clk | HS_CLK_P[F] |
| Latch Clk | HS_CLK_P[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | HS_CLK_P | |||
| 0.000 | 0.000 | tCL | RR | 1 | u_mipi_dphy/DPHY_RX_INST/U0_IB/I |
| 0.683 | 0.683 | tINS | RR | 5 | u_mipi_dphy/DPHY_RX_INST/U0_IB/O |
| 1.043 | 0.360 | tNET | RR | 1 | u_mipi_dphy/DPHY_RX_INST/u_idesx8/opensync_1_s0/CLK |
| 1.275 | 0.232 | tC2Q | RF | 2 | u_mipi_dphy/DPHY_RX_INST/u_idesx8/opensync_1_s0/Q |
| 1.748 | 0.474 | tNET | FF | 1 | u_mipi_dphy/DPHY_RX_INST/u_idesx8/LUT4_0/I2 |
| 2.201 | 0.453 | tINS | FF | 1 | u_mipi_dphy/DPHY_RX_INST/u_idesx8/LUT4_0/F |
| 2.675 | 0.474 | tNET | FF | 1 | u_mipi_dphy/DPHY_RX_INST/u_idesx8/u_DHCEN/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 1.190 | 0.000 | HS_CLK_P | |||
| 1.190 | 0.000 | tCL | FF | 1 | u_mipi_dphy/DPHY_RX_INST/U0_IB/I |
| 1.878 | 0.688 | tINS | FF | 5 | u_mipi_dphy/DPHY_RX_INST/U0_IB/O |
| 2.352 | 0.474 | tNET | FF | 3 | u_mipi_dphy/DPHY_RX_INST/u_idesx8/u_DHCEN/CLKIN |
| 2.166 | -0.186 | tSu | 1 | u_mipi_dphy/DPHY_RX_INST/u_idesx8/u_DHCEN |
| Clock Skew: | 0.119 |
| Setup Relationship: | 1.190 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
| Arrival Data Path Delay: | cell: 0.453, 27.740%; route: 0.948, 58.053%; tC2Q: 0.232, 14.207% |
| Required Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
Path 2
Path Summary:| Slack | 0.085 |
| Data Arrival Time | 22.475 |
| Data Required Time | 22.559 |
| From | u_b2p/u_b2p_inst/rByteCtrl_0_s0 |
| To | u_b2p/u_b2p_inst/u_hs_adj/rSCnt_2_s1 |
| Launch Clk | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_pll_1/rpll_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 19.048 | 0.000 | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT.default_gen_clk | |||
| 19.389 | 0.341 | tCL | RR | 1041 | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
| 19.749 | 0.360 | tNET | RR | 1 | u_b2p/u_b2p_inst/rByteCtrl_0_s0/CLK |
| 19.981 | 0.232 | tC2Q | RF | 11 | u_b2p/u_b2p_inst/rByteCtrl_0_s0/Q |
| 20.455 | 0.474 | tNET | FF | 1 | u_b2p/u_b2p_inst/u_hs_adj/rWCnt_9_s4/I1 |
| 21.010 | 0.555 | tINS | FF | 11 | u_b2p/u_b2p_inst/u_hs_adj/rWCnt_9_s4/F |
| 21.484 | 0.474 | tNET | FF | 1 | u_b2p/u_b2p_inst/u_hs_adj/n69_s2/I0 |
| 22.001 | 0.517 | tINS | FF | 1 | u_b2p/u_b2p_inst/u_hs_adj/n69_s2/F |
| 22.475 | 0.474 | tNET | FF | 1 | u_b2p/u_b2p_inst/u_hs_adj/rSCnt_2_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 21.429 | 0.000 | u_pll_1/rpll_inst/CLKOUT.default_gen_clk | |||
| 22.269 | 0.841 | tCL | RR | 214 | u_pll_1/rpll_inst/CLKOUT |
| 22.629 | 0.360 | tNET | RR | 1 | u_b2p/u_b2p_inst/u_hs_adj/rSCnt_2_s1/CLK |
| 22.594 | -0.035 | tUnc | u_b2p/u_b2p_inst/u_hs_adj/rSCnt_2_s1 | ||
| 22.559 | -0.035 | tSu | 1 | u_b2p/u_b2p_inst/u_hs_adj/rSCnt_2_s1 |
| Clock Skew: | 0.500 |
| Setup Relationship: | 2.381 |
| Logic Level: | 3 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 1.072, 39.325%; route: 1.422, 52.164%; tC2Q: 0.232, 8.511% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 3
Path Summary:| Slack | 0.085 |
| Data Arrival Time | 22.475 |
| Data Required Time | 22.559 |
| From | u_b2p/u_b2p_inst/rByteCtrl_0_s0 |
| To | u_b2p/u_b2p_inst/u_hs_adj/rWCnt_2_s1 |
| Launch Clk | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_pll_1/rpll_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 19.048 | 0.000 | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT.default_gen_clk | |||
| 19.389 | 0.341 | tCL | RR | 1041 | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
| 19.749 | 0.360 | tNET | RR | 1 | u_b2p/u_b2p_inst/rByteCtrl_0_s0/CLK |
| 19.981 | 0.232 | tC2Q | RF | 11 | u_b2p/u_b2p_inst/rByteCtrl_0_s0/Q |
| 20.455 | 0.474 | tNET | FF | 1 | u_b2p/u_b2p_inst/u_hs_adj/rWCnt_9_s4/I1 |
| 21.010 | 0.555 | tINS | FF | 11 | u_b2p/u_b2p_inst/u_hs_adj/rWCnt_9_s4/F |
| 21.484 | 0.474 | tNET | FF | 1 | u_b2p/u_b2p_inst/u_hs_adj/n31_s2/I0 |
| 22.001 | 0.517 | tINS | FF | 1 | u_b2p/u_b2p_inst/u_hs_adj/n31_s2/F |
| 22.475 | 0.474 | tNET | FF | 1 | u_b2p/u_b2p_inst/u_hs_adj/rWCnt_2_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 21.429 | 0.000 | u_pll_1/rpll_inst/CLKOUT.default_gen_clk | |||
| 22.269 | 0.841 | tCL | RR | 214 | u_pll_1/rpll_inst/CLKOUT |
| 22.629 | 0.360 | tNET | RR | 1 | u_b2p/u_b2p_inst/u_hs_adj/rWCnt_2_s1/CLK |
| 22.594 | -0.035 | tUnc | u_b2p/u_b2p_inst/u_hs_adj/rWCnt_2_s1 | ||
| 22.559 | -0.035 | tSu | 1 | u_b2p/u_b2p_inst/u_hs_adj/rWCnt_2_s1 |
| Clock Skew: | 0.500 |
| Setup Relationship: | 2.381 |
| Logic Level: | 3 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 1.072, 39.325%; route: 1.422, 52.164%; tC2Q: 0.232, 8.511% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 4
Path Summary:| Slack | 0.149 |
| Data Arrival Time | 22.411 |
| Data Required Time | 22.559 |
| From | u_b2p/u_b2p_inst/rByteCtrl_0_s0 |
| To | u_b2p/u_b2p_inst/u_hs_adj/rSCnt_3_s1 |
| Launch Clk | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_pll_1/rpll_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 19.048 | 0.000 | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT.default_gen_clk | |||
| 19.389 | 0.341 | tCL | RR | 1041 | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
| 19.749 | 0.360 | tNET | RR | 1 | u_b2p/u_b2p_inst/rByteCtrl_0_s0/CLK |
| 19.981 | 0.232 | tC2Q | RF | 11 | u_b2p/u_b2p_inst/rByteCtrl_0_s0/Q |
| 20.455 | 0.474 | tNET | FF | 1 | u_b2p/u_b2p_inst/u_hs_adj/rWCnt_9_s4/I1 |
| 21.010 | 0.555 | tINS | FF | 11 | u_b2p/u_b2p_inst/u_hs_adj/rWCnt_9_s4/F |
| 21.484 | 0.474 | tNET | FF | 1 | u_b2p/u_b2p_inst/u_hs_adj/n68_s2/I2 |
| 21.937 | 0.453 | tINS | FF | 1 | u_b2p/u_b2p_inst/u_hs_adj/n68_s2/F |
| 22.411 | 0.474 | tNET | FF | 1 | u_b2p/u_b2p_inst/u_hs_adj/rSCnt_3_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 21.429 | 0.000 | u_pll_1/rpll_inst/CLKOUT.default_gen_clk | |||
| 22.269 | 0.841 | tCL | RR | 214 | u_pll_1/rpll_inst/CLKOUT |
| 22.629 | 0.360 | tNET | RR | 1 | u_b2p/u_b2p_inst/u_hs_adj/rSCnt_3_s1/CLK |
| 22.594 | -0.035 | tUnc | u_b2p/u_b2p_inst/u_hs_adj/rSCnt_3_s1 | ||
| 22.559 | -0.035 | tSu | 1 | u_b2p/u_b2p_inst/u_hs_adj/rSCnt_3_s1 |
| Clock Skew: | 0.500 |
| Setup Relationship: | 2.381 |
| Logic Level: | 3 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 1.008, 37.866%; route: 1.422, 53.419%; tC2Q: 0.232, 8.715% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 5
Path Summary:| Slack | 0.149 |
| Data Arrival Time | 22.411 |
| Data Required Time | 22.559 |
| From | u_b2p/u_b2p_inst/rByteCtrl_0_s0 |
| To | u_b2p/u_b2p_inst/u_hs_adj/rSCnt_5_s1 |
| Launch Clk | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_pll_1/rpll_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 19.048 | 0.000 | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT.default_gen_clk | |||
| 19.389 | 0.341 | tCL | RR | 1041 | u_mipi_dphy/DPHY_RX_INST/u_idesx8/Inst3_CLKDIV/CLKOUT |
| 19.749 | 0.360 | tNET | RR | 1 | u_b2p/u_b2p_inst/rByteCtrl_0_s0/CLK |
| 19.981 | 0.232 | tC2Q | RF | 11 | u_b2p/u_b2p_inst/rByteCtrl_0_s0/Q |
| 20.455 | 0.474 | tNET | FF | 1 | u_b2p/u_b2p_inst/u_hs_adj/rWCnt_9_s4/I1 |
| 21.010 | 0.555 | tINS | FF | 11 | u_b2p/u_b2p_inst/u_hs_adj/rWCnt_9_s4/F |
| 21.484 | 0.474 | tNET | FF | 1 | u_b2p/u_b2p_inst/u_hs_adj/n66_s2/I2 |
| 21.937 | 0.453 | tINS | FF | 1 | u_b2p/u_b2p_inst/u_hs_adj/n66_s2/F |
| 22.411 | 0.474 | tNET | FF | 1 | u_b2p/u_b2p_inst/u_hs_adj/rSCnt_5_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 21.429 | 0.000 | u_pll_1/rpll_inst/CLKOUT.default_gen_clk | |||
| 22.269 | 0.841 | tCL | RR | 214 | u_pll_1/rpll_inst/CLKOUT |
| 22.629 | 0.360 | tNET | RR | 1 | u_b2p/u_b2p_inst/u_hs_adj/rSCnt_5_s1/CLK |
| 22.594 | -0.035 | tUnc | u_b2p/u_b2p_inst/u_hs_adj/rSCnt_5_s1 | ||
| 22.559 | -0.035 | tSu | 1 | u_b2p/u_b2p_inst/u_hs_adj/rSCnt_5_s1 |
| Clock Skew: | 0.500 |
| Setup Relationship: | 2.381 |
| Logic Level: | 3 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 1.008, 37.866%; route: 1.422, 53.419%; tC2Q: 0.232, 8.715% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |