Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\myWork\IP\releaseVerify\version\1.9.9.02\Gowin_DSI_RX_B2P_RefDesigns\csi_rx_demo_5a138\fpga_proj\src\byte_to_pixel\byte_to_pixel.v E:\myWork\IP\releaseVerify\version\1.9.9.02\Gowin_DSI_RX_B2P_RefDesigns\csi_rx_demo_5a138\fpga_proj\src\gowin_mipi_dphy_rx\gowin_mipi_dphy_rx.v E:\myWork\IP\releaseVerify\version\1.9.9.02\Gowin_DSI_RX_B2P_RefDesigns\csi_rx_demo_5a138\fpga_proj\src\gowin_pll\gowin_pll.v E:\myWork\IP\releaseVerify\version\1.9.9.02\Gowin_DSI_RX_B2P_RefDesigns\csi_rx_demo_5a138\fpga_proj\src\mipi_csi2_rx\csi2_rx.v E:\myWork\IP\releaseVerify\version\1.9.9.02\Gowin_DSI_RX_B2P_RefDesigns\csi_rx_demo_5a138\fpga_proj\src\ov5647\bayer_to_rgb\bayer_rgb.v E:\myWork\IP\releaseVerify\version\1.9.9.02\Gowin_DSI_RX_B2P_RefDesigns\csi_rx_demo_5a138\fpga_proj\src\ov5647\bayer_to_rgb\ram_line.v E:\myWork\IP\releaseVerify\version\1.9.9.02\Gowin_DSI_RX_B2P_RefDesigns\csi_rx_demo_5a138\fpga_proj\src\ov5647\bayer_to_rgb\shift_line.v E:\myWork\IP\releaseVerify\version\1.9.9.02\Gowin_DSI_RX_B2P_RefDesigns\csi_rx_demo_5a138\fpga_proj\src\ov5647\bayer_to_rgb\video_format_detect.v E:\myWork\IP\releaseVerify\version\1.9.9.02\Gowin_DSI_RX_B2P_RefDesigns\csi_rx_demo_5a138\fpga_proj\src\ov5647\ov5647_init\I2C_Interface.v E:\myWork\IP\releaseVerify\version\1.9.9.02\Gowin_DSI_RX_B2P_RefDesigns\csi_rx_demo_5a138\fpga_proj\src\ov5647\ov5647_init\OV5647_Controller.v E:\myWork\IP\releaseVerify\version\1.9.9.02\Gowin_DSI_RX_B2P_RefDesigns\csi_rx_demo_5a138\fpga_proj\src\ov5647\ov5647_init\OV5647_Registers.v E:\myWork\IP\releaseVerify\version\1.9.9.02\Gowin_DSI_RX_B2P_RefDesigns\csi_rx_demo_5a138\fpga_proj\src\top.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.9.02 |
| Part Number | GW5AST-LV138FPG676AC1/I0 |
| Device | GW5AST-138 |
| Device Version | B |
| Created Time | Tue Mar 19 15:24:09 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | CSI_Demo_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.309s, Peak memory usage = 1673.137MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 1673.137MB Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 1673.137MB Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.048s, Peak memory usage = 1673.137MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 1673.137MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 1673.137MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 1673.137MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 1673.137MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.041s, Peak memory usage = 1673.137MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 1673.137MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 1673.137MB Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 1673.137MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.096s, Peak memory usage = 1673.137MB Generate output files: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.061s, Peak memory usage = 1673.137MB |
| Total Time and Memory Usage | CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 1673.137MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 16 |
| I/O Buf | 9 |
| IBUF | 1 |
| OBUF | 7 |
| TLVDS_IBUF | 1 |
| Register | 827 |
| DFFSE | 23 |
| DFFRE | 170 |
| DFFPE | 50 |
| DFFCE | 584 |
| LUT | 884 |
| LUT2 | 142 |
| LUT3 | 230 |
| LUT4 | 512 |
| ALU | 120 |
| ALU | 120 |
| INV | 15 |
| INV | 15 |
| BSRAM | 2 |
| SDPB | 2 |
| CLOCK | 2 |
| PLL | 1 |
| CLKDIV | 1 |
| MIPI_DPHY_RX | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 1019(899 LUT, 120 ALU) / 138240 | <1% |
| Register | 827 / 139140 | <1% |
| --Register as Latch | 0 / 139140 | 0% |
| --Register as FF | 827 / 139140 | <1% |
| BSRAM | 2 / 340 | <1% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| uut_div4/CLKOUT.default_gen_clk | Generated | 40.000 | 25.0 | 0.000 | 20.000 | DEFAULT_CLK | uut_div4/CLKOUT |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | uut_div4/CLKOUT.default_gen_clk | 25.000(MHz) | 197.628(MHz) | 5 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 34.940 |
| Data Arrival Time | 5.497 |
| Data Required Time | 40.437 |
| From | u_ov5647_ctrl/Regs/wait_cnt_5_s0 |
| To | u_ov5647_ctrl/Regs/wait_cnt_31_s0 |
| Launch Clk | uut_div4/CLKOUT.default_gen_clk[R] |
| Latch Clk | uut_div4/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | uut_div4/CLKOUT.default_gen_clk | |||
| 0.336 | 0.336 | tCL | RR | 218 | uut_div4/CLKOUT |
| 0.748 | 0.413 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_5_s0/CLK |
| 1.131 | 0.382 | tC2Q | RR | 3 | u_ov5647_ctrl/Regs/wait_cnt_5_s0/Q |
| 1.543 | 0.413 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s7/I0 |
| 2.122 | 0.579 | tINS | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s7/F |
| 2.534 | 0.413 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s6/I0 |
| 3.113 | 0.579 | tINS | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s6/F |
| 3.526 | 0.413 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s3/I1 |
| 4.093 | 0.567 | tINS | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s3/F |
| 4.506 | 0.413 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s2/I0 |
| 5.084 | 0.579 | tINS | RR | 32 | u_ov5647_ctrl/Regs/wait_cnt_30_s2/F |
| 5.497 | 0.413 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_31_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 40.000 | 0.000 | uut_div4/CLKOUT.default_gen_clk | |||
| 40.336 | 0.336 | tCL | RR | 218 | uut_div4/CLKOUT |
| 40.748 | 0.413 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_31_s0/CLK |
| 40.437 | -0.311 | tSu | 1 | u_ov5647_ctrl/Regs/wait_cnt_31_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 40.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 2.304, 48.513%; route: 2.063, 43.432%; tC2Q: 0.382, 8.055% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 2
Path Summary:| Slack | 34.940 |
| Data Arrival Time | 5.497 |
| Data Required Time | 40.437 |
| From | u_ov5647_ctrl/Regs/wait_cnt_5_s0 |
| To | u_ov5647_ctrl/Regs/wait_cnt_0_s0 |
| Launch Clk | uut_div4/CLKOUT.default_gen_clk[R] |
| Latch Clk | uut_div4/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | uut_div4/CLKOUT.default_gen_clk | |||
| 0.336 | 0.336 | tCL | RR | 218 | uut_div4/CLKOUT |
| 0.748 | 0.413 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_5_s0/CLK |
| 1.131 | 0.382 | tC2Q | RR | 3 | u_ov5647_ctrl/Regs/wait_cnt_5_s0/Q |
| 1.543 | 0.413 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s7/I0 |
| 2.122 | 0.579 | tINS | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s7/F |
| 2.534 | 0.413 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s6/I0 |
| 3.113 | 0.579 | tINS | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s6/F |
| 3.526 | 0.413 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s3/I1 |
| 4.093 | 0.567 | tINS | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s3/F |
| 4.506 | 0.413 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s2/I0 |
| 5.084 | 0.579 | tINS | RR | 32 | u_ov5647_ctrl/Regs/wait_cnt_30_s2/F |
| 5.497 | 0.413 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_0_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 40.000 | 0.000 | uut_div4/CLKOUT.default_gen_clk | |||
| 40.336 | 0.336 | tCL | RR | 218 | uut_div4/CLKOUT |
| 40.748 | 0.413 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_0_s0/CLK |
| 40.437 | -0.311 | tSu | 1 | u_ov5647_ctrl/Regs/wait_cnt_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 40.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 2.304, 48.513%; route: 2.063, 43.432%; tC2Q: 0.382, 8.055% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 3
Path Summary:| Slack | 34.940 |
| Data Arrival Time | 5.497 |
| Data Required Time | 40.437 |
| From | u_ov5647_ctrl/Regs/wait_cnt_5_s0 |
| To | u_ov5647_ctrl/Regs/wait_cnt_1_s0 |
| Launch Clk | uut_div4/CLKOUT.default_gen_clk[R] |
| Latch Clk | uut_div4/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | uut_div4/CLKOUT.default_gen_clk | |||
| 0.336 | 0.336 | tCL | RR | 218 | uut_div4/CLKOUT |
| 0.748 | 0.413 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_5_s0/CLK |
| 1.131 | 0.382 | tC2Q | RR | 3 | u_ov5647_ctrl/Regs/wait_cnt_5_s0/Q |
| 1.543 | 0.413 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s7/I0 |
| 2.122 | 0.579 | tINS | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s7/F |
| 2.534 | 0.413 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s6/I0 |
| 3.113 | 0.579 | tINS | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s6/F |
| 3.526 | 0.413 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s3/I1 |
| 4.093 | 0.567 | tINS | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s3/F |
| 4.506 | 0.413 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s2/I0 |
| 5.084 | 0.579 | tINS | RR | 32 | u_ov5647_ctrl/Regs/wait_cnt_30_s2/F |
| 5.497 | 0.413 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_1_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 40.000 | 0.000 | uut_div4/CLKOUT.default_gen_clk | |||
| 40.336 | 0.336 | tCL | RR | 218 | uut_div4/CLKOUT |
| 40.748 | 0.413 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_1_s0/CLK |
| 40.437 | -0.311 | tSu | 1 | u_ov5647_ctrl/Regs/wait_cnt_1_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 40.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 2.304, 48.513%; route: 2.063, 43.432%; tC2Q: 0.382, 8.055% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 4
Path Summary:| Slack | 34.940 |
| Data Arrival Time | 5.497 |
| Data Required Time | 40.437 |
| From | u_ov5647_ctrl/Regs/wait_cnt_5_s0 |
| To | u_ov5647_ctrl/Regs/wait_cnt_2_s0 |
| Launch Clk | uut_div4/CLKOUT.default_gen_clk[R] |
| Latch Clk | uut_div4/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | uut_div4/CLKOUT.default_gen_clk | |||
| 0.336 | 0.336 | tCL | RR | 218 | uut_div4/CLKOUT |
| 0.748 | 0.413 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_5_s0/CLK |
| 1.131 | 0.382 | tC2Q | RR | 3 | u_ov5647_ctrl/Regs/wait_cnt_5_s0/Q |
| 1.543 | 0.413 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s7/I0 |
| 2.122 | 0.579 | tINS | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s7/F |
| 2.534 | 0.413 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s6/I0 |
| 3.113 | 0.579 | tINS | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s6/F |
| 3.526 | 0.413 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s3/I1 |
| 4.093 | 0.567 | tINS | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s3/F |
| 4.506 | 0.413 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s2/I0 |
| 5.084 | 0.579 | tINS | RR | 32 | u_ov5647_ctrl/Regs/wait_cnt_30_s2/F |
| 5.497 | 0.413 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_2_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 40.000 | 0.000 | uut_div4/CLKOUT.default_gen_clk | |||
| 40.336 | 0.336 | tCL | RR | 218 | uut_div4/CLKOUT |
| 40.748 | 0.413 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_2_s0/CLK |
| 40.437 | -0.311 | tSu | 1 | u_ov5647_ctrl/Regs/wait_cnt_2_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 40.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 2.304, 48.513%; route: 2.063, 43.432%; tC2Q: 0.382, 8.055% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 5
Path Summary:| Slack | 34.940 |
| Data Arrival Time | 5.497 |
| Data Required Time | 40.437 |
| From | u_ov5647_ctrl/Regs/wait_cnt_5_s0 |
| To | u_ov5647_ctrl/Regs/wait_cnt_3_s0 |
| Launch Clk | uut_div4/CLKOUT.default_gen_clk[R] |
| Latch Clk | uut_div4/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | uut_div4/CLKOUT.default_gen_clk | |||
| 0.336 | 0.336 | tCL | RR | 218 | uut_div4/CLKOUT |
| 0.748 | 0.413 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_5_s0/CLK |
| 1.131 | 0.382 | tC2Q | RR | 3 | u_ov5647_ctrl/Regs/wait_cnt_5_s0/Q |
| 1.543 | 0.413 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s7/I0 |
| 2.122 | 0.579 | tINS | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s7/F |
| 2.534 | 0.413 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s6/I0 |
| 3.113 | 0.579 | tINS | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s6/F |
| 3.526 | 0.413 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s3/I1 |
| 4.093 | 0.567 | tINS | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s3/F |
| 4.506 | 0.413 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_30_s2/I0 |
| 5.084 | 0.579 | tINS | RR | 32 | u_ov5647_ctrl/Regs/wait_cnt_30_s2/F |
| 5.497 | 0.413 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_3_s0/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 40.000 | 0.000 | uut_div4/CLKOUT.default_gen_clk | |||
| 40.336 | 0.336 | tCL | RR | 218 | uut_div4/CLKOUT |
| 40.748 | 0.413 | tNET | RR | 1 | u_ov5647_ctrl/Regs/wait_cnt_3_s0/CLK |
| 40.437 | -0.311 | tSu | 1 | u_ov5647_ctrl/Regs/wait_cnt_3_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 40.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 2.304, 48.513%; route: 2.063, 43.432%; tC2Q: 0.382, 8.055% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |