Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\MIPI_PIXEL_TO_BYTE\data\pixel_to_byte.v D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\MIPI_PIXEL_TO_BYTE\data\pixel_to_byte_wrap.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.9.01 (64-bit) |
| Part Number | GW2A-LV18QN88C7/I6 |
| Device | GW2A-18 |
| Device Version | C |
| Created Time | Wed Mar 6 10:14:33 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | Pixel_to_Byte_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.146s, Peak memory usage = 101.496MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 101.496MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 101.496MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 101.496MB Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 101.496MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 101.496MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 101.496MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 101.496MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 101.496MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 101.496MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 101.496MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 101.496MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.289s, Peak memory usage = 129.523MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.037s, Peak memory usage = 129.523MB Generate output files: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.176s, Peak memory usage = 129.523MB |
| Total Time and Memory Usage | CPU time = 0h 0m 0.449s, Elapsed time = 0h 0m 0.703s, Peak memory usage = 129.523MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 67 |
| I/O Buf | 67 |
| IBUF | 30 |
| OBUF | 37 |
| Register | 210 |
| DFF | 12 |
| DFFS | 2 |
| DFFR | 8 |
| DFFRE | 50 |
| DFFP | 2 |
| DFFPE | 2 |
| DFFC | 22 |
| DFFCE | 112 |
| LUT | 121 |
| LUT2 | 20 |
| LUT3 | 19 |
| LUT4 | 82 |
| ALU | 14 |
| ALU | 14 |
| SSRAM | 8 |
| RAM16SDP4 | 8 |
| INV | 5 |
| INV | 5 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 188(126 LUT, 14 ALU, 8 RAM16) / 20736 | <1% |
| Register | 210 / 15750 | 2% |
| --Register as Latch | 0 / 15750 | 0% |
| --Register as FF | 210 / 15750 | 2% |
| BSRAM | 0 / 46 | 0% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| I_PIXEL_CLK | Base | 10.000 | 100.0 | 0.000 | 5.000 | I_PIXEL_CLK_ibuf/I | ||
| I_BYTE_CLK | Base | 10.000 | 100.0 | 0.000 | 5.000 | I_BYTE_CLK_ibuf/I |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | I_PIXEL_CLK | 100.000(MHz) | 138.298(MHz) | 7 | TOP |
| 2 | I_BYTE_CLK | 100.000(MHz) | 166.396(MHz) | 6 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 2.769 |
| Data Arrival Time | 8.490 |
| Data Required Time | 11.259 |
| From | u_p2b/u_mid_buf/rRPtrWsync_2_s0 |
| To | u_p2b/u_mid_buf/rFull_s0 |
| Launch Clk | I_PIXEL_CLK[R] |
| Latch Clk | I_PIXEL_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_PIXEL_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_PIXEL_CLK_ibuf/I |
| 0.853 | 0.853 | tINS | RR | 114 | I_PIXEL_CLK_ibuf/O |
| 1.303 | 0.450 | tNET | RR | 1 | u_p2b/u_mid_buf/rRPtrWsync_2_s0/CLK |
| 1.593 | 0.290 | tC2Q | RF | 3 | u_p2b/u_mid_buf/rRPtrWsync_2_s0/Q |
| 2.186 | 0.593 | tNET | FF | 1 | u_p2b/u_mid_buf/wRPtrBinX_1_s0/I1 |
| 2.879 | 0.694 | tINS | FF | 3 | u_p2b/u_mid_buf/wRPtrBinX_1_s0/F |
| 3.472 | 0.593 | tNET | FF | 1 | u_p2b/u_mid_buf/wRPtrBinX_0_s0/I1 |
| 4.166 | 0.694 | tINS | FF | 1 | u_p2b/u_mid_buf/wRPtrBinX_0_s0/F |
| 4.758 | 0.593 | tNET | FF | 2 | u_p2b/u_mid_buf/n327_s0/I1 |
| 5.471 | 0.712 | tINS | FR | 1 | u_p2b/u_mid_buf/n327_s0/COUT |
| 5.471 | 0.000 | tNET | RR | 2 | u_p2b/u_mid_buf/n328_s0/CIN |
| 5.515 | 0.044 | tINS | RF | 1 | u_p2b/u_mid_buf/n328_s0/COUT |
| 5.515 | 0.000 | tNET | FF | 2 | u_p2b/u_mid_buf/n329_s0/CIN |
| 5.559 | 0.044 | tINS | FF | 1 | u_p2b/u_mid_buf/n329_s0/COUT |
| 5.559 | 0.000 | tNET | FF | 2 | u_p2b/u_mid_buf/n330_s0/CIN |
| 5.603 | 0.044 | tINS | FF | 1 | u_p2b/u_mid_buf/n330_s0/COUT |
| 6.195 | 0.593 | tNET | FF | 1 | u_p2b/u_mid_buf/n342_s4/I0 |
| 6.841 | 0.646 | tINS | FF | 1 | u_p2b/u_mid_buf/n342_s4/F |
| 7.434 | 0.593 | tNET | FF | 1 | u_p2b/u_mid_buf/n342_s0/I3 |
| 7.898 | 0.464 | tINS | FF | 1 | u_p2b/u_mid_buf/n342_s0/F |
| 8.490 | 0.593 | tNET | FF | 1 | u_p2b/u_mid_buf/rFull_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_PIXEL_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_PIXEL_CLK_ibuf/I |
| 10.853 | 0.853 | tINS | RR | 114 | I_PIXEL_CLK_ibuf/O |
| 11.303 | 0.450 | tNET | RR | 1 | u_p2b/u_mid_buf/rFull_s0/CLK |
| 11.259 | -0.044 | tSu | 1 | u_p2b/u_mid_buf/rFull_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.853, 65.468%; route: 0.450, 34.532% |
| Arrival Data Path Delay: | cell: 3.342, 46.501%; route: 3.555, 49.464%; tC2Q: 0.290, 4.035% |
| Required Clock Path Delay: | cell: 0.853, 65.468%; route: 0.450, 34.532% |
Path 2
Path Summary:| Slack | 3.990 |
| Data Arrival Time | 7.269 |
| Data Required Time | 11.259 |
| From | u_p2b/u_mid_buf/rWPtrRsync_2_s0 |
| To | u_p2b/u_mid_buf/rEmpty_s0 |
| Launch Clk | I_BYTE_CLK[R] |
| Latch Clk | I_BYTE_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_BYTE_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_BYTE_CLK_ibuf/I |
| 0.853 | 0.853 | tINS | RR | 104 | I_BYTE_CLK_ibuf/O |
| 1.303 | 0.450 | tNET | RR | 1 | u_p2b/u_mid_buf/rWPtrRsync_2_s0/CLK |
| 1.593 | 0.290 | tC2Q | RF | 3 | u_p2b/u_mid_buf/rWPtrRsync_2_s0/Q |
| 2.186 | 0.593 | tNET | FF | 1 | u_p2b/u_mid_buf/wWPtrBinX_1_s0/I1 |
| 2.879 | 0.694 | tINS | FF | 4 | u_p2b/u_mid_buf/wWPtrBinX_1_s0/F |
| 3.472 | 0.593 | tNET | FF | 1 | u_p2b/u_mid_buf/wWPtrBinX_0_s0/I1 |
| 4.166 | 0.694 | tINS | FF | 2 | u_p2b/u_mid_buf/wWPtrBinX_0_s0/F |
| 4.758 | 0.593 | tNET | FF | 2 | u_p2b/u_mid_buf/n308_s0/I0 |
| 5.444 | 0.686 | tINS | FR | 1 | u_p2b/u_mid_buf/n308_s0/COUT |
| 5.444 | 0.000 | tNET | RR | 2 | u_p2b/u_mid_buf/n309_s0/CIN |
| 5.488 | 0.044 | tINS | RF | 1 | u_p2b/u_mid_buf/n309_s0/COUT |
| 5.488 | 0.000 | tNET | FF | 2 | u_p2b/u_mid_buf/n310_s0/CIN |
| 5.532 | 0.044 | tINS | FF | 1 | u_p2b/u_mid_buf/n310_s0/COUT |
| 5.532 | 0.000 | tNET | FF | 2 | u_p2b/u_mid_buf/n311_s0/CIN |
| 5.576 | 0.044 | tINS | FF | 1 | u_p2b/u_mid_buf/n311_s0/COUT |
| 5.576 | 0.000 | tNET | FF | 2 | u_p2b/u_mid_buf/n312_s0/CIN |
| 5.620 | 0.044 | tINS | FF | 1 | u_p2b/u_mid_buf/n312_s0/COUT |
| 6.213 | 0.593 | tNET | FF | 1 | u_p2b/u_mid_buf/n314_s0/I3 |
| 6.677 | 0.464 | tINS | FF | 1 | u_p2b/u_mid_buf/n314_s0/F |
| 7.269 | 0.593 | tNET | FF | 1 | u_p2b/u_mid_buf/rEmpty_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_BYTE_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_BYTE_CLK_ibuf/I |
| 10.853 | 0.853 | tINS | RR | 104 | I_BYTE_CLK_ibuf/O |
| 11.303 | 0.450 | tNET | RR | 1 | u_p2b/u_mid_buf/rEmpty_s0/CLK |
| 11.259 | -0.044 | tSu | 1 | u_p2b/u_mid_buf/rEmpty_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.853, 65.468%; route: 0.450, 34.532% |
| Arrival Data Path Delay: | cell: 2.713, 45.483%; route: 2.963, 49.656%; tC2Q: 0.290, 4.861% |
| Required Clock Path Delay: | cell: 0.853, 65.468%; route: 0.450, 34.532% |
Path 3
Path Summary:| Slack | 4.503 |
| Data Arrival Time | 6.756 |
| Data Required Time | 11.259 |
| From | u_p2b/u_mid_buf/rWPtrRsync_2_s0 |
| To | u_p2b/u_mid_buf/rRdDiff_4_s0 |
| Launch Clk | I_BYTE_CLK[R] |
| Latch Clk | I_BYTE_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_BYTE_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_BYTE_CLK_ibuf/I |
| 0.853 | 0.853 | tINS | RR | 104 | I_BYTE_CLK_ibuf/O |
| 1.303 | 0.450 | tNET | RR | 1 | u_p2b/u_mid_buf/rWPtrRsync_2_s0/CLK |
| 1.593 | 0.290 | tC2Q | RF | 3 | u_p2b/u_mid_buf/rWPtrRsync_2_s0/Q |
| 2.186 | 0.593 | tNET | FF | 1 | u_p2b/u_mid_buf/wWPtrBinX_1_s0/I1 |
| 2.879 | 0.694 | tINS | FF | 4 | u_p2b/u_mid_buf/wWPtrBinX_1_s0/F |
| 3.472 | 0.593 | tNET | FF | 1 | u_p2b/u_mid_buf/wWPtrBinX_0_s0/I1 |
| 4.166 | 0.694 | tINS | FF | 2 | u_p2b/u_mid_buf/wWPtrBinX_0_s0/F |
| 4.758 | 0.593 | tNET | FF | 2 | u_p2b/u_mid_buf/wRdDiff_0_s/I0 |
| 5.444 | 0.686 | tINS | FR | 1 | u_p2b/u_mid_buf/wRdDiff_0_s/COUT |
| 5.444 | 0.000 | tNET | RR | 2 | u_p2b/u_mid_buf/wRdDiff_1_s/CIN |
| 5.488 | 0.044 | tINS | RF | 1 | u_p2b/u_mid_buf/wRdDiff_1_s/COUT |
| 5.488 | 0.000 | tNET | FF | 2 | u_p2b/u_mid_buf/wRdDiff_2_s/CIN |
| 5.532 | 0.044 | tINS | FF | 1 | u_p2b/u_mid_buf/wRdDiff_2_s/COUT |
| 5.532 | 0.000 | tNET | FF | 2 | u_p2b/u_mid_buf/wRdDiff_3_s/CIN |
| 5.576 | 0.044 | tINS | FF | 1 | u_p2b/u_mid_buf/wRdDiff_3_s/COUT |
| 5.576 | 0.000 | tNET | FF | 2 | u_p2b/u_mid_buf/wRdDiff_4_s/CIN |
| 6.164 | 0.587 | tINS | FF | 1 | u_p2b/u_mid_buf/wRdDiff_4_s/SUM |
| 6.756 | 0.593 | tNET | FF | 1 | u_p2b/u_mid_buf/rRdDiff_4_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_BYTE_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_BYTE_CLK_ibuf/I |
| 10.853 | 0.853 | tINS | RR | 104 | I_BYTE_CLK_ibuf/O |
| 11.303 | 0.450 | tNET | RR | 1 | u_p2b/u_mid_buf/rRdDiff_4_s0/CLK |
| 11.259 | -0.044 | tSu | 1 | u_p2b/u_mid_buf/rRdDiff_4_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.853, 65.468%; route: 0.450, 34.532% |
| Arrival Data Path Delay: | cell: 2.793, 51.222%; route: 2.370, 43.460%; tC2Q: 0.290, 5.318% |
| Required Clock Path Delay: | cell: 0.853, 65.468%; route: 0.450, 34.532% |
Path 4
Path Summary:| Slack | 4.547 |
| Data Arrival Time | 6.712 |
| Data Required Time | 11.259 |
| From | u_p2b/u_mid_buf/rWPtrRsync_2_s0 |
| To | u_p2b/u_mid_buf/rRdDiff_3_s0 |
| Launch Clk | I_BYTE_CLK[R] |
| Latch Clk | I_BYTE_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_BYTE_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_BYTE_CLK_ibuf/I |
| 0.853 | 0.853 | tINS | RR | 104 | I_BYTE_CLK_ibuf/O |
| 1.303 | 0.450 | tNET | RR | 1 | u_p2b/u_mid_buf/rWPtrRsync_2_s0/CLK |
| 1.593 | 0.290 | tC2Q | RF | 3 | u_p2b/u_mid_buf/rWPtrRsync_2_s0/Q |
| 2.186 | 0.593 | tNET | FF | 1 | u_p2b/u_mid_buf/wWPtrBinX_1_s0/I1 |
| 2.879 | 0.694 | tINS | FF | 4 | u_p2b/u_mid_buf/wWPtrBinX_1_s0/F |
| 3.472 | 0.593 | tNET | FF | 1 | u_p2b/u_mid_buf/wWPtrBinX_0_s0/I1 |
| 4.166 | 0.694 | tINS | FF | 2 | u_p2b/u_mid_buf/wWPtrBinX_0_s0/F |
| 4.758 | 0.593 | tNET | FF | 2 | u_p2b/u_mid_buf/wRdDiff_0_s/I0 |
| 5.444 | 0.686 | tINS | FR | 1 | u_p2b/u_mid_buf/wRdDiff_0_s/COUT |
| 5.444 | 0.000 | tNET | RR | 2 | u_p2b/u_mid_buf/wRdDiff_1_s/CIN |
| 5.488 | 0.044 | tINS | RF | 1 | u_p2b/u_mid_buf/wRdDiff_1_s/COUT |
| 5.488 | 0.000 | tNET | FF | 2 | u_p2b/u_mid_buf/wRdDiff_2_s/CIN |
| 5.532 | 0.044 | tINS | FF | 1 | u_p2b/u_mid_buf/wRdDiff_2_s/COUT |
| 5.532 | 0.000 | tNET | FF | 2 | u_p2b/u_mid_buf/wRdDiff_3_s/CIN |
| 6.120 | 0.587 | tINS | FF | 1 | u_p2b/u_mid_buf/wRdDiff_3_s/SUM |
| 6.712 | 0.593 | tNET | FF | 1 | u_p2b/u_mid_buf/rRdDiff_3_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_BYTE_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_BYTE_CLK_ibuf/I |
| 10.853 | 0.853 | tINS | RR | 104 | I_BYTE_CLK_ibuf/O |
| 11.303 | 0.450 | tNET | RR | 1 | u_p2b/u_mid_buf/rRdDiff_3_s0/CLK |
| 11.259 | -0.044 | tSu | 1 | u_p2b/u_mid_buf/rRdDiff_3_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.853, 65.468%; route: 0.450, 34.532% |
| Arrival Data Path Delay: | cell: 2.749, 50.825%; route: 2.370, 43.814%; tC2Q: 0.290, 5.361% |
| Required Clock Path Delay: | cell: 0.853, 65.468%; route: 0.450, 34.532% |
Path 5
Path Summary:| Slack | 4.591 |
| Data Arrival Time | 6.668 |
| Data Required Time | 11.259 |
| From | u_p2b/u_mid_buf/rWPtrRsync_2_s0 |
| To | u_p2b/u_mid_buf/rRdDiff_2_s0 |
| Launch Clk | I_BYTE_CLK[R] |
| Latch Clk | I_BYTE_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_BYTE_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_BYTE_CLK_ibuf/I |
| 0.853 | 0.853 | tINS | RR | 104 | I_BYTE_CLK_ibuf/O |
| 1.303 | 0.450 | tNET | RR | 1 | u_p2b/u_mid_buf/rWPtrRsync_2_s0/CLK |
| 1.593 | 0.290 | tC2Q | RF | 3 | u_p2b/u_mid_buf/rWPtrRsync_2_s0/Q |
| 2.186 | 0.593 | tNET | FF | 1 | u_p2b/u_mid_buf/wWPtrBinX_1_s0/I1 |
| 2.879 | 0.694 | tINS | FF | 4 | u_p2b/u_mid_buf/wWPtrBinX_1_s0/F |
| 3.472 | 0.593 | tNET | FF | 1 | u_p2b/u_mid_buf/wWPtrBinX_0_s0/I1 |
| 4.166 | 0.694 | tINS | FF | 2 | u_p2b/u_mid_buf/wWPtrBinX_0_s0/F |
| 4.758 | 0.593 | tNET | FF | 2 | u_p2b/u_mid_buf/wRdDiff_0_s/I0 |
| 5.444 | 0.686 | tINS | FR | 1 | u_p2b/u_mid_buf/wRdDiff_0_s/COUT |
| 5.444 | 0.000 | tNET | RR | 2 | u_p2b/u_mid_buf/wRdDiff_1_s/CIN |
| 5.488 | 0.044 | tINS | RF | 1 | u_p2b/u_mid_buf/wRdDiff_1_s/COUT |
| 5.488 | 0.000 | tNET | FF | 2 | u_p2b/u_mid_buf/wRdDiff_2_s/CIN |
| 6.076 | 0.587 | tINS | FF | 1 | u_p2b/u_mid_buf/wRdDiff_2_s/SUM |
| 6.668 | 0.593 | tNET | FF | 1 | u_p2b/u_mid_buf/rRdDiff_2_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | I_BYTE_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | I_BYTE_CLK_ibuf/I |
| 10.853 | 0.853 | tINS | RR | 104 | I_BYTE_CLK_ibuf/O |
| 11.303 | 0.450 | tNET | RR | 1 | u_p2b/u_mid_buf/rRdDiff_2_s0/CLK |
| 11.259 | -0.044 | tSu | 1 | u_p2b/u_mid_buf/rRdDiff_2_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.853, 65.468%; route: 0.450, 34.532% |
| Arrival Data Path Delay: | cell: 2.705, 50.422%; route: 2.370, 44.173%; tC2Q: 0.290, 5.405% |
| Required Clock Path Delay: | cell: 0.853, 65.468%; route: 0.450, 34.532% |