| Report Title |
Power Analysis Report |
| Design File |
F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\Dsi_Test_pattern_2a18\fpga_proj\impl\gwsynthesis\Dsi_test_pattern_2a18.vg |
| Physical Constraints File |
F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\Dsi_Test_pattern_2a18\fpga_proj\src\DK_START_Gw2A18_V2.cst |
| Timing Constraints File |
F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\Dsi_Test_pattern_2a18\fpga_proj\src\dsi_test.sdc |
| Tool Version |
V1.9.9.01 (64-bit) |
| Part Number |
GW2A-LV18PG256C8/I7 |
| Device |
GW2A-18 |
| Device Version |
C |
| Created Time |
Wed Mar 6 11:19:28 2024
|
| Legal Announcement |
Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved. |
| Total Power (mW) |
201.742 |
| Quiescent Power (mW) |
92.073 |
| Dynamic Power (mW) |
109.669 |
| Junction Temperature |
31.460 |
| Theta JA |
32.020 |
| Max Allowed Ambient Temperature |
78.540 |
| Default IO Toggle Rate |
0.125 |
Default Remain Toggle Rate |
0.125 |
| Use Vectorless Estimation |
false |
| Filter Glitches |
false |
| Related Vcd File |
|
| Related Saif File |
|
| Use Custom Theta JA |
false |
| Air Flow |
LFM_0 |
| Heat Sink |
None |
| Use Custom Theta SA |
false |
| Board Thermal Model |
None |
| Use Custom Theta JB |
false |
| Ambient Temperature |
25.000
|
| Voltage Source |
Voltage |
Dynamic Current(mA) |
Quiescent Current(mA) |
Power(mW) |
| VCC |
1.000 |
74.758 |
61.518 |
136.276 |
| VCCX |
2.500 |
2.203 |
11.364 |
33.916 |
| VCCIO12 |
1.200 |
0.171 |
0.260 |
0.517 |
| VCCIO25 |
2.500 |
11.680 |
0.733 |
31.032 |
| Block Type |
Total Power(mW) |
Static Power(mW) |
Average Toggle Rate(millions of transitions/sec) |
| Logic |
2.813 |
NA |
14.300 |
| IO |
41.150
| 3.766
| 31.083
|
| BSRAM |
32.321
| NA |
NA |
| PLL |
37.059
| NA |
NA |
| Hierarchy Entity |
Total Power(mW) |
Block Dynamic Power(mW) |
| DsiTest_Top |
72.194 |
72.194(71.740) |
| DsiTest_Top/u_dsi_tx/ |
33.944 |
33.944(33.944) |
| DsiTest_Top/u_dsi_tx/u_tx/ |
33.944 |
33.944(33.932) |
| DsiTest_Top/u_dsi_tx/u_tx/u_dsi_tx/ |
33.932 |
33.932(32.631) |
| DsiTest_Top/u_dsi_tx/u_tx/u_dsi_tx/u_dphy/ |
32.631 |
32.631(32.503) |
| DsiTest_Top/u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/ |
0.100 |
0.100(0.032) |
| DsiTest_Top/u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_cmd_buf/u_sdpram/ |
0.032 |
0.032(0.000) |
| DsiTest_Top/u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/ |
32.403 |
32.403(32.323) |
| DsiTest_Top/u_dsi_tx/u_tx/u_dsi_tx/u_dphy/u_data_buf/u_sdpram/ |
32.323 |
32.323(0.000) |
| DsiTest_Top/u_p2b/ |
0.415 |
0.415(0.415) |
| DsiTest_Top/u_p2b/u_p2b_0/ |
0.415 |
0.415(0.229) |
| DsiTest_Top/u_p2b/u_p2b_0/GEN_FOR_I[0].u_pulse_dly/ |
0.002 |
0.002(0.000) |
| DsiTest_Top/u_p2b/u_p2b_0/GEN_FOR_I[1].u_pulse_dly/ |
0.003 |
0.003(0.000) |
| DsiTest_Top/u_p2b/u_p2b_0/GEN_FOR_I[2].u_pulse_dly/ |
0.002 |
0.002(0.000) |
| DsiTest_Top/u_p2b/u_p2b_0/GEN_FOR_I[3].u_pulse_dly/ |
0.003 |
0.003(0.000) |
| DsiTest_Top/u_p2b/u_p2b_0/u_mid_buf/ |
0.219 |
0.219(0.054) |
| DsiTest_Top/u_p2b/u_p2b_0/u_mid_buf/u_dpram/ |
0.054 |
0.054(0.000) |
| DsiTest_Top/u_pll/ |
37.059 |
37.059(0.000) |
| DsiTest_Top/u_test_gen/ |
0.316 |
0.316(0.000) |
| DsiTest_Top/u_tx_phy/ |
0.005 |
0.005(0.005) |
| DsiTest_Top/u_tx_phy/DPHY_TX_INST/ |
0.005 |
0.005(0.005) |
| DsiTest_Top/u_tx_phy/DPHY_TX_INST/u_IO_Ctrl_TX/ |
0.003 |
0.003(0.000) |
| DsiTest_Top/u_tx_phy/DPHY_TX_INST/u_oserx4x8/ |
0.002 |
0.002(0.000) |
| Clock Domain |
Clock Frequency(Mhz) |
Total Dynamic Power(mW) |
| pixel_clk |
141.667 |
0.984 |
| byte_clk |
106.250 |
34.184 |
| NO CLOCK DOMAIN |
0.000 |
0.000 |
| u_pll/rpll_inst/CLKOUT.default_gen_clk |
425.000 |
0.029 |
| u_pll/rpll_inst/CLKOUTP.default_gen_clk |
425.000 |
0.029 |
| clk_50 |
50.000 |
37.059 |