Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\Dsi_Test_pattern_2a18\fpga_proj\src\dsi_csi2_tx\dsi_csi2_tx.v F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\Dsi_Test_pattern_2a18\fpga_proj\src\gowin_rpll\gowin_rpll.v F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\Dsi_Test_pattern_2a18\fpga_proj\src\mipi_tx\mipi_tx.v F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\Dsi_Test_pattern_2a18\fpga_proj\src\pixel_to_byte\pixel_to_byte.v F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\Dsi_Test_pattern_2a18\fpga_proj\src\testpattern.v F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\Dsi_Test_pattern_2a18\fpga_proj\src\top.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.9.01 (64-bit) |
| Part Number | GW2A-LV18PG256C8/I7 |
| Device | GW2A-18 |
| Device Version | C |
| Created Time | Wed Mar 6 11:02:14 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | DsiTest_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.312s, Peak memory usage = 563.977MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.026s, Peak memory usage = 563.977MB Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.026s, Peak memory usage = 563.977MB Optimizing Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.046s, Peak memory usage = 563.977MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 563.977MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 563.977MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 563.977MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 563.977MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 563.977MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 563.977MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 563.977MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.453s, Elapsed time = 0h 0m 0.492s, Peak memory usage = 563.977MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.06s, Peak memory usage = 563.977MB Generate output files: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.126s, Peak memory usage = 563.977MB |
| Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 563.977MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 17 |
| I/O Buf | 12 |
| IBUF | 2 |
| OBUF | 3 |
| IOBUF | 2 |
| TLVDS_TBUF | 5 |
| Register | 896 |
| DFF | 120 |
| DFFE | 180 |
| DFFS | 8 |
| DFFSE | 16 |
| DFFR | 92 |
| DFFRE | 70 |
| DFFP | 11 |
| DFFPE | 19 |
| DFFC | 187 |
| DFFCE | 193 |
| LUT | 1551 |
| LUT2 | 131 |
| LUT3 | 612 |
| LUT4 | 808 |
| ALU | 52 |
| ALU | 52 |
| SSRAM | 12 |
| RAM16SDP4 | 12 |
| INV | 18 |
| INV | 18 |
| IOLOGIC | 5 |
| OSER8 | 5 |
| BSRAM | 2 |
| SDPX9B | 2 |
| CLOCK | 1 |
| rPLL | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 1693(1569 LUT, 52 ALU, 12 RAM16) / 20736 | 9% |
| Register | 896 / 16173 | 6% |
| --Register as Latch | 0 / 16173 | 0% |
| --Register as FF | 896 / 16173 | 6% |
| BSRAM | 2 / 46 | 5% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| OSC_50M | Base | 20.000 | 50.0 | 0.000 | 10.000 | OSC_50M_ibuf/I | ||
| u_pll/rpll_inst/CLKOUT.default_gen_clk | Generated | 2.353 | 425.0 | 0.000 | 1.176 | OSC_50M_ibuf/I | OSC_50M | u_pll/rpll_inst/CLKOUT |
| u_pll/rpll_inst/CLKOUTP.default_gen_clk | Generated | 2.353 | 425.0 | 0.588 | 1.765 | OSC_50M_ibuf/I | OSC_50M | u_pll/rpll_inst/CLKOUTP |
| u_pll/rpll_inst/CLKOUTD.default_gen_clk | Generated | 9.412 | 106.2 | 0.000 | 4.706 | OSC_50M_ibuf/I | OSC_50M | u_pll/rpll_inst/CLKOUTD |
| u_pll/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 7.059 | 141.7 | 0.000 | 3.529 | OSC_50M_ibuf/I | OSC_50M | u_pll/rpll_inst/CLKOUTD3 |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | u_pll/rpll_inst/CLKOUTD.default_gen_clk | 106.250(MHz) | 135.172(MHz) | 8 | TOP |
| 2 | u_pll/rpll_inst/CLKOUTD3.default_gen_clk | 141.667(MHz) | 172.873(MHz) | 7 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 0.534 |
| Data Arrival Time | 10.331 |
| Data Required Time | 10.865 |
| From | u_p2b/u_p2b/rCtrlSync_3_s0 |
| To | u_p2b/u_p2b/GEN_FOR_I[2].u_pulse_dly/rCnt_0_s3 |
| Launch Clk | u_pll/rpll_inst/CLKOUTD3.default_gen_clk[R] |
| Latch Clk | u_pll/rpll_inst/CLKOUTD.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 7.059 | 0.000 | u_pll/rpll_inst/CLKOUTD3.default_gen_clk | |||
| 8.236 | 1.177 | tCL | RR | 279 | u_pll/rpll_inst/CLKOUTD3 |
| 8.596 | 0.360 | tNET | RR | 1 | u_p2b/u_p2b/rCtrlSync_3_s0/CLK |
| 8.828 | 0.232 | tC2Q | RF | 3 | u_p2b/u_p2b/rCtrlSync_3_s0/Q |
| 9.302 | 0.474 | tNET | FF | 1 | u_p2b/u_p2b/GEN_FOR_I[2].u_pulse_dly/n32_s6/I1 |
| 9.857 | 0.555 | tINS | FF | 1 | u_p2b/u_p2b/GEN_FOR_I[2].u_pulse_dly/n32_s6/F |
| 10.331 | 0.474 | tNET | FF | 1 | u_p2b/u_p2b/GEN_FOR_I[2].u_pulse_dly/rCnt_0_s3/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 9.412 | 0.000 | u_pll/rpll_inst/CLKOUTD.default_gen_clk | |||
| 10.575 | 1.163 | tCL | RR | 638 | u_pll/rpll_inst/CLKOUTD |
| 10.935 | 0.360 | tNET | RR | 1 | u_p2b/u_p2b/GEN_FOR_I[2].u_pulse_dly/rCnt_0_s3/CLK |
| 10.900 | -0.035 | tUnc | u_p2b/u_p2b/GEN_FOR_I[2].u_pulse_dly/rCnt_0_s3 | ||
| 10.865 | -0.035 | tSu | 1 | u_p2b/u_p2b/GEN_FOR_I[2].u_pulse_dly/rCnt_0_s3 |
| Clock Skew: | -0.014 |
| Setup Relationship: | 2.353 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 0.555, 31.988%; route: 0.948, 54.640%; tC2Q: 0.232, 13.372% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 2
Path Summary:| Slack | 0.534 |
| Data Arrival Time | 10.331 |
| Data Required Time | 10.865 |
| From | u_p2b/u_p2b/rCtrlSync_2_s0 |
| To | u_p2b/u_p2b/GEN_FOR_I[0].u_pulse_dly/rCnt_0_s3 |
| Launch Clk | u_pll/rpll_inst/CLKOUTD3.default_gen_clk[R] |
| Latch Clk | u_pll/rpll_inst/CLKOUTD.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 7.059 | 0.000 | u_pll/rpll_inst/CLKOUTD3.default_gen_clk | |||
| 8.236 | 1.177 | tCL | RR | 279 | u_pll/rpll_inst/CLKOUTD3 |
| 8.596 | 0.360 | tNET | RR | 1 | u_p2b/u_p2b/rCtrlSync_2_s0/CLK |
| 8.828 | 0.232 | tC2Q | RF | 3 | u_p2b/u_p2b/rCtrlSync_2_s0/Q |
| 9.302 | 0.474 | tNET | FF | 1 | u_p2b/u_p2b/GEN_FOR_I[0].u_pulse_dly/n32_s6/I1 |
| 9.857 | 0.555 | tINS | FF | 1 | u_p2b/u_p2b/GEN_FOR_I[0].u_pulse_dly/n32_s6/F |
| 10.331 | 0.474 | tNET | FF | 1 | u_p2b/u_p2b/GEN_FOR_I[0].u_pulse_dly/rCnt_0_s3/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 9.412 | 0.000 | u_pll/rpll_inst/CLKOUTD.default_gen_clk | |||
| 10.575 | 1.163 | tCL | RR | 638 | u_pll/rpll_inst/CLKOUTD |
| 10.935 | 0.360 | tNET | RR | 1 | u_p2b/u_p2b/GEN_FOR_I[0].u_pulse_dly/rCnt_0_s3/CLK |
| 10.900 | -0.035 | tUnc | u_p2b/u_p2b/GEN_FOR_I[0].u_pulse_dly/rCnt_0_s3 | ||
| 10.865 | -0.035 | tSu | 1 | u_p2b/u_p2b/GEN_FOR_I[0].u_pulse_dly/rCnt_0_s3 |
| Clock Skew: | -0.014 |
| Setup Relationship: | 2.353 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 0.555, 31.988%; route: 0.948, 54.640%; tC2Q: 0.232, 13.372% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 3
Path Summary:| Slack | 0.572 |
| Data Arrival Time | 10.293 |
| Data Required Time | 10.865 |
| From | u_p2b/u_p2b/rCtrlSync_3_s0 |
| To | u_p2b/u_p2b/GEN_FOR_I[3].u_pulse_dly/rCnt_0_s3 |
| Launch Clk | u_pll/rpll_inst/CLKOUTD3.default_gen_clk[R] |
| Latch Clk | u_pll/rpll_inst/CLKOUTD.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 7.059 | 0.000 | u_pll/rpll_inst/CLKOUTD3.default_gen_clk | |||
| 8.236 | 1.177 | tCL | RR | 279 | u_pll/rpll_inst/CLKOUTD3 |
| 8.596 | 0.360 | tNET | RR | 1 | u_p2b/u_p2b/rCtrlSync_3_s0/CLK |
| 8.828 | 0.232 | tC2Q | RF | 3 | u_p2b/u_p2b/rCtrlSync_3_s0/Q |
| 9.302 | 0.474 | tNET | FF | 1 | u_p2b/u_p2b/GEN_FOR_I[3].u_pulse_dly/n32_s6/I0 |
| 9.819 | 0.517 | tINS | FF | 1 | u_p2b/u_p2b/GEN_FOR_I[3].u_pulse_dly/n32_s6/F |
| 10.293 | 0.474 | tNET | FF | 1 | u_p2b/u_p2b/GEN_FOR_I[3].u_pulse_dly/rCnt_0_s3/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 9.412 | 0.000 | u_pll/rpll_inst/CLKOUTD.default_gen_clk | |||
| 10.575 | 1.163 | tCL | RR | 638 | u_pll/rpll_inst/CLKOUTD |
| 10.935 | 0.360 | tNET | RR | 1 | u_p2b/u_p2b/GEN_FOR_I[3].u_pulse_dly/rCnt_0_s3/CLK |
| 10.900 | -0.035 | tUnc | u_p2b/u_p2b/GEN_FOR_I[3].u_pulse_dly/rCnt_0_s3 | ||
| 10.865 | -0.035 | tSu | 1 | u_p2b/u_p2b/GEN_FOR_I[3].u_pulse_dly/rCnt_0_s3 |
| Clock Skew: | -0.014 |
| Setup Relationship: | 2.353 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 0.517, 30.466%; route: 0.948, 55.863%; tC2Q: 0.232, 13.671% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 4
Path Summary:| Slack | 0.572 |
| Data Arrival Time | 10.293 |
| Data Required Time | 10.865 |
| From | u_p2b/u_p2b/rCtrlSync_2_s0 |
| To | u_p2b/u_p2b/GEN_FOR_I[1].u_pulse_dly/rCnt_0_s3 |
| Launch Clk | u_pll/rpll_inst/CLKOUTD3.default_gen_clk[R] |
| Latch Clk | u_pll/rpll_inst/CLKOUTD.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 7.059 | 0.000 | u_pll/rpll_inst/CLKOUTD3.default_gen_clk | |||
| 8.236 | 1.177 | tCL | RR | 279 | u_pll/rpll_inst/CLKOUTD3 |
| 8.596 | 0.360 | tNET | RR | 1 | u_p2b/u_p2b/rCtrlSync_2_s0/CLK |
| 8.828 | 0.232 | tC2Q | RF | 3 | u_p2b/u_p2b/rCtrlSync_2_s0/Q |
| 9.302 | 0.474 | tNET | FF | 1 | u_p2b/u_p2b/GEN_FOR_I[1].u_pulse_dly/n32_s6/I0 |
| 9.819 | 0.517 | tINS | FF | 1 | u_p2b/u_p2b/GEN_FOR_I[1].u_pulse_dly/n32_s6/F |
| 10.293 | 0.474 | tNET | FF | 1 | u_p2b/u_p2b/GEN_FOR_I[1].u_pulse_dly/rCnt_0_s3/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 9.412 | 0.000 | u_pll/rpll_inst/CLKOUTD.default_gen_clk | |||
| 10.575 | 1.163 | tCL | RR | 638 | u_pll/rpll_inst/CLKOUTD |
| 10.935 | 0.360 | tNET | RR | 1 | u_p2b/u_p2b/GEN_FOR_I[1].u_pulse_dly/rCnt_0_s3/CLK |
| 10.900 | -0.035 | tUnc | u_p2b/u_p2b/GEN_FOR_I[1].u_pulse_dly/rCnt_0_s3 | ||
| 10.865 | -0.035 | tSu | 1 | u_p2b/u_p2b/GEN_FOR_I[1].u_pulse_dly/rCnt_0_s3 |
| Clock Skew: | -0.014 |
| Setup Relationship: | 2.353 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 0.517, 30.466%; route: 0.948, 55.863%; tC2Q: 0.232, 13.671% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
Path 5
Path Summary:| Slack | 1.274 |
| Data Arrival Time | 7.286 |
| Data Required Time | 8.561 |
| From | u_p2b/u_p2b/u_mid_buf/rRPtrWsync_2_s0 |
| To | u_p2b/u_p2b/u_mid_buf/rFull_s0 |
| Launch Clk | u_pll/rpll_inst/CLKOUTD3.default_gen_clk[R] |
| Latch Clk | u_pll/rpll_inst/CLKOUTD3.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_pll/rpll_inst/CLKOUTD3.default_gen_clk | |||
| 1.177 | 1.177 | tCL | RR | 279 | u_pll/rpll_inst/CLKOUTD3 |
| 1.537 | 0.360 | tNET | RR | 1 | u_p2b/u_p2b/u_mid_buf/rRPtrWsync_2_s0/CLK |
| 1.769 | 0.232 | tC2Q | RF | 3 | u_p2b/u_p2b/u_mid_buf/rRPtrWsync_2_s0/Q |
| 2.243 | 0.474 | tNET | FF | 1 | u_p2b/u_p2b/u_mid_buf/wRPtrBinX_1_s0/I1 |
| 2.798 | 0.555 | tINS | FF | 3 | u_p2b/u_p2b/u_mid_buf/wRPtrBinX_1_s0/F |
| 3.272 | 0.474 | tNET | FF | 1 | u_p2b/u_p2b/u_mid_buf/wRPtrBinX_0_s0/I1 |
| 3.827 | 0.555 | tINS | FF | 1 | u_p2b/u_p2b/u_mid_buf/wRPtrBinX_0_s0/F |
| 4.301 | 0.474 | tNET | FF | 2 | u_p2b/u_p2b/u_mid_buf/n327_s0/I1 |
| 4.871 | 0.570 | tINS | FR | 1 | u_p2b/u_p2b/u_mid_buf/n327_s0/COUT |
| 4.871 | 0.000 | tNET | RR | 2 | u_p2b/u_p2b/u_mid_buf/n328_s0/CIN |
| 4.906 | 0.035 | tINS | RF | 1 | u_p2b/u_p2b/u_mid_buf/n328_s0/COUT |
| 4.906 | 0.000 | tNET | FF | 2 | u_p2b/u_p2b/u_mid_buf/n329_s0/CIN |
| 4.941 | 0.035 | tINS | FF | 1 | u_p2b/u_p2b/u_mid_buf/n329_s0/COUT |
| 4.941 | 0.000 | tNET | FF | 2 | u_p2b/u_p2b/u_mid_buf/n330_s0/CIN |
| 4.976 | 0.035 | tINS | FF | 1 | u_p2b/u_p2b/u_mid_buf/n330_s0/COUT |
| 5.450 | 0.474 | tNET | FF | 1 | u_p2b/u_p2b/u_mid_buf/n342_s4/I0 |
| 5.967 | 0.517 | tINS | FF | 1 | u_p2b/u_p2b/u_mid_buf/n342_s4/F |
| 6.441 | 0.474 | tNET | FF | 1 | u_p2b/u_p2b/u_mid_buf/n342_s0/I3 |
| 6.812 | 0.371 | tINS | FF | 1 | u_p2b/u_p2b/u_mid_buf/n342_s0/F |
| 7.286 | 0.474 | tNET | FF | 1 | u_p2b/u_p2b/u_mid_buf/rFull_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 7.059 | 0.000 | u_pll/rpll_inst/CLKOUTD3.default_gen_clk | |||
| 8.236 | 1.177 | tCL | RR | 279 | u_pll/rpll_inst/CLKOUTD3 |
| 8.596 | 0.360 | tNET | RR | 1 | u_p2b/u_p2b/u_mid_buf/rFull_s0/CLK |
| 8.561 | -0.035 | tSu | 1 | u_p2b/u_p2b/u_mid_buf/rFull_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 7.059 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |
| Arrival Data Path Delay: | cell: 2.674, 46.501%; route: 2.844, 49.464%; tC2Q: 0.232, 4.035% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.360, 100.000% |