Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\data\ipcores\gw_jtag.v F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\Dsi_Test_pattern_2a18\fpga_proj\impl\gao\gw_gao_top.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.9.01 (64-bit) |
| Part Number | GW2A-LV18PG256C8/I7 |
| Device | GW2A-18 |
| Device Version | C |
| Created Time | Wed Mar 6 11:18:54 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | gw_gao |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.403s, Peak memory usage = 116.828MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 116.828MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.058s, Peak memory usage = 116.828MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.026s, Peak memory usage = 116.828MB Optimizing Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.062s, Peak memory usage = 116.828MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 116.828MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 116.828MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 116.828MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 116.828MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.043s, Peak memory usage = 116.828MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 116.828MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 116.828MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 2s, Peak memory usage = 143.637MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.054s, Peak memory usage = 143.637MB Generate output files: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.103s, Peak memory usage = 143.637MB |
| Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 2s, Peak memory usage = 143.637MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 170 |
| I/O Buf | 170 |
| IBUF | 169 |
| OBUF | 1 |
| Register | 982 |
| DFF | 338 |
| DFFR | 1 |
| DFFP | 3 |
| DFFPE | 33 |
| DFFC | 41 |
| DFFCE | 566 |
| LUT | 700 |
| LUT2 | 71 |
| LUT3 | 117 |
| LUT4 | 512 |
| MUX | 1 |
| MUX16 | 1 |
| ALU | 14 |
| ALU | 14 |
| INV | 4 |
| INV | 4 |
| BSRAM | 19 |
| SDPX9B | 19 |
| Black Box | 1 |
| GW_JTAG | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 726(712 LUT, 14 ALU) / 20736 | 4% |
| Register | 982 / 16173 | 7% |
| --Register as Latch | 0 / 16173 | 0% |
| --Register as FF | 982 / 16173 | 7% |
| BSRAM | 19 / 46 | 42% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| byte_clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | byte_clk_ibuf/I | ||
| u_icon_top/n19_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_icon_top/n19_s2/O | ||
| u_la0_top/n15_6 | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_la0_top/n15_s2/O |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | byte_clk | 100.000(MHz) | 175.994(MHz) | 6 | TOP |
| 2 | u_icon_top/n19_6 | 100.000(MHz) | 1349.527(MHz) | 1 | TOP |
| 3 | u_la0_top/n15_6 | 100.000(MHz) | 1349.527(MHz) | 1 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 4.318 |
| Data Arrival Time | 6.689 |
| Data Required Time | 11.007 |
| From | u_la0_top/u_ao_match_0/match_cnt_7_s1 |
| To | u_la0_top/triger_s0 |
| Launch Clk | byte_clk[R] |
| Latch Clk | byte_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | byte_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | byte_clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 451 | byte_clk_ibuf/O |
| 1.043 | 0.360 | tNET | RR | 1 | u_la0_top/u_ao_match_0/match_cnt_7_s1/CLK |
| 1.275 | 0.232 | tC2Q | RF | 2 | u_la0_top/u_ao_match_0/match_cnt_7_s1/Q |
| 1.748 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_match_0/n383_s5/I1 |
| 2.303 | 0.555 | tINS | FF | 1 | u_la0_top/u_ao_match_0/n383_s5/F |
| 2.777 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_match_0/n383_s3/I2 |
| 3.230 | 0.453 | tINS | FF | 4 | u_la0_top/u_ao_match_0/n383_s3/F |
| 3.704 | 0.474 | tNET | FF | 1 | u_la0_top/n6780_s2/I2 |
| 4.157 | 0.453 | tINS | FF | 3 | u_la0_top/n6780_s2/F |
| 4.631 | 0.474 | tNET | FF | 1 | u_la0_top/n6780_s1/I1 |
| 5.186 | 0.555 | tINS | FF | 3 | u_la0_top/n6780_s1/F |
| 5.660 | 0.474 | tNET | FF | 1 | u_la0_top/n6780_s0/I1 |
| 6.215 | 0.555 | tINS | FF | 1 | u_la0_top/n6780_s0/F |
| 6.689 | 0.474 | tNET | FF | 1 | u_la0_top/triger_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | byte_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | byte_clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 451 | byte_clk_ibuf/O |
| 11.042 | 0.360 | tNET | RR | 1 | u_la0_top/triger_s0/CLK |
| 11.007 | -0.035 | tSu | 1 | u_la0_top/triger_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
| Arrival Data Path Delay: | cell: 2.571, 45.529%; route: 2.844, 50.363%; tC2Q: 0.232, 4.108% |
| Required Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
Path 2
Path Summary:| Slack | 4.417 |
| Data Arrival Time | 6.590 |
| Data Required Time | 11.007 |
| From | u_la0_top/u_ao_match_0/match_cnt_7_s1 |
| To | u_la0_top/trigger_seq_start_s1 |
| Launch Clk | byte_clk[R] |
| Latch Clk | byte_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | byte_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | byte_clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 451 | byte_clk_ibuf/O |
| 1.043 | 0.360 | tNET | RR | 1 | u_la0_top/u_ao_match_0/match_cnt_7_s1/CLK |
| 1.275 | 0.232 | tC2Q | RF | 2 | u_la0_top/u_ao_match_0/match_cnt_7_s1/Q |
| 1.748 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_match_0/n383_s5/I1 |
| 2.303 | 0.555 | tINS | FF | 1 | u_la0_top/u_ao_match_0/n383_s5/F |
| 2.777 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_match_0/n383_s3/I2 |
| 3.230 | 0.453 | tINS | FF | 4 | u_la0_top/u_ao_match_0/n383_s3/F |
| 3.704 | 0.474 | tNET | FF | 1 | u_la0_top/n6780_s2/I2 |
| 4.157 | 0.453 | tINS | FF | 3 | u_la0_top/n6780_s2/F |
| 4.631 | 0.474 | tNET | FF | 1 | u_la0_top/n6780_s1/I1 |
| 5.186 | 0.555 | tINS | FF | 3 | u_la0_top/n6780_s1/F |
| 5.660 | 0.474 | tNET | FF | 1 | u_la0_top/trigger_seq_start_s3/I1 |
| 6.230 | 0.570 | tINS | FR | 1 | u_la0_top/trigger_seq_start_s3/F |
| 6.590 | 0.360 | tNET | RR | 1 | u_la0_top/trigger_seq_start_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | byte_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | byte_clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 451 | byte_clk_ibuf/O |
| 11.042 | 0.360 | tNET | RR | 1 | u_la0_top/trigger_seq_start_s1/CLK |
| 11.007 | -0.035 | tSu | 1 | u_la0_top/trigger_seq_start_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
| Arrival Data Path Delay: | cell: 2.586, 46.611%; route: 2.730, 49.207%; tC2Q: 0.232, 4.182% |
| Required Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
Path 3
Path Summary:| Slack | 4.420 |
| Data Arrival Time | 6.587 |
| Data Required Time | 11.007 |
| From | u_la0_top/u_ao_match_0/match_cnt_7_s1 |
| To | u_la0_top/u_ao_match_0/matched_s7 |
| Launch Clk | byte_clk[R] |
| Latch Clk | byte_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | byte_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | byte_clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 451 | byte_clk_ibuf/O |
| 1.043 | 0.360 | tNET | RR | 1 | u_la0_top/u_ao_match_0/match_cnt_7_s1/CLK |
| 1.275 | 0.232 | tC2Q | RF | 2 | u_la0_top/u_ao_match_0/match_cnt_7_s1/Q |
| 1.748 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_match_0/n383_s5/I1 |
| 2.303 | 0.555 | tINS | FF | 1 | u_la0_top/u_ao_match_0/n383_s5/F |
| 2.777 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_match_0/n383_s3/I2 |
| 3.230 | 0.453 | tINS | FF | 4 | u_la0_top/u_ao_match_0/n383_s3/F |
| 3.704 | 0.474 | tNET | FF | 1 | u_la0_top/n6780_s2/I2 |
| 4.157 | 0.453 | tINS | FF | 3 | u_la0_top/n6780_s2/F |
| 4.631 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_match_0/matched_s5/I2 |
| 5.084 | 0.453 | tINS | FF | 5 | u_la0_top/u_ao_match_0/matched_s5/F |
| 5.558 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_match_0/n350_s5/I1 |
| 6.113 | 0.555 | tINS | FF | 1 | u_la0_top/u_ao_match_0/n350_s5/F |
| 6.587 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_match_0/matched_s7/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | byte_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | byte_clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 451 | byte_clk_ibuf/O |
| 11.042 | 0.360 | tNET | RR | 1 | u_la0_top/u_ao_match_0/matched_s7/CLK |
| 11.007 | -0.035 | tSu | 1 | u_la0_top/u_ao_match_0/matched_s7 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
| Arrival Data Path Delay: | cell: 2.469, 44.527%; route: 2.844, 51.289%; tC2Q: 0.232, 4.184% |
| Required Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
Path 4
Path Summary:| Slack | 4.438 |
| Data Arrival Time | 6.569 |
| Data Required Time | 11.007 |
| From | u_la0_top/u_ao_match_0/match_cnt_7_s1 |
| To | u_la0_top/triger_level_cnt_0_s1 |
| Launch Clk | byte_clk[R] |
| Latch Clk | byte_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | byte_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | byte_clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 451 | byte_clk_ibuf/O |
| 1.043 | 0.360 | tNET | RR | 1 | u_la0_top/u_ao_match_0/match_cnt_7_s1/CLK |
| 1.275 | 0.232 | tC2Q | RF | 2 | u_la0_top/u_ao_match_0/match_cnt_7_s1/Q |
| 1.748 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_match_0/n383_s5/I1 |
| 2.303 | 0.555 | tINS | FF | 1 | u_la0_top/u_ao_match_0/n383_s5/F |
| 2.777 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_match_0/n383_s3/I2 |
| 3.230 | 0.453 | tINS | FF | 4 | u_la0_top/u_ao_match_0/n383_s3/F |
| 3.704 | 0.474 | tNET | FF | 1 | u_la0_top/n6780_s2/I2 |
| 4.157 | 0.453 | tINS | FF | 3 | u_la0_top/n6780_s2/F |
| 4.631 | 0.474 | tNET | FF | 1 | u_la0_top/n6780_s1/I1 |
| 5.186 | 0.555 | tINS | FF | 3 | u_la0_top/n6780_s1/F |
| 5.660 | 0.474 | tNET | FF | 1 | u_la0_top/triger_level_cnt_3_s3/I0 |
| 6.209 | 0.549 | tINS | FR | 4 | u_la0_top/triger_level_cnt_3_s3/F |
| 6.569 | 0.360 | tNET | RR | 1 | u_la0_top/triger_level_cnt_0_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | byte_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | byte_clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 451 | byte_clk_ibuf/O |
| 11.042 | 0.360 | tNET | RR | 1 | u_la0_top/triger_level_cnt_0_s1/CLK |
| 11.007 | -0.035 | tSu | 1 | u_la0_top/triger_level_cnt_0_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
| Arrival Data Path Delay: | cell: 2.565, 46.409%; route: 2.730, 49.393%; tC2Q: 0.232, 4.198% |
| Required Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
Path 5
Path Summary:| Slack | 4.438 |
| Data Arrival Time | 6.569 |
| Data Required Time | 11.007 |
| From | u_la0_top/u_ao_match_0/match_cnt_7_s1 |
| To | u_la0_top/triger_level_cnt_1_s1 |
| Launch Clk | byte_clk[R] |
| Latch Clk | byte_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | byte_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | byte_clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 451 | byte_clk_ibuf/O |
| 1.043 | 0.360 | tNET | RR | 1 | u_la0_top/u_ao_match_0/match_cnt_7_s1/CLK |
| 1.275 | 0.232 | tC2Q | RF | 2 | u_la0_top/u_ao_match_0/match_cnt_7_s1/Q |
| 1.748 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_match_0/n383_s5/I1 |
| 2.303 | 0.555 | tINS | FF | 1 | u_la0_top/u_ao_match_0/n383_s5/F |
| 2.777 | 0.474 | tNET | FF | 1 | u_la0_top/u_ao_match_0/n383_s3/I2 |
| 3.230 | 0.453 | tINS | FF | 4 | u_la0_top/u_ao_match_0/n383_s3/F |
| 3.704 | 0.474 | tNET | FF | 1 | u_la0_top/n6780_s2/I2 |
| 4.157 | 0.453 | tINS | FF | 3 | u_la0_top/n6780_s2/F |
| 4.631 | 0.474 | tNET | FF | 1 | u_la0_top/n6780_s1/I1 |
| 5.186 | 0.555 | tINS | FF | 3 | u_la0_top/n6780_s1/F |
| 5.660 | 0.474 | tNET | FF | 1 | u_la0_top/triger_level_cnt_3_s3/I0 |
| 6.209 | 0.549 | tINS | FR | 4 | u_la0_top/triger_level_cnt_3_s3/F |
| 6.569 | 0.360 | tNET | RR | 1 | u_la0_top/triger_level_cnt_1_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | byte_clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | byte_clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 451 | byte_clk_ibuf/O |
| 11.042 | 0.360 | tNET | RR | 1 | u_la0_top/triger_level_cnt_1_s1/CLK |
| 11.007 | -0.035 | tSu | 1 | u_la0_top/triger_level_cnt_1_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |
| Arrival Data Path Delay: | cell: 2.565, 46.409%; route: 2.730, 49.393%; tC2Q: 0.232, 4.198% |
| Required Clock Path Delay: | cell: 0.683, 65.468%; route: 0.360, 34.532% |