Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\MIPI_PIXEL_TO_BYTE\data\pixel_to_byte.v
D:\Programs\Gowin\Gowin_V1.9.9.01_x64\IDE\ipcore\MIPI_PIXEL_TO_BYTE\data\pixel_to_byte_wrap.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.01 (64-bit)
Part Number GW1NR-LV9MG100PC7/I6
Device GW1NR-9
Device Version C
Created Time Wed Mar 6 09:52:46 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Pixel_to_Byte_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.145s, Peak memory usage = 102.258MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 102.258MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 102.258MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 102.258MB
    Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 102.258MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 102.258MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 102.258MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 102.258MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 102.258MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 102.258MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 102.258MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 102.258MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.357s, Peak memory usage = 130.664MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.05s, Peak memory usage = 130.664MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.072s, Peak memory usage = 130.664MB
Total Time and Memory Usage CPU time = 0h 0m 0.621s, Elapsed time = 0h 0m 0.704s, Peak memory usage = 130.664MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 99
I/O Buf 99
    IBUF 30
    OBUF 69
Register 340
    DFF 12
    DFFS 2
    DFFR 8
    DFFRE 82
    DFFP 2
    DFFPE 2
    DFFC 24
    DFFCE 208
LUT 187
    LUT2 20
    LUT3 18
    LUT4 149
ALU 14
    ALU 14
SSRAM 16
    RAM16SDP4 16
INV 5
    INV 5

Resource Utilization Summary

Resource Usage Utilization
Logic 302(192 LUT, 14 ALU, 16 RAM16) / 8640 4%
Register 340 / 6741 6%
  --Register as Latch 0 / 6741 0%
  --Register as FF 340 / 6741 6%
BSRAM 0 / 26 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
I_PIXEL_CLK Base 20.000 50.0 0.000 10.000 I_PIXEL_CLK_ibuf/I
I_BYTE_CLK Base 20.000 50.0 0.000 10.000 I_BYTE_CLK_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 I_PIXEL_CLK 50.000(MHz) 115.440(MHz) 7 TOP
2 I_BYTE_CLK 50.000(MHz) 139.582(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 11.337
Data Arrival Time 9.632
Data Required Time 20.969
From u_p2b/u_mid_buf/rRPtrWsync_2_s0
To u_p2b/u_mid_buf/rFull_s0
Launch Clk I_PIXEL_CLK[R]
Latch Clk I_PIXEL_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_PIXEL_CLK
0.000 0.000 tCL RR 1 I_PIXEL_CLK_ibuf/I
0.728 0.728 tINS RR 188 I_PIXEL_CLK_ibuf/O
1.266 0.538 tNET RR 1 u_p2b/u_mid_buf/rRPtrWsync_2_s0/CLK
1.605 0.340 tC2Q RF 3 u_p2b/u_mid_buf/rRPtrWsync_2_s0/Q
2.317 0.711 tNET FF 1 u_p2b/u_mid_buf/wRPtrBinX_1_s0/I1
3.131 0.814 tINS FF 3 u_p2b/u_mid_buf/wRPtrBinX_1_s0/F
3.842 0.711 tNET FF 1 u_p2b/u_mid_buf/wRPtrBinX_0_s0/I1
4.657 0.814 tINS FF 1 u_p2b/u_mid_buf/wRPtrBinX_0_s0/F
5.368 0.711 tNET FF 2 u_p2b/u_mid_buf/n327_s0/I1
6.142 0.774 tINS FF 1 u_p2b/u_mid_buf/n327_s0/COUT
6.142 0.000 tNET FF 2 u_p2b/u_mid_buf/n328_s0/CIN
6.185 0.042 tINS FF 1 u_p2b/u_mid_buf/n328_s0/COUT
6.185 0.000 tNET FF 2 u_p2b/u_mid_buf/n329_s0/CIN
6.227 0.042 tINS FF 1 u_p2b/u_mid_buf/n329_s0/COUT
6.227 0.000 tNET FF 2 u_p2b/u_mid_buf/n330_s0/CIN
6.269 0.042 tINS FF 1 u_p2b/u_mid_buf/n330_s0/COUT
6.980 0.711 tNET FF 1 u_p2b/u_mid_buf/n342_s4/I0
7.745 0.765 tINS FF 1 u_p2b/u_mid_buf/n342_s4/F
8.456 0.711 tNET FF 1 u_p2b/u_mid_buf/n342_s0/I3
8.920 0.464 tINS FF 1 u_p2b/u_mid_buf/n342_s0/F
9.632 0.711 tNET FF 1 u_p2b/u_mid_buf/rFull_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 I_PIXEL_CLK
20.000 0.000 tCL RR 1 I_PIXEL_CLK_ibuf/I
20.728 0.728 tINS RR 188 I_PIXEL_CLK_ibuf/O
21.266 0.538 tNET RR 1 u_p2b/u_mid_buf/rFull_s0/CLK
20.969 -0.296 tSu 1 u_p2b/u_mid_buf/rFull_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.728, 57.491%; route: 0.538, 42.509%
Arrival Data Path Delay: cell: 3.758, 44.923%; route: 4.268, 51.017%; tC2Q: 0.340, 4.060%
Required Clock Path Delay: cell: 0.728, 57.491%; route: 0.538, 42.509%

Path 2

Path Summary:
Slack 12.836
Data Arrival Time 8.133
Data Required Time 20.969
From u_p2b/u_mid_buf/rWPtrRsync_2_s0
To u_p2b/u_mid_buf/rEmpty_s0
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.728 0.728 tINS RR 168 I_BYTE_CLK_ibuf/O
1.266 0.538 tNET RR 1 u_p2b/u_mid_buf/rWPtrRsync_2_s0/CLK
1.605 0.340 tC2Q RF 3 u_p2b/u_mid_buf/rWPtrRsync_2_s0/Q
2.317 0.711 tNET FF 1 u_p2b/u_mid_buf/wWPtrBinX_1_s0/I1
3.131 0.814 tINS FF 4 u_p2b/u_mid_buf/wWPtrBinX_1_s0/F
3.842 0.711 tNET FF 1 u_p2b/u_mid_buf/wWPtrBinX_0_s0/I1
4.657 0.814 tINS FF 2 u_p2b/u_mid_buf/wWPtrBinX_0_s0/F
5.368 0.711 tNET FF 2 u_p2b/u_mid_buf/n308_s0/I0
6.078 0.710 tINS FF 1 u_p2b/u_mid_buf/n308_s0/COUT
6.078 0.000 tNET FF 2 u_p2b/u_mid_buf/n309_s0/CIN
6.120 0.042 tINS FF 1 u_p2b/u_mid_buf/n309_s0/COUT
6.120 0.000 tNET FF 2 u_p2b/u_mid_buf/n310_s0/CIN
6.162 0.042 tINS FF 1 u_p2b/u_mid_buf/n310_s0/COUT
6.162 0.000 tNET FF 2 u_p2b/u_mid_buf/n311_s0/CIN
6.205 0.042 tINS FF 1 u_p2b/u_mid_buf/n311_s0/COUT
6.205 0.000 tNET FF 2 u_p2b/u_mid_buf/n312_s0/CIN
6.247 0.042 tINS FF 1 u_p2b/u_mid_buf/n312_s0/COUT
6.958 0.711 tNET FF 1 u_p2b/u_mid_buf/n314_s0/I3
7.422 0.464 tINS FF 1 u_p2b/u_mid_buf/n314_s0/F
8.133 0.711 tNET FF 1 u_p2b/u_mid_buf/rEmpty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 I_BYTE_CLK
20.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
20.728 0.728 tINS RR 168 I_BYTE_CLK_ibuf/O
21.266 0.538 tNET RR 1 u_p2b/u_mid_buf/rEmpty_s0/CLK
20.969 -0.296 tSu 1 u_p2b/u_mid_buf/rEmpty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.728, 57.491%; route: 0.538, 42.509%
Arrival Data Path Delay: cell: 2.971, 43.266%; route: 3.557, 51.789%; tC2Q: 0.340, 4.945%
Required Clock Path Delay: cell: 0.728, 57.491%; route: 0.538, 42.509%

Path 3

Path Summary:
Slack 13.636
Data Arrival Time 7.333
Data Required Time 20.969
From u_p2b/u_mid_buf/rWPtrRsync_2_s0
To u_p2b/u_mid_buf/rRdDiff_4_s0
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.728 0.728 tINS RR 168 I_BYTE_CLK_ibuf/O
1.266 0.538 tNET RR 1 u_p2b/u_mid_buf/rWPtrRsync_2_s0/CLK
1.605 0.340 tC2Q RF 3 u_p2b/u_mid_buf/rWPtrRsync_2_s0/Q
2.317 0.711 tNET FF 1 u_p2b/u_mid_buf/wWPtrBinX_1_s0/I1
3.131 0.814 tINS FF 4 u_p2b/u_mid_buf/wWPtrBinX_1_s0/F
3.842 0.711 tNET FF 1 u_p2b/u_mid_buf/wWPtrBinX_0_s0/I1
4.657 0.814 tINS FF 2 u_p2b/u_mid_buf/wWPtrBinX_0_s0/F
5.368 0.711 tNET FF 2 u_p2b/u_mid_buf/wRdDiff_0_s/I0
6.078 0.710 tINS FF 1 u_p2b/u_mid_buf/wRdDiff_0_s/COUT
6.078 0.000 tNET FF 2 u_p2b/u_mid_buf/wRdDiff_1_s/CIN
6.120 0.042 tINS FF 1 u_p2b/u_mid_buf/wRdDiff_1_s/COUT
6.120 0.000 tNET FF 2 u_p2b/u_mid_buf/wRdDiff_2_s/CIN
6.162 0.042 tINS FF 1 u_p2b/u_mid_buf/wRdDiff_2_s/COUT
6.162 0.000 tNET FF 2 u_p2b/u_mid_buf/wRdDiff_3_s/CIN
6.205 0.042 tINS FF 1 u_p2b/u_mid_buf/wRdDiff_3_s/COUT
6.205 0.000 tNET FF 2 u_p2b/u_mid_buf/wRdDiff_4_s/CIN
6.622 0.417 tINS FF 1 u_p2b/u_mid_buf/wRdDiff_4_s/SUM
7.333 0.711 tNET FF 1 u_p2b/u_mid_buf/rRdDiff_4_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 I_BYTE_CLK
20.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
20.728 0.728 tINS RR 168 I_BYTE_CLK_ibuf/O
21.266 0.538 tNET RR 1 u_p2b/u_mid_buf/rRdDiff_4_s0/CLK
20.969 -0.296 tSu 1 u_p2b/u_mid_buf/rRdDiff_4_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.728, 57.491%; route: 0.538, 42.509%
Arrival Data Path Delay: cell: 2.882, 47.507%; route: 2.845, 46.896%; tC2Q: 0.340, 5.597%
Required Clock Path Delay: cell: 0.728, 57.491%; route: 0.538, 42.509%

Path 4

Path Summary:
Slack 13.678
Data Arrival Time 7.291
Data Required Time 20.969
From u_p2b/u_mid_buf/rWPtrRsync_2_s0
To u_p2b/u_mid_buf/rRdDiff_3_s0
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.728 0.728 tINS RR 168 I_BYTE_CLK_ibuf/O
1.266 0.538 tNET RR 1 u_p2b/u_mid_buf/rWPtrRsync_2_s0/CLK
1.605 0.340 tC2Q RF 3 u_p2b/u_mid_buf/rWPtrRsync_2_s0/Q
2.317 0.711 tNET FF 1 u_p2b/u_mid_buf/wWPtrBinX_1_s0/I1
3.131 0.814 tINS FF 4 u_p2b/u_mid_buf/wWPtrBinX_1_s0/F
3.842 0.711 tNET FF 1 u_p2b/u_mid_buf/wWPtrBinX_0_s0/I1
4.657 0.814 tINS FF 2 u_p2b/u_mid_buf/wWPtrBinX_0_s0/F
5.368 0.711 tNET FF 2 u_p2b/u_mid_buf/wRdDiff_0_s/I0
6.078 0.710 tINS FF 1 u_p2b/u_mid_buf/wRdDiff_0_s/COUT
6.078 0.000 tNET FF 2 u_p2b/u_mid_buf/wRdDiff_1_s/CIN
6.120 0.042 tINS FF 1 u_p2b/u_mid_buf/wRdDiff_1_s/COUT
6.120 0.000 tNET FF 2 u_p2b/u_mid_buf/wRdDiff_2_s/CIN
6.162 0.042 tINS FF 1 u_p2b/u_mid_buf/wRdDiff_2_s/COUT
6.162 0.000 tNET FF 2 u_p2b/u_mid_buf/wRdDiff_3_s/CIN
6.579 0.417 tINS FF 1 u_p2b/u_mid_buf/wRdDiff_3_s/SUM
7.291 0.711 tNET FF 1 u_p2b/u_mid_buf/rRdDiff_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 I_BYTE_CLK
20.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
20.728 0.728 tINS RR 168 I_BYTE_CLK_ibuf/O
21.266 0.538 tNET RR 1 u_p2b/u_mid_buf/rRdDiff_3_s0/CLK
20.969 -0.296 tSu 1 u_p2b/u_mid_buf/rRdDiff_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.728, 57.491%; route: 0.538, 42.509%
Arrival Data Path Delay: cell: 2.840, 47.139%; route: 2.845, 47.224%; tC2Q: 0.340, 5.637%
Required Clock Path Delay: cell: 0.728, 57.491%; route: 0.538, 42.509%

Path 5

Path Summary:
Slack 13.721
Data Arrival Time 7.249
Data Required Time 20.969
From u_p2b/u_mid_buf/rWPtrRsync_2_s0
To u_p2b/u_mid_buf/rRdDiff_2_s0
Launch Clk I_BYTE_CLK[R]
Latch Clk I_BYTE_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 I_BYTE_CLK
0.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
0.728 0.728 tINS RR 168 I_BYTE_CLK_ibuf/O
1.266 0.538 tNET RR 1 u_p2b/u_mid_buf/rWPtrRsync_2_s0/CLK
1.605 0.340 tC2Q RF 3 u_p2b/u_mid_buf/rWPtrRsync_2_s0/Q
2.317 0.711 tNET FF 1 u_p2b/u_mid_buf/wWPtrBinX_1_s0/I1
3.131 0.814 tINS FF 4 u_p2b/u_mid_buf/wWPtrBinX_1_s0/F
3.842 0.711 tNET FF 1 u_p2b/u_mid_buf/wWPtrBinX_0_s0/I1
4.657 0.814 tINS FF 2 u_p2b/u_mid_buf/wWPtrBinX_0_s0/F
5.368 0.711 tNET FF 2 u_p2b/u_mid_buf/wRdDiff_0_s/I0
6.078 0.710 tINS FF 1 u_p2b/u_mid_buf/wRdDiff_0_s/COUT
6.078 0.000 tNET FF 2 u_p2b/u_mid_buf/wRdDiff_1_s/CIN
6.120 0.042 tINS FF 1 u_p2b/u_mid_buf/wRdDiff_1_s/COUT
6.120 0.000 tNET FF 2 u_p2b/u_mid_buf/wRdDiff_2_s/CIN
6.537 0.417 tINS FF 1 u_p2b/u_mid_buf/wRdDiff_2_s/SUM
7.249 0.711 tNET FF 1 u_p2b/u_mid_buf/rRdDiff_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 I_BYTE_CLK
20.000 0.000 tCL RR 1 I_BYTE_CLK_ibuf/I
20.728 0.728 tINS RR 168 I_BYTE_CLK_ibuf/O
21.266 0.538 tNET RR 1 u_p2b/u_mid_buf/rRdDiff_2_s0/CLK
20.969 -0.296 tSu 1 u_p2b/u_mid_buf/rRdDiff_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.728, 57.491%; route: 0.538, 42.509%
Arrival Data Path Delay: cell: 2.798, 46.765%; route: 2.845, 47.559%; tC2Q: 0.340, 5.676%
Required Clock Path Delay: cell: 0.728, 57.491%; route: 0.538, 42.509%