PnR Messages

Report Title PnR Report
Design File F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_Test_Pattern_1nr9\fpga_proj\impl\gwsynthesis\Dsi_test_pattern.vg
Gao Design File F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_Test_Pattern_1nr9\fpga_proj\impl\gao\gao.v
Physical Constraints File F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_Test_Pattern_1nr9\fpga_proj\src\dsi_test.cst
Timing Constraints File F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_Test_Pattern_1nr9\fpga_proj\src\dsi_test.sdc
Tool Version V1.9.9.01 (64-bit)
Part Number GW1NR-LV9MG100PC7/I6
Device GW1NR-9
Device Version C
Created Time Wed Mar 6 09:56:51 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

PnR Details

Place & Route Process Running placement: Placement Phase 0: CPU time = 0h 0m 0.575s, Elapsed time = 0h 0m 0.575s Placement Phase 1: CPU time = 0h 0m 0.064s, Elapsed time = 0h 0m 0.064s Placement Phase 2: CPU time = 0h 0m 0.575s, Elapsed time = 0h 0m 0.575s Placement Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s Placement Phase GAO : CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.061s Total Placement: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 2s Running routing: Routing Phase 0: CPU time = 0h 0m 0.002s, Elapsed time = 0h 0m 0.002s Routing Phase 1: CPU time = 0h 0m 0.77s, Elapsed time = 0h 0m 0.77s Routing Phase 2: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s Routing Phase 3: CPU time = 0h 0m 0.873s, Elapsed time = 0h 0m 0.873s Total Routing: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s Generate output files: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
Total Time and Memory Usage CPU time = 0h 0m 8s, Elapsed time = 0h 0m 8s, Peak memory usage = 422MB

Resource

Resource Usage Summary:

Resource Usage Utilization
Logic 3043/8640 36%
    --LUT,ALU,ROM16 2923(2863 LUT, 60 ALU, 0 ROM16) -
    --SSRAM(RAM16) 20 -
Register 1211/6741 18%
    --Logic Register as Latch 0/6480 0%
    --Logic Register as FF 1210/6480 19%
    --I/O Register as Latch 0/261 0%
    --I/O Register as FF 1/261 <1%
CLS 1937/4320 45%
I/O Port 15 -
I/O Buf 10 -
    --Input Buf 2 -
    --Output Buf 8 -
    --Inout Buf 0 -
IOLOGIC 5 OSER16
 11%
BSRAM 2 SDPX9B
 8%
DSP 00%
PLL 1/2 50%
DCS 0/8 0%
DQCE 0/24 0%
OSC 0/1 0%
User Flash 0/1 0%
CLKDIV 0/8 0%
DLLDLY 0/8 0%
DHCEN 0/8 0%
DHCENC 0/4 0%

GAO Resource Usage Summary:

Resource Usage
Logic 479
    --LUT,ALU,ROM16 479(466 LUT, 13 ALU, 0 ROM16)
    --SSRAM(RAM16) 0
Register 523
I/O Port 77
I/O Buf 4
    --Input Buf 3
    --Output Buf 1
    --Inout Buf 0
BSRAM 4

I/O Bank Usage Summary:

I/O Bank Usage
bank 0 0/12(0%)
bank 1 5/22(22%)
bank 2 10/32(31%)
bank 3 0/21(0%)

Global Clock Usage Summary:

Global Clock Usage
PRIMARY 2/8(25%)
LW 7/8(88%)
GCLK_PIN 1/5(20%)
PLL 1/2(50%)
CLKDIV 0/8(0%)
DLLDLY 0/8(0%)

Global Clock Signals:

Signal Global Clock Location
byte_clk PRIMARY TR TL BR BL
pixel_clk PRIMARY TL BR BL
RESET_N_d LW -
pixel_de LW -
n158_6 LW -
u_dsi_tx/u_tx/u_dsi_tx/n512_3 LW -
u_dsi_tx/u_tx/u_dsi_tx/n4769_3 LW -
u_dsi_tx/u_tx/u_dsi_tx/n10866_5 LW -
u_dsi_tx/u_tx/u_dsi_tx/rRegData_125_10 LW -
bit_clk HCLK BOTTOM[1]
bit_clk_90 HCLK BOTTOM[0]

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor BankVccio
RESET_N B9/1 Y in IOT45[A] LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
OSC_50M C9/1 Y in IOR5[A] LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
TX_CLK_P TX_CLK_N J6,H6/2 Y out IOB29 MIPI 3.5 NA NA NA NA NA NA NA 1.2
TX_D0_P TX_D0_N K10,K9/2 Y out IOB41 MIPI 3.5 NA NA NA NA NA NA NA 1.2
TX_D1_P TX_D1_N F6,G6/2 Y out IOB35 MIPI 3.5 NA NA NA NA NA NA NA 1.2
TX_D2_P TX_D2_N F7,G7/2 Y out IOB39 MIPI 3.5 NA NA NA NA NA NA NA 1.2
TX_D3_P TX_D3_N K7,K8/2 Y out IOB31 MIPI 3.5 NA NA NA NA NA NA NA 1.2
led[0] F10/1 Y out IOR16[B] LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8
led[1] H8/1 Y out IOR18[B] LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8
led[2] G10/1 Y out IOR21[B] LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8

All Package Pins:

Loc./Bank Signal Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor Bank Vccio
D4/3 - in IOT6[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A3/3 - in IOT8[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A4/3 - in IOT8[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C4/3 - in IOT11[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B4/3 - in IOT11[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D5/0 - in IOT13[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D6/0 - in IOT13[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C5/0 - in IOT17[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B5/0 - in IOT17[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C6/0 - in IOT21[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B6/0 - in IOT21[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A6/0 - in IOT27[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A7/0 - in IOT27[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
E6/0 - in IOT29[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
E7/0 - in IOT29[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C7/0 - in IOT33[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B7/0 - in IOT33[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B8/1 - in IOT39[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C8/1 - in IOT39[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D7/1 - in IOT41[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D8/1 - in IOT41[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B9/1 RESET_N in IOT45[A] LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
A10/1 - in IOT45[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
H1/2 - in IOB3[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
K1/2 - in IOB4[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
K2/2 - in IOB4[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
G4/2 - in IOB8[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
G3/2 - in IOB8[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
J3/2 - in IOB11[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
H3/2 - in IOB11[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
E4/2 - in IOB13[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
F4/2 - in IOB13[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
K3/2 - in IOB15[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
K4/2 - in IOB15[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
J4/2 - in IOB17[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
H4/2 - in IOB17[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
K5/2 - in IOB21[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
K6/2 - in IOB21[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
H5/2 - in IOB23[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
G5/2 - in IOB23[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
F5/2 - in IOB28[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
E5/2 - in IOB28[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
J6/2 TX_CLK_P out IOB29[A] MIPI 3.5 NA NA NA NA NA NA NA 1.2
H6/2 TX_CLK_N out IOB29[B] MIPI 3.5 NA NA NA NA NA NA NA 1.2
K7/2 TX_D3_P out IOB31[A] MIPI 3.5 NA NA NA NA NA NA NA 1.2
K8/2 TX_D3_N out IOB31[B] MIPI 3.5 NA NA NA NA NA NA NA 1.2
J7/2 - in IOB33[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
H7/2 - in IOB33[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
F6/2 TX_D1_P out IOB35[A] MIPI 3.5 NA NA NA NA NA NA NA 1.2
G6/2 TX_D1_N out IOB35[B] MIPI 3.5 NA NA NA NA NA NA NA 1.2
F7/2 TX_D2_P out IOB39[A] MIPI 3.5 NA NA NA NA NA NA NA 1.2
G7/2 TX_D2_N out IOB39[B] MIPI 3.5 NA NA NA NA NA NA NA 1.2
K10/2 TX_D0_P out IOB41[A] MIPI 3.5 NA NA NA NA NA NA NA 1.2
K9/2 TX_D0_N out IOB41[B] MIPI 3.5 NA NA NA NA NA NA NA 1.2
J10/2 - in IOB43[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
B2/3 - in IOL4[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B1/3 - in IOL5[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B3/3 - in IOL5[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C1/3 - in IOL7[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C2/3 - in IOL8[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C3/3 - in IOL9[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
E2/3 tms_pad_i in IOL11[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
E3/3 tck_pad_i in IOL11[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
F3/3 tdi_pad_i in IOL12[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
F2/3 tdo_pad_o out IOL13[A] LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
D3/3 - in IOL13[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D1/3 - in IOL14[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
F1/3 - in IOL15[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D2/3 - in IOL16[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
G2/3 - in IOL21[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
G1/3 - in IOL22[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
H2/3 - in IOL25[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C10/1 - in IOR2[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B10/1 - in IOR3[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C9/1 OSC_50M in IOR5[A] LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
D9/1 - in IOR5[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D10/1 - in IOR7[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
E8/1 - in IOR9[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
F9/1 - in IOR11[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
E10/1 - in IOR12[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
G9/1 - in IOR14[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
F10/1 led[0] out IOR16[B] LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8
F8/1 - in IOR17[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
G8/1 - in IOR17[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
H8/1 led[1] out IOR18[B] LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8
G10/1 led[2] out IOR21[B] LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8
H9/1 - in IOR24[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
H10/1 - in IOR25[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8