Synthesis Messages

Report Title GowinSynthesis Report
Design File F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_Test_Pattern_1nr9\fpga_proj\src\gowin_rpll\gowin_rpll.v
F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_Test_Pattern_1nr9\fpga_proj\src\mipi_dsi_tx\mipi_dsi_tx.v
F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_Test_Pattern_1nr9\fpga_proj\src\mipi_tx\mipi_tx.v
F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_Test_Pattern_1nr9\fpga_proj\src\pixel_to_byte\pixel_to_byte.v
F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_Test_Pattern_1nr9\fpga_proj\src\testpattern.v
F:\mySrc\MIPI_modular_IP\Ref_Design\Saved\DSI_Test_Pattern_1nr9\fpga_proj\src\top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.01 (64-bit)
Part Number GW1NR-LV9MG100PC7/I6
Device GW1NR-9
Device Version C
Created Time Wed Mar 6 09:53:57 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module DsiTest_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.484s, Elapsed time = 0h 0m 0.486s, Peak memory usage = 401.082MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.043s, Peak memory usage = 401.082MB
    Optimizing Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.046s, Peak memory usage = 401.082MB
    Optimizing Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.074s, Peak memory usage = 401.082MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 401.082MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 401.082MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 401.082MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 401.082MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.057s, Peak memory usage = 401.082MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 401.082MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 401.082MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.89s, Elapsed time = 0h 0m 0.877s, Peak memory usage = 401.082MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.075s, Peak memory usage = 401.082MB
Generate output files:
    CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.22s, Peak memory usage = 401.082MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 401.082MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 15
I/O Buf 10
    IBUF 2
    OBUF 3
    MIPI_OBUF_A 5
Register 1211
    DFF 220
    DFFE 236
    DFFS 8
    DFFSE 16
    DFFR 118
    DFFRE 108
    DFFP 10
    DFFPE 20
    DFFC 187
    DFFCE 288
LUT 2854
    LUT2 213
    LUT3 1105
    LUT4 1536
ALU 52
    ALU 52
SSRAM 20
    RAM16SDP4 20
INV 15
    INV 15
IOLOGIC 5
    OSER16 5
BSRAM 2
    SDPX9B 2
CLOCK 1
    rPLL 1

Resource Utilization Summary

Resource Usage Utilization
Logic 3041(2869 LUT, 52 ALU, 20 RAM16) / 8640 36%
Register 1211 / 6741 18%
  --Register as Latch 0 / 6741 0%
  --Register as FF 1211 / 6741 18%
BSRAM 2 / 26 8%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
OSC_50M Base 20.000 50.0 0.000 10.000 OSC_50M_ibuf/I
u_pll/rpll_inst/CLKOUT.default_gen_clk Generated 2.353 425.0 0.000 1.176 OSC_50M_ibuf/I OSC_50M u_pll/rpll_inst/CLKOUT
u_pll/rpll_inst/CLKOUTP.default_gen_clk Generated 2.353 425.0 0.588 1.765 OSC_50M_ibuf/I OSC_50M u_pll/rpll_inst/CLKOUTP
u_pll/rpll_inst/CLKOUTD.default_gen_clk Generated 18.824 53.1 0.000 9.412 OSC_50M_ibuf/I OSC_50M u_pll/rpll_inst/CLKOUTD
u_pll/rpll_inst/CLKOUTD3.default_gen_clk Generated 7.059 141.7 0.000 3.529 OSC_50M_ibuf/I OSC_50M u_pll/rpll_inst/CLKOUTD3

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 u_pll/rpll_inst/CLKOUTD.default_gen_clk 53.125(MHz) 75.160(MHz) 9 TOP
2 u_pll/rpll_inst/CLKOUTD3.default_gen_clk 141.667(MHz) 115.440(MHz) 7 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -1.604
Data Arrival Time 10.411
Data Required Time 8.807
From u_p2b/u_p2b/u_mid_buf/rRPtrWsync_2_s0
To u_p2b/u_p2b/u_mid_buf/rFull_s0
Launch Clk u_pll/rpll_inst/CLKOUTD3.default_gen_clk[R]
Latch Clk u_pll/rpll_inst/CLKOUTD3.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 u_pll/rpll_inst/CLKOUTD3.default_gen_clk
1.506 1.506 tCL RR 353 u_pll/rpll_inst/CLKOUTD3
2.044 0.538 tNET RR 1 u_p2b/u_p2b/u_mid_buf/rRPtrWsync_2_s0/CLK
2.384 0.340 tC2Q RF 3 u_p2b/u_p2b/u_mid_buf/rRPtrWsync_2_s0/Q
3.095 0.711 tNET FF 1 u_p2b/u_p2b/u_mid_buf/wRPtrBinX_1_s0/I1
3.910 0.814 tINS FF 3 u_p2b/u_p2b/u_mid_buf/wRPtrBinX_1_s0/F
4.621 0.711 tNET FF 1 u_p2b/u_p2b/u_mid_buf/wRPtrBinX_0_s0/I1
5.435 0.814 tINS FF 1 u_p2b/u_p2b/u_mid_buf/wRPtrBinX_0_s0/F
6.147 0.711 tNET FF 2 u_p2b/u_p2b/u_mid_buf/n327_s0/I1
6.921 0.774 tINS FF 1 u_p2b/u_p2b/u_mid_buf/n327_s0/COUT
6.921 0.000 tNET FF 2 u_p2b/u_p2b/u_mid_buf/n328_s0/CIN
6.963 0.042 tINS FF 1 u_p2b/u_p2b/u_mid_buf/n328_s0/COUT
6.963 0.000 tNET FF 2 u_p2b/u_p2b/u_mid_buf/n329_s0/CIN
7.006 0.042 tINS FF 1 u_p2b/u_p2b/u_mid_buf/n329_s0/COUT
7.006 0.000 tNET FF 2 u_p2b/u_p2b/u_mid_buf/n330_s0/CIN
7.048 0.042 tINS FF 1 u_p2b/u_p2b/u_mid_buf/n330_s0/COUT
7.759 0.711 tNET FF 1 u_p2b/u_p2b/u_mid_buf/n342_s4/I0
8.524 0.765 tINS FF 1 u_p2b/u_p2b/u_mid_buf/n342_s4/F
9.235 0.711 tNET FF 1 u_p2b/u_p2b/u_mid_buf/n342_s0/I3
9.699 0.464 tINS FF 1 u_p2b/u_p2b/u_mid_buf/n342_s0/F
10.411 0.711 tNET FF 1 u_p2b/u_p2b/u_mid_buf/rFull_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
7.059 0.000 u_pll/rpll_inst/CLKOUTD3.default_gen_clk
8.565 1.506 tCL RR 353 u_pll/rpll_inst/CLKOUTD3
9.103 0.538 tNET RR 1 u_p2b/u_p2b/u_mid_buf/rFull_s0/CLK
8.807 -0.296 tSu 1 u_p2b/u_p2b/u_mid_buf/rFull_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 7.059
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.758, 44.923%; route: 4.268, 51.017%; tC2Q: 0.340, 4.060%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 2

Path Summary:
Slack -0.566
Data Arrival Time 39.915
Data Required Time 39.349
From u_p2b/u_p2b/rCtrlSync_3_s0
To u_p2b/u_p2b/GEN_FOR_I[3].u_pulse_dly/rCnt_0_s3
Launch Clk u_pll/rpll_inst/CLKOUTD3.default_gen_clk[R]
Latch Clk u_pll/rpll_inst/CLKOUTD.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
35.294 0.000 u_pll/rpll_inst/CLKOUTD3.default_gen_clk
36.801 1.506 tCL RR 353 u_pll/rpll_inst/CLKOUTD3
37.339 0.538 tNET RR 1 u_p2b/u_p2b/rCtrlSync_3_s0/CLK
37.678 0.340 tC2Q RF 3 u_p2b/u_p2b/rCtrlSync_3_s0/Q
38.390 0.711 tNET FF 1 u_p2b/u_p2b/GEN_FOR_I[3].u_pulse_dly/n32_s6/I1
39.204 0.814 tINS FF 1 u_p2b/u_p2b/GEN_FOR_I[3].u_pulse_dly/n32_s6/F
39.915 0.711 tNET FF 1 u_p2b/u_p2b/GEN_FOR_I[3].u_pulse_dly/rCnt_0_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
37.647 0.000 u_pll/rpll_inst/CLKOUTD.default_gen_clk
39.137 1.490 tCL RR 887 u_pll/rpll_inst/CLKOUTD
39.675 0.538 tNET RR 1 u_p2b/u_p2b/GEN_FOR_I[3].u_pulse_dly/rCnt_0_s3/CLK
39.645 -0.030 tUnc u_p2b/u_p2b/GEN_FOR_I[3].u_pulse_dly/rCnt_0_s3
39.349 -0.296 tSu 1 u_p2b/u_p2b/GEN_FOR_I[3].u_pulse_dly/rCnt_0_s3
Path Statistics:
Clock Skew: -0.016
Setup Relationship: 2.353
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 0.814, 31.605%; route: 1.423, 55.214%; tC2Q: 0.340, 13.181%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 3

Path Summary:
Slack -0.566
Data Arrival Time 39.915
Data Required Time 39.349
From u_p2b/u_p2b/rCtrlSync_2_s0
To u_p2b/u_p2b/GEN_FOR_I[1].u_pulse_dly/rCnt_0_s3
Launch Clk u_pll/rpll_inst/CLKOUTD3.default_gen_clk[R]
Latch Clk u_pll/rpll_inst/CLKOUTD.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
35.294 0.000 u_pll/rpll_inst/CLKOUTD3.default_gen_clk
36.801 1.506 tCL RR 353 u_pll/rpll_inst/CLKOUTD3
37.339 0.538 tNET RR 1 u_p2b/u_p2b/rCtrlSync_2_s0/CLK
37.678 0.340 tC2Q RF 3 u_p2b/u_p2b/rCtrlSync_2_s0/Q
38.390 0.711 tNET FF 1 u_p2b/u_p2b/GEN_FOR_I[1].u_pulse_dly/n32_s6/I1
39.204 0.814 tINS FF 1 u_p2b/u_p2b/GEN_FOR_I[1].u_pulse_dly/n32_s6/F
39.915 0.711 tNET FF 1 u_p2b/u_p2b/GEN_FOR_I[1].u_pulse_dly/rCnt_0_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
37.647 0.000 u_pll/rpll_inst/CLKOUTD.default_gen_clk
39.137 1.490 tCL RR 887 u_pll/rpll_inst/CLKOUTD
39.675 0.538 tNET RR 1 u_p2b/u_p2b/GEN_FOR_I[1].u_pulse_dly/rCnt_0_s3/CLK
39.645 -0.030 tUnc u_p2b/u_p2b/GEN_FOR_I[1].u_pulse_dly/rCnt_0_s3
39.349 -0.296 tSu 1 u_p2b/u_p2b/GEN_FOR_I[1].u_pulse_dly/rCnt_0_s3
Path Statistics:
Clock Skew: -0.016
Setup Relationship: 2.353
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 0.814, 31.605%; route: 1.423, 55.214%; tC2Q: 0.340, 13.181%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 4

Path Summary:
Slack -0.361
Data Arrival Time 39.710
Data Required Time 39.349
From u_p2b/u_p2b/rCtrlSync_3_s0
To u_p2b/u_p2b/GEN_FOR_I[2].u_pulse_dly/rCnt_0_s3
Launch Clk u_pll/rpll_inst/CLKOUTD3.default_gen_clk[R]
Latch Clk u_pll/rpll_inst/CLKOUTD.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
35.294 0.000 u_pll/rpll_inst/CLKOUTD3.default_gen_clk
36.801 1.506 tCL RR 353 u_pll/rpll_inst/CLKOUTD3
37.339 0.538 tNET RR 1 u_p2b/u_p2b/rCtrlSync_3_s0/CLK
37.678 0.340 tC2Q RF 3 u_p2b/u_p2b/rCtrlSync_3_s0/Q
38.390 0.711 tNET FF 1 u_p2b/u_p2b/GEN_FOR_I[2].u_pulse_dly/n32_s6/I2
38.999 0.609 tINS FF 1 u_p2b/u_p2b/GEN_FOR_I[2].u_pulse_dly/n32_s6/F
39.710 0.711 tNET FF 1 u_p2b/u_p2b/GEN_FOR_I[2].u_pulse_dly/rCnt_0_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
37.647 0.000 u_pll/rpll_inst/CLKOUTD.default_gen_clk
39.137 1.490 tCL RR 887 u_pll/rpll_inst/CLKOUTD
39.675 0.538 tNET RR 1 u_p2b/u_p2b/GEN_FOR_I[2].u_pulse_dly/rCnt_0_s3/CLK
39.645 -0.030 tUnc u_p2b/u_p2b/GEN_FOR_I[2].u_pulse_dly/rCnt_0_s3
39.349 -0.296 tSu 1 u_p2b/u_p2b/GEN_FOR_I[2].u_pulse_dly/rCnt_0_s3
Path Statistics:
Clock Skew: -0.016
Setup Relationship: 2.353
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 0.609, 25.685%; route: 1.423, 59.994%; tC2Q: 0.340, 14.321%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 5

Path Summary:
Slack -0.361
Data Arrival Time 39.710
Data Required Time 39.349
From u_p2b/u_p2b/rCtrlSync_2_s0
To u_p2b/u_p2b/GEN_FOR_I[0].u_pulse_dly/rCnt_0_s3
Launch Clk u_pll/rpll_inst/CLKOUTD3.default_gen_clk[R]
Latch Clk u_pll/rpll_inst/CLKOUTD.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
35.294 0.000 u_pll/rpll_inst/CLKOUTD3.default_gen_clk
36.801 1.506 tCL RR 353 u_pll/rpll_inst/CLKOUTD3
37.339 0.538 tNET RR 1 u_p2b/u_p2b/rCtrlSync_2_s0/CLK
37.678 0.340 tC2Q RF 3 u_p2b/u_p2b/rCtrlSync_2_s0/Q
38.390 0.711 tNET FF 1 u_p2b/u_p2b/GEN_FOR_I[0].u_pulse_dly/n32_s6/I2
38.999 0.609 tINS FF 1 u_p2b/u_p2b/GEN_FOR_I[0].u_pulse_dly/n32_s6/F
39.710 0.711 tNET FF 1 u_p2b/u_p2b/GEN_FOR_I[0].u_pulse_dly/rCnt_0_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
37.647 0.000 u_pll/rpll_inst/CLKOUTD.default_gen_clk
39.137 1.490 tCL RR 887 u_pll/rpll_inst/CLKOUTD
39.675 0.538 tNET RR 1 u_p2b/u_p2b/GEN_FOR_I[0].u_pulse_dly/rCnt_0_s3/CLK
39.645 -0.030 tUnc u_p2b/u_p2b/GEN_FOR_I[0].u_pulse_dly/rCnt_0_s3
39.349 -0.296 tSu 1 u_p2b/u_p2b/GEN_FOR_I[0].u_pulse_dly/rCnt_0_s3
Path Statistics:
Clock Skew: -0.016
Setup Relationship: 2.353
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 0.609, 25.685%; route: 1.423, 59.994%; tC2Q: 0.340, 14.321%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%