rtl_dir		:=	../../project/src
tb_dir		:=	../../tb
tb_file		:=	$(tb_dir)/tb.v
prim_file	:=	$(tb_dir)/prim_sim.v

vcs:
	vcs -debug_acc+all  -debug_region+cell+encrypt -R -full64 -fsdb -sverilog \
	-v $(prim_file) \
	$(tb_file) \
	$(rtl_dir)/top.v \
	$(rtl_dir)/motivation_response.v \
	$(rtl_dir)/easycdr/easycdr.vo \
	$(rtl_dir)/pll_hclk/pll_hclk.v \
	$(rtl_dir)/pll_hclk_tx/pll_hclk_tx.v \
	 -cm line+cond+fsm+branch+tgl


vd:
	verdi -nologo -sverilog			\
	-v $(prim_file) \
	$(tb_file) \
	$(rtl_dir)/top.v \
	$(rtl_dir)/motivation_response.v \
	$(rtl_dir)/easycdr/easycdr.vo \
	$(rtl_dir)/pll_hclk/pll_hclk.v \
	$(rtl_dir)/pll_hclk_tx/pll_hclk_tx.v \
	-ssf tb.fsdb \
	&
