Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\IP_Release\EasyCDR\1.2\ref_design\Gowin_EasyCDR_RefDesign\project\src\easycdr\easycdr.v E:\IP_Release\EasyCDR\1.2\ref_design\Gowin_EasyCDR_RefDesign\project\src\motivation_response.v E:\IP_Release\EasyCDR\1.2\ref_design\Gowin_EasyCDR_RefDesign\project\src\pll_hclk\pll_hclk.v E:\IP_Release\EasyCDR\1.2\ref_design\Gowin_EasyCDR_RefDesign\project\src\pll_hclk_tx\pll_hclk_tx.v E:\IP_Release\EasyCDR\1.2\ref_design\Gowin_EasyCDR_RefDesign\project\src\top.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v D:\Gowin\Gowin_V1.9.9.03_x64\IDE\data\ipcores\gw_jtag.v E:\IP_Release\EasyCDR\1.2\ref_design\Gowin_EasyCDR_RefDesign\project\impl\gwsynthesis\RTL_GAO\gw_gao_top.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.9.03 (64-bit) |
| Part Number | GW5A-LV25UG324ES |
| Device | GW5A-25 |
| Device Version | A |
| Created Time | Wed Apr 24 16:21:02 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.5s, Elapsed time = 0h 0m 0.547s, Peak memory usage = 228.289MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.046s, Peak memory usage = 228.289MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.026s, Peak memory usage = 228.289MB Optimizing Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.056s, Peak memory usage = 228.289MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 228.289MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 228.289MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 228.289MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 228.289MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.04s, Peak memory usage = 228.289MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 228.289MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 228.289MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 253.227MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.058s, Peak memory usage = 253.227MB Generate output files: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.075s, Peak memory usage = 253.227MB |
| Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 253.227MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 14 |
| I/O Buf | 12 |
| IBUF | 6 |
| OBUF | 4 |
| TLVDS_IBUF | 1 |
| ELVDS_OBUF | 1 |
| Register | 713 |
| DFFRE | 11 |
| DFFPE | 58 |
| DFFCE | 644 |
| LUT | 974 |
| LUT2 | 90 |
| LUT3 | 280 |
| LUT4 | 604 |
| MUX | 1 |
| MUX16 | 1 |
| ALU | 13 |
| ALU | 13 |
| INV | 13 |
| INV | 13 |
| IOLOGIC | 2 |
| OSER10 | 1 |
| OSIDES32 | 1 |
| BSRAM | 2 |
| SDPB | 1 |
| SDPX9B | 1 |
| CLOCK | 8 |
| CLKDIV | 2 |
| DHCE | 4 |
| PLLA | 2 |
| Black Box | 1 |
| GW_JTAG | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 1008(995 LUT, 13 ALU) / 23040 | 5% |
| Register | 713 / 23685 | 4% |
| --Register as Latch | 0 / 23685 | 0% |
| --Register as FF | 713 / 23685 | 4% |
| BSRAM | 2 / 56 | 4% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| board_clk | Base | 20.000 | 50.0 | 0.000 | 10.000 | board_clk_ibuf/I | ||
| u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT0.default_gen_clk | Generated | 2.000 | 500.0 | 0.000 | 1.000 | board_clk_ibuf/I | board_clk | u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT0 |
| u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT1.default_gen_clk | Generated | 2.000 | 500.0 | 0.000 | 1.000 | board_clk_ibuf/I | board_clk | u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT1 |
| u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT2.default_gen_clk | Generated | 2.000 | 500.0 | 0.000 | 1.000 | board_clk_ibuf/I | board_clk | u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT2 |
| u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT3.default_gen_clk | Generated | 2.000 | 500.0 | 0.000 | 1.000 | board_clk_ibuf/I | board_clk | u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT3 |
| u_motivation_response/u_pll_hclk_tx/PLLA_inst/CLKOUT0.default_gen_clk | Generated | 2.000 | 500.0 | 0.000 | 1.000 | board_clk_ibuf/I | board_clk | u_motivation_response/u_pll_hclk_tx/PLLA_inst/CLKOUT0 |
| u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT.default_gen_clk | Generated | 10.000 | 100.0 | 0.000 | 5.000 | u_motivation_response/u_pll_hclk_tx/PLLA_inst/CLKOUT0 | u_motivation_response/u_pll_hclk_tx/PLLA_inst/CLKOUT0.default_gen_clk | u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT |
| u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT.default_gen_clk | Generated | 8.000 | 125.0 | 0.000 | 4.000 | u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT0 | u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT0.default_gen_clk | u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | board_clk | 50.000(MHz) | 208.768(MHz) | 6 | TOP |
| 2 | u_motivation_response/u_tx_module_top/clkdiv_inst_tx/CLKOUT.default_gen_clk | 100.000(MHz) | 190.749(MHz) | 6 | TOP |
| 3 | u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT.default_gen_clk | 125.000(MHz) | 189.125(MHz) | 6 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 0.282 |
| Data Arrival Time | 1.132 |
| Data Required Time | 1.414 |
| From | u_EasyCDR_Top/u_easycdr/u_share_logic/cen_s0 |
| To | u_EasyCDR_Top/u_easycdr/u_share_logic/dhcen_625m_270 |
| Launch Clk | board_clk[F] |
| Latch Clk | u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT3.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | board_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | board_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 28 | board_clk_ibuf/O |
| 0.375 | 0.375 | tNET | RR | 1 | u_EasyCDR_Top/u_easycdr/u_share_logic/cen_s0/CLK |
| 0.757 | 0.382 | tC2Q | RR | 4 | u_EasyCDR_Top/u_easycdr/u_share_logic/cen_s0/Q |
| 1.132 | 0.375 | tNET | RR | 1 | u_EasyCDR_Top/u_easycdr/u_share_logic/dhcen_625m_270/CEN |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 1.000 | 0.000 | u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT3.default_gen_clk | |||
| 1.281 | 0.281 | tCL | FF | 1 | u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT3 |
| 1.632 | 0.350 | tNET | FF | 3 | u_EasyCDR_Top/u_easycdr/u_share_logic/dhcen_625m_270/CLKIN |
| 1.597 | -0.035 | tUnc | u_EasyCDR_Top/u_easycdr/u_share_logic/dhcen_625m_270 | ||
| 1.414 | -0.182 | tSu | 1 | u_EasyCDR_Top/u_easycdr/u_share_logic/dhcen_625m_270 |
| Clock Skew: | 0.257 |
| Setup Relationship: | 1.000 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.375, 49.505%; tC2Q: 0.382, 50.495% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 2
Path Summary:| Slack | 0.282 |
| Data Arrival Time | 1.132 |
| Data Required Time | 1.414 |
| From | u_EasyCDR_Top/u_easycdr/u_share_logic/cen_s0 |
| To | u_EasyCDR_Top/u_easycdr/u_share_logic/dhcen_625m_180 |
| Launch Clk | board_clk[F] |
| Latch Clk | u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT2.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | board_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | board_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 28 | board_clk_ibuf/O |
| 0.375 | 0.375 | tNET | RR | 1 | u_EasyCDR_Top/u_easycdr/u_share_logic/cen_s0/CLK |
| 0.757 | 0.382 | tC2Q | RR | 4 | u_EasyCDR_Top/u_easycdr/u_share_logic/cen_s0/Q |
| 1.132 | 0.375 | tNET | RR | 1 | u_EasyCDR_Top/u_easycdr/u_share_logic/dhcen_625m_180/CEN |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 1.000 | 0.000 | u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT2.default_gen_clk | |||
| 1.281 | 0.281 | tCL | FF | 1 | u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT2 |
| 1.632 | 0.350 | tNET | FF | 3 | u_EasyCDR_Top/u_easycdr/u_share_logic/dhcen_625m_180/CLKIN |
| 1.597 | -0.035 | tUnc | u_EasyCDR_Top/u_easycdr/u_share_logic/dhcen_625m_180 | ||
| 1.414 | -0.182 | tSu | 1 | u_EasyCDR_Top/u_easycdr/u_share_logic/dhcen_625m_180 |
| Clock Skew: | 0.257 |
| Setup Relationship: | 1.000 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.375, 49.505%; tC2Q: 0.382, 50.495% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 3
Path Summary:| Slack | 0.282 |
| Data Arrival Time | 1.132 |
| Data Required Time | 1.414 |
| From | u_EasyCDR_Top/u_easycdr/u_share_logic/cen_s0 |
| To | u_EasyCDR_Top/u_easycdr/u_share_logic/dhcen_625m_90 |
| Launch Clk | board_clk[F] |
| Latch Clk | u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT1.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | board_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | board_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 28 | board_clk_ibuf/O |
| 0.375 | 0.375 | tNET | RR | 1 | u_EasyCDR_Top/u_easycdr/u_share_logic/cen_s0/CLK |
| 0.757 | 0.382 | tC2Q | RR | 4 | u_EasyCDR_Top/u_easycdr/u_share_logic/cen_s0/Q |
| 1.132 | 0.375 | tNET | RR | 1 | u_EasyCDR_Top/u_easycdr/u_share_logic/dhcen_625m_90/CEN |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 1.000 | 0.000 | u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT1.default_gen_clk | |||
| 1.281 | 0.281 | tCL | FF | 1 | u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT1 |
| 1.632 | 0.350 | tNET | FF | 3 | u_EasyCDR_Top/u_easycdr/u_share_logic/dhcen_625m_90/CLKIN |
| 1.597 | -0.035 | tUnc | u_EasyCDR_Top/u_easycdr/u_share_logic/dhcen_625m_90 | ||
| 1.414 | -0.182 | tSu | 1 | u_EasyCDR_Top/u_easycdr/u_share_logic/dhcen_625m_90 |
| Clock Skew: | 0.257 |
| Setup Relationship: | 1.000 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.375, 49.505%; tC2Q: 0.382, 50.495% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 4
Path Summary:| Slack | 0.282 |
| Data Arrival Time | 1.132 |
| Data Required Time | 1.414 |
| From | u_EasyCDR_Top/u_easycdr/u_share_logic/cen_s0 |
| To | u_EasyCDR_Top/u_easycdr/u_share_logic/dhcen_625m_0 |
| Launch Clk | board_clk[F] |
| Latch Clk | u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | board_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | board_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 28 | board_clk_ibuf/O |
| 0.375 | 0.375 | tNET | RR | 1 | u_EasyCDR_Top/u_easycdr/u_share_logic/cen_s0/CLK |
| 0.757 | 0.382 | tC2Q | RR | 4 | u_EasyCDR_Top/u_easycdr/u_share_logic/cen_s0/Q |
| 1.132 | 0.375 | tNET | RR | 1 | u_EasyCDR_Top/u_easycdr/u_share_logic/dhcen_625m_0/CEN |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 1.000 | 0.000 | u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT0.default_gen_clk | |||
| 1.281 | 0.281 | tCL | FF | 1 | u_motivation_response/u_pll_hclk/PLLA_inst/CLKOUT0 |
| 1.632 | 0.350 | tNET | FF | 3 | u_EasyCDR_Top/u_easycdr/u_share_logic/dhcen_625m_0/CLKIN |
| 1.597 | -0.035 | tUnc | u_EasyCDR_Top/u_easycdr/u_share_logic/dhcen_625m_0 | ||
| 1.414 | -0.182 | tSu | 1 | u_EasyCDR_Top/u_easycdr/u_share_logic/dhcen_625m_0 |
| Clock Skew: | 0.257 |
| Setup Relationship: | 1.000 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.375, 49.505%; tC2Q: 0.382, 50.495% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
Path 5
Path Summary:| Slack | 2.296 |
| Data Arrival Time | 22.034 |
| Data Required Time | 24.330 |
| From | u_EasyCDR_Top/u_easycdr/u_share_logic/reset_o_s0 |
| To | u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_cdr/o_dout_0_s1 |
| Launch Clk | board_clk[R] |
| Latch Clk | u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | board_clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | board_clk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 28 | board_clk_ibuf/O |
| 20.375 | 0.375 | tNET | RR | 1 | u_EasyCDR_Top/u_easycdr/u_share_logic/reset_o_s0/CLK |
| 20.757 | 0.382 | tC2Q | RR | 2 | u_EasyCDR_Top/u_easycdr/u_share_logic/reset_o_s0/Q |
| 21.132 | 0.375 | tNET | RR | 1 | u_EasyCDR_Top/u_easycdr/rstn_pclk_s1/I0 |
| 21.659 | 0.526 | tINS | RR | 273 | u_EasyCDR_Top/u_easycdr/rstn_pclk_s1/F |
| 22.034 | 0.375 | tNET | RR | 1 | u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_cdr/o_dout_0_s1/RESET |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 24.000 | 0.000 | u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT.default_gen_clk | |||
| 24.362 | 0.362 | tCL | RR | 422 | u_EasyCDR_Top/u_easycdr/u_share_logic/clkdiv_inst/CLKOUT |
| 24.737 | 0.375 | tNET | RR | 1 | u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_cdr/o_dout_0_s1/CLK |
| 24.702 | -0.035 | tUnc | u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_cdr/o_dout_0_s1 | ||
| 24.330 | -0.373 | tSu | 1 | u_EasyCDR_Top/u_easycdr/u_easycdr_32/u_cdr/o_dout_0_s1 |
| Clock Skew: | 0.362 |
| Setup Relationship: | 4.000 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |
| Arrival Data Path Delay: | cell: 0.526, 31.726%; route: 0.750, 45.214%; tC2Q: 0.382, 23.060% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.375, 100.000% |