﻿_______________________________________________________________________________
                  EasyCDR 参考设计阅读指南
----------------------------------------------------------------------
目标器件：GW5A-LV25UG324ES
----------------------------------------------------------------------
文件列表
----------------------------------------------------------------------
| -- docs
|     | -- EasyCDR_Readme.txt				-->	自述文件
| -- project
|     | -- fpga_project.gprj				-->	参考设计工程
|     | -- impl
|     | -- src
|         | -- top.v					-->	工程顶层模块
|         | -- motivation_response.v
|         | -- easycdr
|              | -- easycdr.vo				-->	仿真使用vo文件
|         | -- pll_hclk
|              | -- pll_hclk.v
|         | -- pll_hclk_tx
|              | -- pll_hclk_tx.v
|         | -- fpga_project.cst
|         | -- fpga_project.rao
|         | -- fpga_project.sdc
| -- simulation
|     | -- Modelsim
|         | -- cmd.do					-->	Modelsim仿真脚本
|     | -- VCS
|         | -- makefile					-->	VCS仿真脚本
| --tb
|     | -- tb.v					-->	仿真testbench
|     | -- prim_sim.v					-->	仿真模型
----------------------------------------------------------------------
使用说明：
	1、板测：使用Gowin软件打开上述文件中fpga_project.gprj，设置工程顶层模块并进行综合。根据所使用器件设置物理约束并布局布线后下载测试，最后使用示波器查看结果。
	2、modelsim仿真：仿真脚本存放于Modelsim文件夹中。
	3、vcs仿真：仿真脚本存放于VCS文件夹中。
_______________________________________________________________________________
                  Example EasyCDR Design Readme
----------------------------------------------------------------------
Object device:GW5A-LV25UG324ES
----------------------------------------------------------------------
File List:
----------------------------------------------------------------------
| -- docs
|     | -- EasyCDR_Readme.txt				-->	Read Me file (this file)
| -- project
|     | -- fpga_project.gprj				-->	Gowin Project File for Example Design
|     | -- impl
|     | -- src
|         | -- top.v					-->	Top file for Gowin Project 
|         | -- motivation_response.v
|         | -- easycdr
|              | -- easycdr.vo				-->	Verilog simulation File for tb
|         | -- pll_hclk
|              | -- pll_hclk.v
|         | -- pll_hclk_tx
|              | -- pll_hclk_tx.v
|         | -- fpga_project.cst
|         | -- fpga_project.rao
|         | -- fpga_project.sdc
| -- simulation
|     | -- Modelsim
|         | -- cmd.do					-->	Modelsim simulation script
|     | -- VCS
|         | -- makefile					-->	VCS simulation script
| -- tb
|     | -- tb.v					-->	TestBench for simulation
|     | -- prim_sim.v					-->	Simulation Model

----------------------------------------------------------------------
Instructions:
	1.Onboard test:Use Gowin software to open fpga_project.gprj in the above file, set up the top-level module of the project and synthesize it. Set the physical constraints, download the test, and finally use the oscilloscope to view the results.
	2.Modelsim simulation: Please use script in Modelsim folder.
	3.VCS simulation:Use script in VCS folder.
