Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.7.05Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v
C:\Gowin\Gowin_V1.9.7.05Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v
C:\Gowin\Gowin_V1.9.7.05Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v
C:\Gowin\Gowin_V1.9.7.05Beta\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v
C:\Gowin\Gowin_V1.9.7.05Beta\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v
C:\Gowin\Gowin_V1.9.7.05Beta\IDE\data\ipcores\gw_jtag.v
E:\myWork\IP\releaseVerify\V1.9.7.05\aeawb_gowinsyn\Release_test_gwsyn\fpga_project\impl\gao\gw_gao_top.v
GowinSynthesis Constraints File ---
GowinSynthesis Version GowinSynthesis V1.9.7.05Beta
Part Number GW2A-LV18PG256C8/I7
Device GW2A-18
Created Time Tue May 11 14:59:04 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module gw_gao
Synthesis Process Running parser:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 39.000MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 39.000MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 39.000MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 39.000MB
    Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.034s, Peak memory usage = 39.000MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 39.000MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 39.000MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 39.000MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 39.000MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 39.000MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 39.000MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 39.000MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 53.543MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.072s, Peak memory usage = 53.543MB
Generate output files:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.04s, Peak memory usage = 53.543MB
Total Time and Memory Usage CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 53.543MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 27
I/O Buf 27
    IBUF 26
    OBUF 1
Register 305
    DFF 44
    DFFP 1
    DFFPE 33
    DFFC 24
    DFFCE 197
    DFFNP 2
    DFFNC 4
LUT 357
    LUT2 56
    LUT3 107
    LUT4 194
MUX 1
    MUX16 1
ALU 9
    ALU 9
INV 2
    INV 2
BSRAM 2
    SDPX9B 2

Resource Utilization Summary

Resource Usage Utilization
Logic 376(367 LUTs, 9 ALUs) / 20736 2%
Register 305 / 16173 2%
  --Register as Latch 0 / 16173 0%
  --Register as FF 305 / 16173 2%
BSRAM 2 / 46 4%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
SYM_CLK_d Base 10.000 100.0 0.000 5.000 SYM_CLK_d_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 SYM_CLK_d 100.0(MHz) 234.7(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 5.740
Data Arrival Time 5.088
Data Required Time 10.828
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk SYM_CLK_d[R]
Latch Clk SYM_CLK_d[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 SYM_CLK_d
0.000 0.000 tCL RR 1 SYM_CLK_d_ibuf/I
0.683 0.683 tINS RR 95 SYM_CLK_d_ibuf/O
0.863 0.180 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
1.095 0.232 tC2Q RF 7 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/Q
1.332 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n259_s2/I1
1.887 0.555 tINS FF 3 u_la0_top/u_ao_mem_ctrl/n259_s2/F
2.124 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n257_s2/I2
2.577 0.453 tINS FF 3 u_la0_top/u_ao_mem_ctrl/n257_s2/F
2.814 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n255_s3/I2
3.267 0.453 tINS FF 2 u_la0_top/u_ao_mem_ctrl/n255_s3/F
3.504 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n254_s3/I1
4.059 0.555 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n254_s3/F
4.296 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n254_s1/I1
4.851 0.555 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n254_s1/F
5.088 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 SYM_CLK_d
10.000 0.000 tCL RR 1 SYM_CLK_d_ibuf/I
10.682 0.683 tINS RR 95 SYM_CLK_d_ibuf/O
10.863 0.180 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
10.828 -0.035 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.571, 60.852%; route: 1.422, 33.657%; tC2Q: 0.232, 5.491%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 6.467
Data Arrival Time 4.360
Data Required Time 10.828
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
To u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk SYM_CLK_d[R]
Latch Clk SYM_CLK_d[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 SYM_CLK_d
0.000 0.000 tCL RR 1 SYM_CLK_d_ibuf/I
0.683 0.683 tINS RR 95 SYM_CLK_d_ibuf/O
0.863 0.180 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
1.095 0.232 tC2Q RF 6 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q
1.332 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n254_s9/I0
1.849 0.517 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n254_s9/F
2.086 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n254_s6/I1
2.641 0.555 tINS FF 2 u_la0_top/u_ao_mem_ctrl/n254_s6/F
2.878 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n254_s4/I0
3.395 0.517 tINS FF 10 u_la0_top/u_ao_mem_ctrl/n254_s4/F
3.632 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0
4.181 0.549 tINS FR 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F
4.360 0.180 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 SYM_CLK_d
10.000 0.000 tCL RR 1 SYM_CLK_d_ibuf/I
10.682 0.683 tINS RR 95 SYM_CLK_d_ibuf/O
10.863 0.180 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
10.828 -0.035 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.138, 61.121%; route: 1.128, 32.247%; tC2Q: 0.232, 6.632%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack 6.506
Data Arrival Time 4.321
Data Required Time 10.828
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk SYM_CLK_d[R]
Latch Clk SYM_CLK_d[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 SYM_CLK_d
0.000 0.000 tCL RR 1 SYM_CLK_d_ibuf/I
0.683 0.683 tINS RR 95 SYM_CLK_d_ibuf/O
0.863 0.180 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
1.095 0.232 tC2Q RF 6 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q
1.332 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n254_s9/I0
1.849 0.517 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n254_s9/F
2.086 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n254_s6/I1
2.641 0.555 tINS FF 2 u_la0_top/u_ao_mem_ctrl/n254_s6/F
2.878 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n254_s4/I0
3.395 0.517 tINS FF 10 u_la0_top/u_ao_mem_ctrl/n254_s4/F
3.632 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n262_s1/I2
4.084 0.453 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n262_s1/F
4.321 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 SYM_CLK_d
10.000 0.000 tCL RR 1 SYM_CLK_d_ibuf/I
10.682 0.683 tINS RR 95 SYM_CLK_d_ibuf/O
10.863 0.180 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
10.828 -0.035 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.042, 59.035%; route: 1.185, 34.258%; tC2Q: 0.232, 6.707%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 6.506
Data Arrival Time 4.321
Data Required Time 10.828
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk SYM_CLK_d[R]
Latch Clk SYM_CLK_d[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 SYM_CLK_d
0.000 0.000 tCL RR 1 SYM_CLK_d_ibuf/I
0.683 0.683 tINS RR 95 SYM_CLK_d_ibuf/O
0.863 0.180 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
1.095 0.232 tC2Q RF 6 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q
1.332 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n254_s9/I0
1.849 0.517 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n254_s9/F
2.086 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n254_s6/I1
2.641 0.555 tINS FF 2 u_la0_top/u_ao_mem_ctrl/n254_s6/F
2.878 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n254_s4/I0
3.395 0.517 tINS FF 10 u_la0_top/u_ao_mem_ctrl/n254_s4/F
3.632 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n260_s1/I2
4.084 0.453 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n260_s1/F
4.321 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 SYM_CLK_d
10.000 0.000 tCL RR 1 SYM_CLK_d_ibuf/I
10.682 0.683 tINS RR 95 SYM_CLK_d_ibuf/O
10.863 0.180 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
10.828 -0.035 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.042, 59.035%; route: 1.185, 34.258%; tC2Q: 0.232, 6.707%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack 6.506
Data Arrival Time 4.321
Data Required Time 10.828
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk SYM_CLK_d[R]
Latch Clk SYM_CLK_d[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 SYM_CLK_d
0.000 0.000 tCL RR 1 SYM_CLK_d_ibuf/I
0.683 0.683 tINS RR 95 SYM_CLK_d_ibuf/O
0.863 0.180 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
1.095 0.232 tC2Q RF 6 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q
1.332 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n254_s9/I0
1.849 0.517 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n254_s9/F
2.086 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n254_s6/I1
2.641 0.555 tINS FF 2 u_la0_top/u_ao_mem_ctrl/n254_s6/F
2.878 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n254_s4/I0
3.395 0.517 tINS FF 10 u_la0_top/u_ao_mem_ctrl/n254_s4/F
3.632 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n259_s1/I2
4.084 0.453 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n259_s1/F
4.321 0.237 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 SYM_CLK_d
10.000 0.000 tCL RR 1 SYM_CLK_d_ibuf/I
10.682 0.683 tINS RR 95 SYM_CLK_d_ibuf/O
10.863 0.180 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
10.828 -0.035 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.042, 59.035%; route: 1.185, 34.258%; tC2Q: 0.232, 6.707%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%