Timing Messages
| Report Title | Timing Analysis Report |
| Design File | E:\work_files\IP_A_new\GoConfig\00_2025\I2C_jtag\ref_design\fpga_project\impl\gwsynthesis\fpga_project.vg |
| Physical Constraints File | E:\work_files\IP_A_new\GoConfig\00_2025\I2C_jtag\ref_design\fpga_project\src\fpga_project.cst |
| Timing Constraint File | --- |
| Tool Version | V1.9.12 (64-bit) |
| Part Number | GW1N-LV2LQ144XC7/I6 |
| Device | GW1N-2 |
| Device Version | C |
| Created Time | Fri Aug 8 16:30:08 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
| Setup Delay Model | Slow 1.14V 85C C7/I6 |
| Hold Delay Model | Fast 1.26V 0C C7/I6 |
| Numbers of Paths Analyzed | 1530 |
| Numbers of Endpoints Analyzed | 734 |
| Numbers of Falling Endpoints | 0 |
| Numbers of Setup Violated Endpoints | 0 |
| Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
|---|---|---|---|---|---|---|---|---|---|
| 1 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | Base | 40.000 | 25.000 | 0.000 | 20.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | 25.000(MHz) | 105.830(MHz) | 7 | TOP |
Total Negative Slack Summary:
| Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
|---|---|---|---|
| u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | Setup | 0.000 | 0 |
| u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 30.551 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/sda_out_s2/D | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 9.153 |
| 2 | 30.762 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1/D | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 8.942 |
| 3 | 30.804 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_10_s1/D | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 8.899 |
| 4 | 30.846 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_9_s1/D | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 8.857 |
| 5 | 30.889 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_8_s1/D | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 8.815 |
| 6 | 30.931 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_7_s1/D | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 8.773 |
| 7 | 30.973 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_6_s1/D | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 8.730 |
| 8 | 30.984 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/rden_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/mem_mem_0_0_s/CEB | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 8.878 |
| 9 | 31.015 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_5_s1/D | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 8.688 |
| 10 | 31.058 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_4_s1/D | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 8.646 |
| 11 | 31.100 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_3_s1/D | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 8.604 |
| 12 | 31.142 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/D | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 8.562 |
| 13 | 31.184 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_1_s1/D | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 8.519 |
| 14 | 31.227 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_0_s1/D | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 8.477 |
| 15 | 31.821 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_5_s0/CE | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 8.146 |
| 16 | 31.847 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/counter_10_s2/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_11_s0/CE | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 8.121 |
| 17 | 31.889 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/rden_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0/D | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 7.815 |
| 18 | 31.902 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_0_s0/CE | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 8.066 |
| 19 | 31.983 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_14_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_model_state_1_s2/D | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 7.721 |
| 20 | 32.058 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_3_s0/CE | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 7.910 |
| 21 | 32.090 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_6_s0/CE | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 7.877 |
| 22 | 32.090 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_7_s0/CE | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 7.877 |
| 23 | 32.094 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_0_s0/D | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 7.610 |
| 24 | 32.119 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/counter_10_s2/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_14_s0/CE | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 7.848 |
| 25 | 32.123 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/counter_10_s2/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_8_s0/CE | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 7.845 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 0.439 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/in_reg_enable_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/in_reg_0_s0/CE | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 0.448 |
| 2 | 0.524 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_13_s1/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_13_s1/D | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 0.524 |
| 3 | 0.524 | led_s1/Q | led_s1/D | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 0.524 |
| 4 | 0.524 | led_cnt_31_s0/Q | led_cnt_31_s0/D | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 0.524 |
| 5 | 0.524 | led_cnt_1_s0/Q | led_cnt_1_s0/D | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 0.524 |
| 6 | 0.524 | led_cnt_2_s0/Q | led_cnt_2_s0/D | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 0.524 |
| 7 | 0.524 | led_cnt_5_s0/Q | led_cnt_5_s0/D | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 0.524 |
| 8 | 0.524 | led_cnt_7_s0/Q | led_cnt_7_s0/D | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 0.524 |
| 9 | 0.524 | led_cnt_13_s0/Q | led_cnt_13_s0/D | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 0.524 |
| 10 | 0.524 | led_cnt_14_s0/Q | led_cnt_14_s0/D | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 0.524 |
| 11 | 0.524 | led_cnt_16_s0/Q | led_cnt_16_s0/D | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 0.524 |
| 12 | 0.524 | led_cnt_21_s0/Q | led_cnt_21_s0/D | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 0.524 |
| 13 | 0.524 | led_cnt_25_s0/Q | led_cnt_25_s0/D | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 0.524 |
| 14 | 0.525 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/RXRDY_s5/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/RXRDY_s5/D | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 0.525 |
| 15 | 0.525 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/length_flag_s2/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/length_flag_s2/D | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 0.525 |
| 16 | 0.525 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_add_0_s1/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_add_0_s1/D | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 0.525 |
| 17 | 0.525 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_bit_cnt_2_s1/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_bit_cnt_2_s1/D | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 0.525 |
| 18 | 0.525 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_10_s1/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_10_s1/D | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 0.525 |
| 19 | 0.525 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_14_s1/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_14_s1/D | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 0.525 |
| 20 | 0.525 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_1_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_1_s0/D | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 0.525 |
| 21 | 0.525 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_2_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_2_s0/D | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 0.525 |
| 22 | 0.525 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/counter_1_s3/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/counter_1_s3/D | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 0.525 |
| 23 | 0.525 | led_cnt_10_s0/Q | led_cnt_10_s0/D | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 0.525 |
| 24 | 0.525 | led_cnt_27_s0/Q | led_cnt_27_s0/D | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 0.525 |
| 25 | 0.526 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_bit_cnt_0_s1/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_bit_cnt_0_s1/D | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 0.526 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 37.795 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/mem_mem_0_0_s/RESETB | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 2.054 |
| 2 | 37.914 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_0_s1/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 2.054 |
| 3 | 37.914 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_1_s1/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 2.054 |
| 4 | 37.914 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 2.054 |
| 5 | 37.914 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_3_s1/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 2.054 |
| 6 | 37.914 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_4_s1/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 2.054 |
| 7 | 37.914 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_5_s1/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 2.054 |
| 8 | 37.914 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_6_s1/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 2.054 |
| 9 | 37.914 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_7_s1/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 2.054 |
| 10 | 37.914 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_8_s1/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 2.054 |
| 11 | 37.914 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_9_s1/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 2.054 |
| 12 | 37.914 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_10_s1/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 2.054 |
| 13 | 37.914 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 2.054 |
| 14 | 37.914 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0/PRESET | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 2.054 |
| 15 | 37.914 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_0_s0/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 2.054 |
| 16 | 37.914 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_1_s0/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 2.054 |
| 17 | 37.914 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_2_s0/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 2.054 |
| 18 | 37.914 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_3_s0/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 2.054 |
| 19 | 37.914 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_4_s0/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 2.054 |
| 20 | 37.914 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_5_s0/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 2.054 |
| 21 | 37.914 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_6_s0/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 2.054 |
| 22 | 37.914 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_7_s0/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 2.054 |
| 23 | 37.914 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_8_s0/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 2.054 |
| 24 | 37.914 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_9_s0/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 2.054 |
| 25 | 37.914 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_10_s0/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 40.000 | 0.000 | 2.054 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 1.330 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/mem_mem_0_0_s/RESETB | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 1.339 |
| 2 | 1.330 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_0_s1/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 1.339 |
| 3 | 1.330 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_1_s1/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 1.339 |
| 4 | 1.330 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 1.339 |
| 5 | 1.330 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_3_s1/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 1.339 |
| 6 | 1.330 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_4_s1/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 1.339 |
| 7 | 1.330 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_5_s1/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 1.339 |
| 8 | 1.330 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_6_s1/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 1.339 |
| 9 | 1.330 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_7_s1/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 1.339 |
| 10 | 1.330 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_8_s1/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 1.339 |
| 11 | 1.330 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_9_s1/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 1.339 |
| 12 | 1.330 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_10_s1/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 1.339 |
| 13 | 1.330 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 1.339 |
| 14 | 1.330 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0/PRESET | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 1.339 |
| 15 | 1.330 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_0_s0/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 1.339 |
| 16 | 1.330 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_1_s0/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 1.339 |
| 17 | 1.330 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_2_s0/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 1.339 |
| 18 | 1.330 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_3_s0/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 1.339 |
| 19 | 1.330 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_4_s0/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 1.339 |
| 20 | 1.330 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_5_s0/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 1.339 |
| 21 | 1.330 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_6_s0/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 1.339 |
| 22 | 1.330 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_7_s0/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 1.339 |
| 23 | 1.330 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_8_s0/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 1.339 |
| 24 | 1.330 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_9_s0/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 1.339 |
| 25 | 1.330 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_10_s0/CLEAR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] | 0.000 | 0.000 | 1.339 |
Minimum Pulse Width Table:
| Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
|---|---|---|---|---|---|---|
| 1 | 19.017 | 19.943 | 0.926 | Low Pulse Width | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | led_cnt_30_s0 |
| 2 | 19.017 | 19.943 | 0.926 | Low Pulse Width | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | led_cnt_28_s0 |
| 3 | 19.017 | 19.943 | 0.926 | Low Pulse Width | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | led_cnt_24_s0 |
| 4 | 19.017 | 19.943 | 0.926 | Low Pulse Width | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | led_cnt_16_s0 |
| 5 | 19.017 | 19.943 | 0.926 | Low Pulse Width | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | led_cnt_0_s0 |
| 6 | 19.017 | 19.943 | 0.926 | Low Pulse Width | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_3_s0 |
| 7 | 19.017 | 19.943 | 0.926 | Low Pulse Width | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_7_s0 |
| 8 | 19.017 | 19.943 | 0.926 | Low Pulse Width | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_6_s0 |
| 9 | 19.017 | 19.943 | 0.926 | Low Pulse Width | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_7_s0 |
| 10 | 19.017 | 19.943 | 0.926 | Low Pulse Width | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_8_s0 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 30.551 |
| Data Arrival Time | 9.333 |
| Data Required Time | 39.884 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/sda_out_s2 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R11C4[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1/CLK |
| 0.520 | 0.340 | tC2Q | RR | 2 | R11C4[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1/Q |
| 0.831 | 0.311 | tNET | RR | 1 | R11C4[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s4/I3 |
| 1.596 | 0.765 | tINS | RF | 2 | R11C4[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s4/F |
| 2.195 | 0.599 | tNET | FF | 1 | R12C3[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Full_d_s/I0 |
| 2.960 | 0.765 | tINS | FF | 28 | R12C3[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Full_d_s/F |
| 5.736 | 2.776 | tNET | FF | 1 | R12C16[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/n853_s50/I2 |
| 6.501 | 0.765 | tINS | FF | 1 | R12C16[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/n853_s50/F |
| 6.505 | 0.004 | tNET | FF | 1 | R12C16[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/n853_s44/I2 |
| 7.270 | 0.765 | tINS | FF | 1 | R12C16[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/n853_s44/F |
| 7.274 | 0.004 | tNET | FF | 1 | R12C16[3][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/n853_s38/I3 |
| 7.883 | 0.609 | tINS | FF | 1 | R12C16[3][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/n853_s38/F |
| 8.724 | 0.841 | tNET | FF | 1 | R12C18[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/n853_s34/I3 |
| 9.333 | 0.609 | tINS | FF | 1 | R12C18[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/n853_s34/F |
| 9.333 | 0.000 | tNET | FF | 1 | R12C18[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/sda_out_s2/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R12C18[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/sda_out_s2/CLK |
| 39.884 | -0.296 | tSu | 1 | R12C18[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/sda_out_s2 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 7 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 4.277, 46.730%; route: 4.536, 49.559%; tC2Q: 0.340, 3.711% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path2
Path Summary:
| Slack | 30.762 |
| Data Arrival Time | 9.122 |
| Data Required Time | 39.884 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R15C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0/CLK |
| 0.520 | 0.340 | tC2Q | RF | 9 | R15C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0/Q |
| 1.727 | 1.207 | tNET | FF | 1 | R15C10[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_wren_s1/I0 |
| 2.336 | 0.609 | tINS | FF | 1 | R15C10[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_wren_s1/F |
| 3.646 | 1.310 | tNET | FF | 1 | R12C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s1/I3 |
| 4.255 | 0.609 | tINS | FF | 5 | R12C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s1/F |
| 5.225 | 0.970 | tNET | FF | 1 | R11C5[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n147_1_s1/I2 |
| 5.834 | 0.609 | tINS | FF | 1 | R11C5[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n147_1_s1/F |
| 8.240 | 2.406 | tNET | FF | 2 | R11C3[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n211_1_s/CIN |
| 8.283 | 0.042 | tINS | FF | 1 | R11C3[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n211_1_s/COUT |
| 8.283 | 0.000 | tNET | FF | 2 | R11C3[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n210_1_s/CIN |
| 8.325 | 0.042 | tINS | FF | 1 | R11C3[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n210_1_s/COUT |
| 8.325 | 0.000 | tNET | FF | 2 | R11C3[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n209_1_s/CIN |
| 8.367 | 0.042 | tINS | FF | 1 | R11C3[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n209_1_s/COUT |
| 8.367 | 0.000 | tNET | FF | 2 | R11C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n208_1_s/CIN |
| 8.409 | 0.042 | tINS | FF | 1 | R11C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n208_1_s/COUT |
| 8.409 | 0.000 | tNET | FF | 2 | R11C3[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n207_1_s/CIN |
| 8.452 | 0.042 | tINS | FF | 1 | R11C3[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n207_1_s/COUT |
| 8.452 | 0.000 | tNET | FF | 2 | R11C3[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n206_1_s/CIN |
| 8.494 | 0.042 | tINS | FF | 1 | R11C3[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n206_1_s/COUT |
| 8.494 | 0.000 | tNET | FF | 2 | R11C4[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n205_1_s/CIN |
| 8.536 | 0.042 | tINS | FF | 1 | R11C4[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n205_1_s/COUT |
| 8.536 | 0.000 | tNET | FF | 2 | R11C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n204_1_s/CIN |
| 8.578 | 0.042 | tINS | FF | 1 | R11C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n204_1_s/COUT |
| 8.578 | 0.000 | tNET | FF | 2 | R11C4[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n203_1_s/CIN |
| 8.620 | 0.042 | tINS | FF | 1 | R11C4[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n203_1_s/COUT |
| 8.620 | 0.000 | tNET | FF | 2 | R11C4[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n202_1_s/CIN |
| 8.663 | 0.042 | tINS | FF | 1 | R11C4[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n202_1_s/COUT |
| 8.663 | 0.000 | tNET | FF | 2 | R11C4[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n201_1_s/CIN |
| 8.705 | 0.042 | tINS | FF | 1 | R11C4[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n201_1_s/COUT |
| 8.705 | 0.000 | tNET | FF | 2 | R11C4[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n200_1_s/CIN |
| 9.122 | 0.417 | tINS | FF | 1 | R11C4[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n200_1_s/SUM |
| 9.122 | 0.000 | tNET | FF | 1 | R11C4[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R11C4[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1/CLK |
| 39.884 | -0.296 | tSu | 1 | R11C4[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 7 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 2.709, 30.298%; route: 5.893, 65.904%; tC2Q: 0.340, 3.798% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path3
Path Summary:
| Slack | 30.804 |
| Data Arrival Time | 9.080 |
| Data Required Time | 39.884 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_10_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R15C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0/CLK |
| 0.520 | 0.340 | tC2Q | RF | 9 | R15C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0/Q |
| 1.727 | 1.207 | tNET | FF | 1 | R15C10[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_wren_s1/I0 |
| 2.336 | 0.609 | tINS | FF | 1 | R15C10[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_wren_s1/F |
| 3.646 | 1.310 | tNET | FF | 1 | R12C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s1/I3 |
| 4.255 | 0.609 | tINS | FF | 5 | R12C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s1/F |
| 5.225 | 0.970 | tNET | FF | 1 | R11C5[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n147_1_s1/I2 |
| 5.834 | 0.609 | tINS | FF | 1 | R11C5[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n147_1_s1/F |
| 8.240 | 2.406 | tNET | FF | 2 | R11C3[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n211_1_s/CIN |
| 8.283 | 0.042 | tINS | FF | 1 | R11C3[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n211_1_s/COUT |
| 8.283 | 0.000 | tNET | FF | 2 | R11C3[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n210_1_s/CIN |
| 8.325 | 0.042 | tINS | FF | 1 | R11C3[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n210_1_s/COUT |
| 8.325 | 0.000 | tNET | FF | 2 | R11C3[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n209_1_s/CIN |
| 8.367 | 0.042 | tINS | FF | 1 | R11C3[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n209_1_s/COUT |
| 8.367 | 0.000 | tNET | FF | 2 | R11C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n208_1_s/CIN |
| 8.409 | 0.042 | tINS | FF | 1 | R11C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n208_1_s/COUT |
| 8.409 | 0.000 | tNET | FF | 2 | R11C3[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n207_1_s/CIN |
| 8.452 | 0.042 | tINS | FF | 1 | R11C3[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n207_1_s/COUT |
| 8.452 | 0.000 | tNET | FF | 2 | R11C3[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n206_1_s/CIN |
| 8.494 | 0.042 | tINS | FF | 1 | R11C3[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n206_1_s/COUT |
| 8.494 | 0.000 | tNET | FF | 2 | R11C4[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n205_1_s/CIN |
| 8.536 | 0.042 | tINS | FF | 1 | R11C4[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n205_1_s/COUT |
| 8.536 | 0.000 | tNET | FF | 2 | R11C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n204_1_s/CIN |
| 8.578 | 0.042 | tINS | FF | 1 | R11C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n204_1_s/COUT |
| 8.578 | 0.000 | tNET | FF | 2 | R11C4[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n203_1_s/CIN |
| 8.620 | 0.042 | tINS | FF | 1 | R11C4[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n203_1_s/COUT |
| 8.620 | 0.000 | tNET | FF | 2 | R11C4[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n202_1_s/CIN |
| 8.663 | 0.042 | tINS | FF | 1 | R11C4[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n202_1_s/COUT |
| 8.663 | 0.000 | tNET | FF | 2 | R11C4[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n201_1_s/CIN |
| 9.080 | 0.417 | tINS | FF | 1 | R11C4[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n201_1_s/SUM |
| 9.080 | 0.000 | tNET | FF | 1 | R11C4[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_10_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R11C4[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_10_s1/CLK |
| 39.884 | -0.296 | tSu | 1 | R11C4[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_10_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 7 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 2.667, 29.967%; route: 5.893, 66.217%; tC2Q: 0.340, 3.816% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path4
Path Summary:
| Slack | 30.846 |
| Data Arrival Time | 9.038 |
| Data Required Time | 39.884 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_9_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R15C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0/CLK |
| 0.520 | 0.340 | tC2Q | RF | 9 | R15C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0/Q |
| 1.727 | 1.207 | tNET | FF | 1 | R15C10[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_wren_s1/I0 |
| 2.336 | 0.609 | tINS | FF | 1 | R15C10[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_wren_s1/F |
| 3.646 | 1.310 | tNET | FF | 1 | R12C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s1/I3 |
| 4.255 | 0.609 | tINS | FF | 5 | R12C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s1/F |
| 5.225 | 0.970 | tNET | FF | 1 | R11C5[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n147_1_s1/I2 |
| 5.834 | 0.609 | tINS | FF | 1 | R11C5[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n147_1_s1/F |
| 8.240 | 2.406 | tNET | FF | 2 | R11C3[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n211_1_s/CIN |
| 8.283 | 0.042 | tINS | FF | 1 | R11C3[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n211_1_s/COUT |
| 8.283 | 0.000 | tNET | FF | 2 | R11C3[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n210_1_s/CIN |
| 8.325 | 0.042 | tINS | FF | 1 | R11C3[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n210_1_s/COUT |
| 8.325 | 0.000 | tNET | FF | 2 | R11C3[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n209_1_s/CIN |
| 8.367 | 0.042 | tINS | FF | 1 | R11C3[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n209_1_s/COUT |
| 8.367 | 0.000 | tNET | FF | 2 | R11C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n208_1_s/CIN |
| 8.409 | 0.042 | tINS | FF | 1 | R11C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n208_1_s/COUT |
| 8.409 | 0.000 | tNET | FF | 2 | R11C3[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n207_1_s/CIN |
| 8.452 | 0.042 | tINS | FF | 1 | R11C3[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n207_1_s/COUT |
| 8.452 | 0.000 | tNET | FF | 2 | R11C3[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n206_1_s/CIN |
| 8.494 | 0.042 | tINS | FF | 1 | R11C3[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n206_1_s/COUT |
| 8.494 | 0.000 | tNET | FF | 2 | R11C4[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n205_1_s/CIN |
| 8.536 | 0.042 | tINS | FF | 1 | R11C4[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n205_1_s/COUT |
| 8.536 | 0.000 | tNET | FF | 2 | R11C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n204_1_s/CIN |
| 8.578 | 0.042 | tINS | FF | 1 | R11C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n204_1_s/COUT |
| 8.578 | 0.000 | tNET | FF | 2 | R11C4[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n203_1_s/CIN |
| 8.620 | 0.042 | tINS | FF | 1 | R11C4[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n203_1_s/COUT |
| 8.620 | 0.000 | tNET | FF | 2 | R11C4[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n202_1_s/CIN |
| 9.038 | 0.417 | tINS | FF | 1 | R11C4[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n202_1_s/SUM |
| 9.038 | 0.000 | tNET | FF | 1 | R11C4[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_9_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R11C4[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_9_s1/CLK |
| 39.884 | -0.296 | tSu | 1 | R11C4[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_9_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 7 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 2.625, 29.633%; route: 5.893, 66.533%; tC2Q: 0.340, 3.834% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path5
Path Summary:
| Slack | 30.889 |
| Data Arrival Time | 8.995 |
| Data Required Time | 39.884 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_8_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R15C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0/CLK |
| 0.520 | 0.340 | tC2Q | RF | 9 | R15C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0/Q |
| 1.727 | 1.207 | tNET | FF | 1 | R15C10[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_wren_s1/I0 |
| 2.336 | 0.609 | tINS | FF | 1 | R15C10[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_wren_s1/F |
| 3.646 | 1.310 | tNET | FF | 1 | R12C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s1/I3 |
| 4.255 | 0.609 | tINS | FF | 5 | R12C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s1/F |
| 5.225 | 0.970 | tNET | FF | 1 | R11C5[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n147_1_s1/I2 |
| 5.834 | 0.609 | tINS | FF | 1 | R11C5[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n147_1_s1/F |
| 8.240 | 2.406 | tNET | FF | 2 | R11C3[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n211_1_s/CIN |
| 8.283 | 0.042 | tINS | FF | 1 | R11C3[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n211_1_s/COUT |
| 8.283 | 0.000 | tNET | FF | 2 | R11C3[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n210_1_s/CIN |
| 8.325 | 0.042 | tINS | FF | 1 | R11C3[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n210_1_s/COUT |
| 8.325 | 0.000 | tNET | FF | 2 | R11C3[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n209_1_s/CIN |
| 8.367 | 0.042 | tINS | FF | 1 | R11C3[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n209_1_s/COUT |
| 8.367 | 0.000 | tNET | FF | 2 | R11C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n208_1_s/CIN |
| 8.409 | 0.042 | tINS | FF | 1 | R11C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n208_1_s/COUT |
| 8.409 | 0.000 | tNET | FF | 2 | R11C3[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n207_1_s/CIN |
| 8.452 | 0.042 | tINS | FF | 1 | R11C3[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n207_1_s/COUT |
| 8.452 | 0.000 | tNET | FF | 2 | R11C3[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n206_1_s/CIN |
| 8.494 | 0.042 | tINS | FF | 1 | R11C3[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n206_1_s/COUT |
| 8.494 | 0.000 | tNET | FF | 2 | R11C4[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n205_1_s/CIN |
| 8.536 | 0.042 | tINS | FF | 1 | R11C4[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n205_1_s/COUT |
| 8.536 | 0.000 | tNET | FF | 2 | R11C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n204_1_s/CIN |
| 8.578 | 0.042 | tINS | FF | 1 | R11C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n204_1_s/COUT |
| 8.578 | 0.000 | tNET | FF | 2 | R11C4[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n203_1_s/CIN |
| 8.995 | 0.417 | tINS | FF | 1 | R11C4[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n203_1_s/SUM |
| 8.995 | 0.000 | tNET | FF | 1 | R11C4[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_8_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R11C4[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_8_s1/CLK |
| 39.884 | -0.296 | tSu | 1 | R11C4[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_8_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 7 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 2.582, 29.296%; route: 5.893, 66.852%; tC2Q: 0.340, 3.853% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path6
Path Summary:
| Slack | 30.931 |
| Data Arrival Time | 8.953 |
| Data Required Time | 39.884 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_7_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R15C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0/CLK |
| 0.520 | 0.340 | tC2Q | RF | 9 | R15C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0/Q |
| 1.727 | 1.207 | tNET | FF | 1 | R15C10[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_wren_s1/I0 |
| 2.336 | 0.609 | tINS | FF | 1 | R15C10[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_wren_s1/F |
| 3.646 | 1.310 | tNET | FF | 1 | R12C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s1/I3 |
| 4.255 | 0.609 | tINS | FF | 5 | R12C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s1/F |
| 5.225 | 0.970 | tNET | FF | 1 | R11C5[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n147_1_s1/I2 |
| 5.834 | 0.609 | tINS | FF | 1 | R11C5[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n147_1_s1/F |
| 8.240 | 2.406 | tNET | FF | 2 | R11C3[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n211_1_s/CIN |
| 8.283 | 0.042 | tINS | FF | 1 | R11C3[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n211_1_s/COUT |
| 8.283 | 0.000 | tNET | FF | 2 | R11C3[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n210_1_s/CIN |
| 8.325 | 0.042 | tINS | FF | 1 | R11C3[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n210_1_s/COUT |
| 8.325 | 0.000 | tNET | FF | 2 | R11C3[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n209_1_s/CIN |
| 8.367 | 0.042 | tINS | FF | 1 | R11C3[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n209_1_s/COUT |
| 8.367 | 0.000 | tNET | FF | 2 | R11C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n208_1_s/CIN |
| 8.409 | 0.042 | tINS | FF | 1 | R11C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n208_1_s/COUT |
| 8.409 | 0.000 | tNET | FF | 2 | R11C3[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n207_1_s/CIN |
| 8.452 | 0.042 | tINS | FF | 1 | R11C3[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n207_1_s/COUT |
| 8.452 | 0.000 | tNET | FF | 2 | R11C3[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n206_1_s/CIN |
| 8.494 | 0.042 | tINS | FF | 1 | R11C3[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n206_1_s/COUT |
| 8.494 | 0.000 | tNET | FF | 2 | R11C4[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n205_1_s/CIN |
| 8.536 | 0.042 | tINS | FF | 1 | R11C4[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n205_1_s/COUT |
| 8.536 | 0.000 | tNET | FF | 2 | R11C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n204_1_s/CIN |
| 8.953 | 0.417 | tINS | FF | 1 | R11C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n204_1_s/SUM |
| 8.953 | 0.000 | tNET | FF | 1 | R11C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_7_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R11C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_7_s1/CLK |
| 39.884 | -0.296 | tSu | 1 | R11C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_7_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 7 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 2.540, 28.955%; route: 5.893, 67.173%; tC2Q: 0.340, 3.871% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path7
Path Summary:
| Slack | 30.973 |
| Data Arrival Time | 8.911 |
| Data Required Time | 39.884 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_6_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R15C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0/CLK |
| 0.520 | 0.340 | tC2Q | RF | 9 | R15C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0/Q |
| 1.727 | 1.207 | tNET | FF | 1 | R15C10[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_wren_s1/I0 |
| 2.336 | 0.609 | tINS | FF | 1 | R15C10[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_wren_s1/F |
| 3.646 | 1.310 | tNET | FF | 1 | R12C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s1/I3 |
| 4.255 | 0.609 | tINS | FF | 5 | R12C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s1/F |
| 5.225 | 0.970 | tNET | FF | 1 | R11C5[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n147_1_s1/I2 |
| 5.834 | 0.609 | tINS | FF | 1 | R11C5[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n147_1_s1/F |
| 8.240 | 2.406 | tNET | FF | 2 | R11C3[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n211_1_s/CIN |
| 8.283 | 0.042 | tINS | FF | 1 | R11C3[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n211_1_s/COUT |
| 8.283 | 0.000 | tNET | FF | 2 | R11C3[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n210_1_s/CIN |
| 8.325 | 0.042 | tINS | FF | 1 | R11C3[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n210_1_s/COUT |
| 8.325 | 0.000 | tNET | FF | 2 | R11C3[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n209_1_s/CIN |
| 8.367 | 0.042 | tINS | FF | 1 | R11C3[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n209_1_s/COUT |
| 8.367 | 0.000 | tNET | FF | 2 | R11C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n208_1_s/CIN |
| 8.409 | 0.042 | tINS | FF | 1 | R11C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n208_1_s/COUT |
| 8.409 | 0.000 | tNET | FF | 2 | R11C3[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n207_1_s/CIN |
| 8.452 | 0.042 | tINS | FF | 1 | R11C3[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n207_1_s/COUT |
| 8.452 | 0.000 | tNET | FF | 2 | R11C3[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n206_1_s/CIN |
| 8.494 | 0.042 | tINS | FF | 1 | R11C3[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n206_1_s/COUT |
| 8.494 | 0.000 | tNET | FF | 2 | R11C4[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n205_1_s/CIN |
| 8.911 | 0.417 | tINS | FF | 1 | R11C4[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n205_1_s/SUM |
| 8.911 | 0.000 | tNET | FF | 1 | R11C4[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_6_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R11C4[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_6_s1/CLK |
| 39.884 | -0.296 | tSu | 1 | R11C4[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_6_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 2.498, 28.611%; route: 5.893, 67.498%; tC2Q: 0.340, 3.890% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path8
Path Summary:
| Slack | 30.984 |
| Data Arrival Time | 9.058 |
| Data Required Time | 40.042 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/rden_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/mem_mem_0_0_s |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R12C17[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/rden_s0/CLK |
| 0.520 | 0.340 | tC2Q | RF | 1 | R12C17[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/rden_s0/Q |
| 1.596 | 1.076 | tNET | FF | 1 | R12C6[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_rden_s0/I1 |
| 2.361 | 0.765 | tINS | FF | 6 | R12C6[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_rden_s0/F |
| 3.091 | 0.730 | tNET | FF | 1 | R11C7[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n101_s0/I1 |
| 3.700 | 0.609 | tINS | FF | 1 | R11C7[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n101_s0/F |
| 3.949 | 0.249 | tNET | FF | 2 | R11C7[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_0_s/I1 |
| 4.357 | 0.408 | tINS | FR | 1 | R11C7[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_0_s/COUT |
| 4.357 | 0.000 | tNET | RR | 2 | R11C7[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_1_s/CIN |
| 4.399 | 0.042 | tINS | RF | 1 | R11C7[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_1_s/COUT |
| 4.399 | 0.000 | tNET | FF | 2 | R11C7[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_2_s/CIN |
| 4.441 | 0.042 | tINS | FF | 1 | R11C7[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_2_s/COUT |
| 4.441 | 0.000 | tNET | FF | 2 | R11C7[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_3_s/CIN |
| 4.484 | 0.042 | tINS | FF | 1 | R11C7[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_3_s/COUT |
| 4.484 | 0.000 | tNET | FF | 2 | R11C7[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_4_s/CIN |
| 4.526 | 0.042 | tINS | FF | 1 | R11C7[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_4_s/COUT |
| 4.526 | 0.000 | tNET | FF | 2 | R11C7[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_5_s/CIN |
| 4.568 | 0.042 | tINS | FF | 1 | R11C7[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_5_s/COUT |
| 4.568 | 0.000 | tNET | FF | 2 | R11C8[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_6_s/CIN |
| 4.610 | 0.042 | tINS | FF | 1 | R11C8[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_6_s/COUT |
| 4.610 | 0.000 | tNET | FF | 2 | R11C8[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_7_s/CIN |
| 5.028 | 0.417 | tINS | FF | 3 | R11C8[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_7_s/SUM |
| 5.877 | 0.850 | tNET | FF | 2 | R12C8[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n245_s0/I0 |
| 6.587 | 0.710 | tINS | FF | 1 | R12C8[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n245_s0/COUT |
| 6.587 | 0.000 | tNET | FF | 2 | R12C8[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n246_s0/CIN |
| 6.629 | 0.042 | tINS | FF | 1 | R12C8[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n246_s0/COUT |
| 6.629 | 0.000 | tNET | FF | 2 | R12C8[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n247_s0/CIN |
| 6.671 | 0.042 | tINS | FF | 1 | R12C8[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n247_s0/COUT |
| 6.671 | 0.000 | tNET | FF | 2 | R12C8[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n248_s0/CIN |
| 6.714 | 0.042 | tINS | FF | 1 | R12C8[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n248_s0/COUT |
| 6.714 | 0.000 | tNET | FF | 2 | R12C9[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n249_s0/CIN |
| 6.756 | 0.042 | tINS | FF | 2 | R12C9[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n249_s0/COUT |
| 7.181 | 0.425 | tNET | FF | 1 | R12C9[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n13_s0/I2 |
| 7.967 | 0.786 | tINS | FR | 1 | R12C9[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n13_s0/F |
| 9.058 | 1.091 | tNET | RR | 1 | BSRAM_R10[2] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/mem_mem_0_0_s/CEB |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | BSRAM_R10[2] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/mem_mem_0_0_s/CLKB |
| 40.042 | -0.139 | tSu | 1 | BSRAM_R10[2] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/mem_mem_0_0_s |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 9 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 4.117, 46.374%; route: 4.421, 49.801%; tC2Q: 0.340, 3.826% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path9
Path Summary:
| Slack | 31.015 |
| Data Arrival Time | 8.869 |
| Data Required Time | 39.884 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_5_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R15C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0/CLK |
| 0.520 | 0.340 | tC2Q | RF | 9 | R15C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0/Q |
| 1.727 | 1.207 | tNET | FF | 1 | R15C10[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_wren_s1/I0 |
| 2.336 | 0.609 | tINS | FF | 1 | R15C10[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_wren_s1/F |
| 3.646 | 1.310 | tNET | FF | 1 | R12C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s1/I3 |
| 4.255 | 0.609 | tINS | FF | 5 | R12C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s1/F |
| 5.225 | 0.970 | tNET | FF | 1 | R11C5[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n147_1_s1/I2 |
| 5.834 | 0.609 | tINS | FF | 1 | R11C5[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n147_1_s1/F |
| 8.240 | 2.406 | tNET | FF | 2 | R11C3[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n211_1_s/CIN |
| 8.283 | 0.042 | tINS | FF | 1 | R11C3[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n211_1_s/COUT |
| 8.283 | 0.000 | tNET | FF | 2 | R11C3[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n210_1_s/CIN |
| 8.325 | 0.042 | tINS | FF | 1 | R11C3[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n210_1_s/COUT |
| 8.325 | 0.000 | tNET | FF | 2 | R11C3[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n209_1_s/CIN |
| 8.367 | 0.042 | tINS | FF | 1 | R11C3[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n209_1_s/COUT |
| 8.367 | 0.000 | tNET | FF | 2 | R11C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n208_1_s/CIN |
| 8.409 | 0.042 | tINS | FF | 1 | R11C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n208_1_s/COUT |
| 8.409 | 0.000 | tNET | FF | 2 | R11C3[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n207_1_s/CIN |
| 8.452 | 0.042 | tINS | FF | 1 | R11C3[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n207_1_s/COUT |
| 8.452 | 0.000 | tNET | FF | 2 | R11C3[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n206_1_s/CIN |
| 8.869 | 0.417 | tINS | FF | 1 | R11C3[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n206_1_s/SUM |
| 8.869 | 0.000 | tNET | FF | 1 | R11C3[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_5_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R11C3[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_5_s1/CLK |
| 39.884 | -0.296 | tSu | 1 | R11C3[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_5_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 2.456, 28.264%; route: 5.893, 67.827%; tC2Q: 0.340, 3.909% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path10
Path Summary:
| Slack | 31.058 |
| Data Arrival Time | 8.826 |
| Data Required Time | 39.884 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_4_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R15C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0/CLK |
| 0.520 | 0.340 | tC2Q | RF | 9 | R15C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0/Q |
| 1.727 | 1.207 | tNET | FF | 1 | R15C10[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_wren_s1/I0 |
| 2.336 | 0.609 | tINS | FF | 1 | R15C10[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_wren_s1/F |
| 3.646 | 1.310 | tNET | FF | 1 | R12C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s1/I3 |
| 4.255 | 0.609 | tINS | FF | 5 | R12C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s1/F |
| 5.225 | 0.970 | tNET | FF | 1 | R11C5[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n147_1_s1/I2 |
| 5.834 | 0.609 | tINS | FF | 1 | R11C5[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n147_1_s1/F |
| 8.240 | 2.406 | tNET | FF | 2 | R11C3[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n211_1_s/CIN |
| 8.283 | 0.042 | tINS | FF | 1 | R11C3[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n211_1_s/COUT |
| 8.283 | 0.000 | tNET | FF | 2 | R11C3[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n210_1_s/CIN |
| 8.325 | 0.042 | tINS | FF | 1 | R11C3[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n210_1_s/COUT |
| 8.325 | 0.000 | tNET | FF | 2 | R11C3[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n209_1_s/CIN |
| 8.367 | 0.042 | tINS | FF | 1 | R11C3[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n209_1_s/COUT |
| 8.367 | 0.000 | tNET | FF | 2 | R11C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n208_1_s/CIN |
| 8.409 | 0.042 | tINS | FF | 1 | R11C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n208_1_s/COUT |
| 8.409 | 0.000 | tNET | FF | 2 | R11C3[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n207_1_s/CIN |
| 8.826 | 0.417 | tINS | FF | 1 | R11C3[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n207_1_s/SUM |
| 8.826 | 0.000 | tNET | FF | 1 | R11C3[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_4_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R11C3[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_4_s1/CLK |
| 39.884 | -0.296 | tSu | 1 | R11C3[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_4_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 2.413, 27.914%; route: 5.893, 68.158%; tC2Q: 0.340, 3.928% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path11
Path Summary:
| Slack | 31.100 |
| Data Arrival Time | 8.784 |
| Data Required Time | 39.884 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_3_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R15C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0/CLK |
| 0.520 | 0.340 | tC2Q | RF | 9 | R15C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0/Q |
| 1.727 | 1.207 | tNET | FF | 1 | R15C10[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_wren_s1/I0 |
| 2.336 | 0.609 | tINS | FF | 1 | R15C10[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_wren_s1/F |
| 3.646 | 1.310 | tNET | FF | 1 | R12C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s1/I3 |
| 4.255 | 0.609 | tINS | FF | 5 | R12C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s1/F |
| 5.225 | 0.970 | tNET | FF | 1 | R11C5[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n147_1_s1/I2 |
| 5.834 | 0.609 | tINS | FF | 1 | R11C5[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n147_1_s1/F |
| 8.240 | 2.406 | tNET | FF | 2 | R11C3[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n211_1_s/CIN |
| 8.283 | 0.042 | tINS | FF | 1 | R11C3[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n211_1_s/COUT |
| 8.283 | 0.000 | tNET | FF | 2 | R11C3[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n210_1_s/CIN |
| 8.325 | 0.042 | tINS | FF | 1 | R11C3[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n210_1_s/COUT |
| 8.325 | 0.000 | tNET | FF | 2 | R11C3[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n209_1_s/CIN |
| 8.367 | 0.042 | tINS | FF | 1 | R11C3[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n209_1_s/COUT |
| 8.367 | 0.000 | tNET | FF | 2 | R11C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n208_1_s/CIN |
| 8.784 | 0.417 | tINS | FF | 1 | R11C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n208_1_s/SUM |
| 8.784 | 0.000 | tNET | FF | 1 | R11C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_3_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R11C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_3_s1/CLK |
| 39.884 | -0.296 | tSu | 1 | R11C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_3_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 2.371, 27.560%; route: 5.893, 68.493%; tC2Q: 0.340, 3.947% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path12
Path Summary:
| Slack | 31.142 |
| Data Arrival Time | 8.742 |
| Data Required Time | 39.884 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R15C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0/CLK |
| 0.520 | 0.340 | tC2Q | RF | 9 | R15C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0/Q |
| 1.727 | 1.207 | tNET | FF | 1 | R15C10[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_wren_s1/I0 |
| 2.336 | 0.609 | tINS | FF | 1 | R15C10[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_wren_s1/F |
| 3.646 | 1.310 | tNET | FF | 1 | R12C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s1/I3 |
| 4.255 | 0.609 | tINS | FF | 5 | R12C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s1/F |
| 5.225 | 0.970 | tNET | FF | 1 | R11C5[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n147_1_s1/I2 |
| 5.834 | 0.609 | tINS | FF | 1 | R11C5[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n147_1_s1/F |
| 8.240 | 2.406 | tNET | FF | 2 | R11C3[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n211_1_s/CIN |
| 8.283 | 0.042 | tINS | FF | 1 | R11C3[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n211_1_s/COUT |
| 8.283 | 0.000 | tNET | FF | 2 | R11C3[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n210_1_s/CIN |
| 8.325 | 0.042 | tINS | FF | 1 | R11C3[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n210_1_s/COUT |
| 8.325 | 0.000 | tNET | FF | 2 | R11C3[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n209_1_s/CIN |
| 8.742 | 0.417 | tINS | FF | 1 | R11C3[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n209_1_s/SUM |
| 8.742 | 0.000 | tNET | FF | 1 | R11C3[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R11C3[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/CLK |
| 39.884 | -0.296 | tSu | 1 | R11C3[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 2.329, 27.203%; route: 5.893, 68.830%; tC2Q: 0.340, 3.967% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path13
Path Summary:
| Slack | 31.184 |
| Data Arrival Time | 8.700 |
| Data Required Time | 39.884 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_1_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R15C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0/CLK |
| 0.520 | 0.340 | tC2Q | RF | 9 | R15C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0/Q |
| 1.727 | 1.207 | tNET | FF | 1 | R15C10[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_wren_s1/I0 |
| 2.336 | 0.609 | tINS | FF | 1 | R15C10[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_wren_s1/F |
| 3.646 | 1.310 | tNET | FF | 1 | R12C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s1/I3 |
| 4.255 | 0.609 | tINS | FF | 5 | R12C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s1/F |
| 5.225 | 0.970 | tNET | FF | 1 | R11C5[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n147_1_s1/I2 |
| 5.834 | 0.609 | tINS | FF | 1 | R11C5[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n147_1_s1/F |
| 8.240 | 2.406 | tNET | FF | 2 | R11C3[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n211_1_s/CIN |
| 8.283 | 0.042 | tINS | FF | 1 | R11C3[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n211_1_s/COUT |
| 8.283 | 0.000 | tNET | FF | 2 | R11C3[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n210_1_s/CIN |
| 8.700 | 0.417 | tINS | FF | 1 | R11C3[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n210_1_s/SUM |
| 8.700 | 0.000 | tNET | FF | 1 | R11C3[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_1_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R11C3[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_1_s1/CLK |
| 39.884 | -0.296 | tSu | 1 | R11C3[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_1_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 2.287, 26.842%; route: 5.893, 69.172%; tC2Q: 0.340, 3.987% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path14
Path Summary:
| Slack | 31.227 |
| Data Arrival Time | 8.658 |
| Data Required Time | 39.884 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_0_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R15C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0/CLK |
| 0.520 | 0.340 | tC2Q | RF | 9 | R15C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/in_sel_s0/Q |
| 1.727 | 1.207 | tNET | FF | 1 | R15C10[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_wren_s1/I0 |
| 2.336 | 0.609 | tINS | FF | 1 | R15C10[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_wren_s1/F |
| 3.646 | 1.310 | tNET | FF | 1 | R12C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s1/I3 |
| 4.255 | 0.609 | tINS | FF | 5 | R12C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s1/F |
| 5.225 | 0.970 | tNET | FF | 1 | R11C5[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n147_1_s1/I2 |
| 5.834 | 0.609 | tINS | FF | 1 | R11C5[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n147_1_s1/F |
| 8.240 | 2.406 | tNET | FF | 2 | R11C3[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n211_1_s/CIN |
| 8.658 | 0.417 | tINS | FF | 1 | R11C3[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n211_1_s/SUM |
| 8.658 | 0.000 | tNET | FF | 1 | R11C3[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_0_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R11C3[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_0_s1/CLK |
| 39.884 | -0.296 | tSu | 1 | R11C3[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_0_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 2.244, 26.477%; route: 5.893, 69.516%; tC2Q: 0.340, 4.006% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path15
Path Summary:
| Slack | 31.821 |
| Data Arrival Time | 8.327 |
| Data Required Time | 40.148 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_5_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R11C4[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1/CLK |
| 0.520 | 0.340 | tC2Q | RR | 2 | R11C4[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1/Q |
| 0.831 | 0.311 | tNET | RR | 1 | R11C4[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s4/I3 |
| 1.596 | 0.765 | tINS | RF | 2 | R11C4[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s4/F |
| 2.195 | 0.599 | tNET | FF | 1 | R12C3[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Full_d_s/I0 |
| 2.960 | 0.765 | tINS | FF | 28 | R12C3[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Full_d_s/F |
| 4.421 | 1.461 | tNET | FF | 1 | R15C5[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1640_s4/I0 |
| 5.030 | 0.609 | tINS | FF | 9 | R15C5[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1640_s4/F |
| 5.046 | 0.016 | tNET | FF | 1 | R15C5[3][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1486_s3/I3 |
| 5.640 | 0.594 | tINS | FR | 3 | R15C5[3][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1486_s3/F |
| 5.955 | 0.315 | tNET | RR | 1 | R15C4[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_7_s8/I0 |
| 6.419 | 0.464 | tINS | RF | 8 | R15C4[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_7_s8/F |
| 7.019 | 0.600 | tNET | FF | 1 | R14C5[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_5_s5/I3 |
| 7.805 | 0.786 | tINS | FR | 1 | R14C5[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_5_s5/F |
| 8.327 | 0.522 | tNET | RR | 1 | R13C5[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_5_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R13C5[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_5_s0/CLK |
| 40.148 | -0.032 | tSu | 1 | R13C5[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_5_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 7 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 3.983, 48.891%; route: 3.824, 46.940%; tC2Q: 0.340, 4.169% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path16
Path Summary:
| Slack | 31.847 |
| Data Arrival Time | 8.301 |
| Data Required Time | 40.148 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/counter_10_s2 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_11_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R15C13[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/counter_10_s2/CLK |
| 0.520 | 0.340 | tC2Q | RF | 4 | R15C13[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/counter_10_s2/Q |
| 1.379 | 0.859 | tNET | FF | 1 | R18C13[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n557_s5/I1 |
| 1.988 | 0.609 | tINS | FF | 2 | R18C13[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n557_s5/F |
| 2.600 | 0.612 | tNET | FF | 1 | R16C13[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_7_s6/I2 |
| 3.365 | 0.765 | tINS | FF | 18 | R16C13[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_7_s6/F |
| 4.709 | 1.344 | tNET | FF | 1 | R12C11[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_15_s4/I0 |
| 5.318 | 0.609 | tINS | FF | 9 | R12C11[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_15_s4/F |
| 6.192 | 0.874 | tNET | FF | 1 | R14C12[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_15_s3/I0 |
| 6.952 | 0.760 | tINS | FR | 8 | R14C12[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_15_s3/F |
| 8.301 | 1.349 | tNET | RR | 1 | R12C10[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_11_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R12C10[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_11_s0/CLK |
| 40.148 | -0.032 | tSu | 1 | R12C10[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_11_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 2.743, 33.780%; route: 5.038, 62.038%; tC2Q: 0.340, 4.182% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path17
Path Summary:
| Slack | 31.889 |
| Data Arrival Time | 7.996 |
| Data Required Time | 39.884 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/rden_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R12C17[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/rden_s0/CLK |
| 0.520 | 0.340 | tC2Q | RF | 1 | R12C17[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/rden_s0/Q |
| 1.596 | 1.076 | tNET | FF | 1 | R12C6[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_rden_s0/I1 |
| 2.361 | 0.765 | tINS | FF | 6 | R12C6[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_rden_s0/F |
| 3.091 | 0.730 | tNET | FF | 1 | R11C7[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n101_s0/I1 |
| 3.700 | 0.609 | tINS | FF | 1 | R11C7[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n101_s0/F |
| 3.949 | 0.249 | tNET | FF | 2 | R11C7[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_0_s/I1 |
| 4.357 | 0.408 | tINS | FR | 1 | R11C7[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_0_s/COUT |
| 4.357 | 0.000 | tNET | RR | 2 | R11C7[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_1_s/CIN |
| 4.399 | 0.042 | tINS | RF | 1 | R11C7[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_1_s/COUT |
| 4.399 | 0.000 | tNET | FF | 2 | R11C7[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_2_s/CIN |
| 4.441 | 0.042 | tINS | FF | 1 | R11C7[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_2_s/COUT |
| 4.441 | 0.000 | tNET | FF | 2 | R11C7[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_3_s/CIN |
| 4.484 | 0.042 | tINS | FF | 1 | R11C7[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_3_s/COUT |
| 4.484 | 0.000 | tNET | FF | 2 | R11C7[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_4_s/CIN |
| 4.526 | 0.042 | tINS | FF | 1 | R11C7[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_4_s/COUT |
| 4.526 | 0.000 | tNET | FF | 2 | R11C7[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_5_s/CIN |
| 4.568 | 0.042 | tINS | FF | 1 | R11C7[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_5_s/COUT |
| 4.568 | 0.000 | tNET | FF | 2 | R11C8[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_6_s/CIN |
| 4.610 | 0.042 | tINS | FF | 1 | R11C8[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_6_s/COUT |
| 4.610 | 0.000 | tNET | FF | 2 | R11C8[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_7_s/CIN |
| 5.028 | 0.417 | tINS | FF | 3 | R11C8[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rbin_next_7_s/SUM |
| 5.877 | 0.850 | tNET | FF | 2 | R12C8[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n245_s0/I0 |
| 6.587 | 0.710 | tINS | FF | 1 | R12C8[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n245_s0/COUT |
| 6.587 | 0.000 | tNET | FF | 2 | R12C8[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n246_s0/CIN |
| 6.629 | 0.042 | tINS | FF | 1 | R12C8[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n246_s0/COUT |
| 6.629 | 0.000 | tNET | FF | 2 | R12C8[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n247_s0/CIN |
| 6.671 | 0.042 | tINS | FF | 1 | R12C8[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n247_s0/COUT |
| 6.671 | 0.000 | tNET | FF | 2 | R12C8[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n248_s0/CIN |
| 6.714 | 0.042 | tINS | FF | 1 | R12C8[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n248_s0/COUT |
| 6.714 | 0.000 | tNET | FF | 2 | R12C9[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n249_s0/CIN |
| 6.756 | 0.042 | tINS | FF | 2 | R12C9[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n249_s0/COUT |
| 7.181 | 0.425 | tNET | FF | 1 | R12C9[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rempty_val_s1/I0 |
| 7.996 | 0.814 | tINS | FF | 1 | R12C9[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/rempty_val_s1/F |
| 7.996 | 0.000 | tNET | FF | 1 | R12C9[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R12C9[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0/CLK |
| 39.884 | -0.296 | tSu | 1 | R12C9[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 9 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 4.145, 53.040%; route: 3.330, 42.614%; tC2Q: 0.340, 4.346% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path18
Path Summary:
| Slack | 31.902 |
| Data Arrival Time | 8.247 |
| Data Required Time | 40.148 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_0_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R11C4[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1/CLK |
| 0.520 | 0.340 | tC2Q | RR | 2 | R11C4[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1/Q |
| 0.831 | 0.311 | tNET | RR | 1 | R11C4[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s4/I3 |
| 1.596 | 0.765 | tINS | RF | 2 | R11C4[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s4/F |
| 2.195 | 0.599 | tNET | FF | 1 | R12C3[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Full_d_s/I0 |
| 2.960 | 0.765 | tINS | FF | 28 | R12C3[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Full_d_s/F |
| 4.421 | 1.461 | tNET | FF | 1 | R15C5[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1640_s4/I0 |
| 5.030 | 0.609 | tINS | FF | 9 | R15C5[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1640_s4/F |
| 5.046 | 0.016 | tNET | FF | 1 | R15C5[3][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1486_s3/I3 |
| 5.640 | 0.594 | tINS | FR | 3 | R15C5[3][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1486_s3/F |
| 5.955 | 0.315 | tNET | RR | 1 | R15C4[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_7_s8/I0 |
| 6.419 | 0.464 | tINS | RF | 8 | R15C4[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_7_s8/F |
| 7.403 | 0.984 | tNET | FF | 1 | R18C5[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_0_s5/I3 |
| 7.998 | 0.594 | tINS | FR | 1 | R18C5[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_0_s5/F |
| 8.247 | 0.249 | tNET | RR | 1 | R18C5[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_0_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R18C5[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_0_s0/CLK |
| 40.148 | -0.032 | tSu | 1 | R18C5[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_0_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 7 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 3.791, 46.997%; route: 3.936, 48.792%; tC2Q: 0.340, 4.210% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path19
Path Summary:
| Slack | 31.983 |
| Data Arrival Time | 7.901 |
| Data Required Time | 39.884 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_14_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_model_state_1_s2 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R11C11[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_14_s0/CLK |
| 0.520 | 0.340 | tC2Q | RF | 3 | R11C11[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_14_s0/Q |
| 2.804 | 2.283 | tNET | FF | 2 | R13C10[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n476_s0/I1 |
| 3.578 | 0.774 | tINS | FF | 1 | R13C10[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n476_s0/COUT |
| 3.578 | 0.000 | tNET | FF | 2 | R13C10[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n477_s0/CIN |
| 3.620 | 0.042 | tINS | FF | 2 | R13C10[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n477_s0/COUT |
| 4.997 | 1.376 | tNET | FF | 1 | R17C11[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n641_s13/I0 |
| 5.460 | 0.463 | tINS | FR | 2 | R17C11[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n641_s13/F |
| 5.772 | 0.312 | tNET | RR | 1 | R16C11[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n640_s19/I2 |
| 6.536 | 0.765 | tINS | RF | 2 | R16C11[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n640_s19/F |
| 7.136 | 0.600 | tNET | FF | 1 | R17C10[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n640_s17/I1 |
| 7.901 | 0.765 | tINS | FF | 1 | R17C10[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n640_s17/F |
| 7.901 | 0.000 | tNET | FF | 1 | R17C10[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_model_state_1_s2/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R17C10[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_model_state_1_s2/CLK |
| 39.884 | -0.296 | tSu | 1 | R17C10[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/FIFO_model_state_1_s2 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 2.809, 36.385%; route: 4.572, 59.216%; tC2Q: 0.340, 4.399% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path20
Path Summary:
| Slack | 32.058 |
| Data Arrival Time | 8.090 |
| Data Required Time | 40.148 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_3_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R11C4[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1/CLK |
| 0.520 | 0.340 | tC2Q | RR | 2 | R11C4[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1/Q |
| 0.831 | 0.311 | tNET | RR | 1 | R11C4[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s4/I3 |
| 1.596 | 0.765 | tINS | RF | 2 | R11C4[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s4/F |
| 2.195 | 0.599 | tNET | FF | 1 | R12C3[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Full_d_s/I0 |
| 2.960 | 0.765 | tINS | FF | 28 | R12C3[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Full_d_s/F |
| 4.421 | 1.461 | tNET | FF | 1 | R15C5[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1640_s4/I0 |
| 5.030 | 0.609 | tINS | FF | 9 | R15C5[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1640_s4/F |
| 5.046 | 0.016 | tNET | FF | 1 | R15C5[3][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1486_s3/I3 |
| 5.640 | 0.594 | tINS | FR | 3 | R15C5[3][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1486_s3/F |
| 5.955 | 0.315 | tNET | RR | 1 | R15C4[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_7_s8/I0 |
| 6.419 | 0.464 | tINS | RF | 8 | R15C4[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_7_s8/F |
| 7.044 | 0.625 | tNET | FF | 1 | R16C5[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_3_s5/I3 |
| 7.507 | 0.463 | tINS | FR | 1 | R16C5[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_3_s5/F |
| 8.090 | 0.583 | tNET | RR | 1 | R15C5[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_3_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R15C5[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_3_s0/CLK |
| 40.148 | -0.032 | tSu | 1 | R15C5[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_3_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 7 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 3.660, 46.270%; route: 3.910, 49.436%; tC2Q: 0.340, 4.294% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path21
Path Summary:
| Slack | 32.090 |
| Data Arrival Time | 8.058 |
| Data Required Time | 40.148 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_6_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R11C4[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1/CLK |
| 0.520 | 0.340 | tC2Q | RR | 2 | R11C4[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1/Q |
| 0.831 | 0.311 | tNET | RR | 1 | R11C4[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s4/I3 |
| 1.596 | 0.765 | tINS | RF | 2 | R11C4[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s4/F |
| 2.195 | 0.599 | tNET | FF | 1 | R12C3[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Full_d_s/I0 |
| 2.960 | 0.765 | tINS | FF | 28 | R12C3[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Full_d_s/F |
| 4.421 | 1.461 | tNET | FF | 1 | R15C5[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1640_s4/I0 |
| 5.030 | 0.609 | tINS | FF | 9 | R15C5[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1640_s4/F |
| 5.046 | 0.016 | tNET | FF | 1 | R15C5[3][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1486_s3/I3 |
| 5.640 | 0.594 | tINS | FR | 3 | R15C5[3][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1486_s3/F |
| 5.955 | 0.315 | tNET | RR | 1 | R15C4[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_7_s8/I0 |
| 6.419 | 0.464 | tINS | RF | 8 | R15C4[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_7_s8/F |
| 7.023 | 0.603 | tNET | FF | 1 | R13C5[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_6_s5/I3 |
| 7.809 | 0.786 | tINS | FR | 1 | R13C5[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_6_s5/F |
| 8.058 | 0.249 | tNET | RR | 1 | R13C5[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_6_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R13C5[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_6_s0/CLK |
| 40.148 | -0.032 | tSu | 1 | R13C5[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_6_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 7 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 3.983, 50.561%; route: 3.555, 45.128%; tC2Q: 0.340, 4.311% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path22
Path Summary:
| Slack | 32.090 |
| Data Arrival Time | 8.058 |
| Data Required Time | 40.148 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_7_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R11C4[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1/CLK |
| 0.520 | 0.340 | tC2Q | RR | 2 | R11C4[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1/Q |
| 0.831 | 0.311 | tNET | RR | 1 | R11C4[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s4/I3 |
| 1.596 | 0.765 | tINS | RF | 2 | R11C4[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s4/F |
| 2.195 | 0.599 | tNET | FF | 1 | R12C3[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Full_d_s/I0 |
| 2.960 | 0.765 | tINS | FF | 28 | R12C3[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Full_d_s/F |
| 4.421 | 1.461 | tNET | FF | 1 | R15C5[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1640_s4/I0 |
| 5.030 | 0.609 | tINS | FF | 9 | R15C5[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1640_s4/F |
| 5.046 | 0.016 | tNET | FF | 1 | R15C5[3][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1486_s3/I3 |
| 5.640 | 0.594 | tINS | FR | 3 | R15C5[3][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1486_s3/F |
| 5.955 | 0.315 | tNET | RR | 1 | R15C4[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_7_s8/I0 |
| 6.419 | 0.464 | tINS | RF | 8 | R15C4[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_7_s8/F |
| 7.023 | 0.603 | tNET | FF | 1 | R13C5[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_7_s5/I3 |
| 7.809 | 0.786 | tINS | FR | 1 | R13C5[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_7_s5/F |
| 8.058 | 0.249 | tNET | RR | 1 | R13C5[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_7_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R13C5[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_7_s0/CLK |
| 40.148 | -0.032 | tSu | 1 | R13C5[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_7_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 7 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 3.983, 50.561%; route: 3.555, 45.128%; tC2Q: 0.340, 4.311% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path23
Path Summary:
| Slack | 32.094 |
| Data Arrival Time | 7.790 |
| Data Required Time | 39.884 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_0_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R11C4[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1/CLK |
| 0.520 | 0.340 | tC2Q | RR | 2 | R11C4[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1/Q |
| 0.831 | 0.311 | tNET | RR | 1 | R11C4[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s4/I3 |
| 1.596 | 0.765 | tINS | RF | 2 | R11C4[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/n7_s4/F |
| 2.195 | 0.599 | tNET | FF | 1 | R12C3[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Full_d_s/I0 |
| 2.960 | 0.765 | tINS | FF | 28 | R12C3[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Full_d_s/F |
| 4.421 | 1.461 | tNET | FF | 1 | R15C5[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1640_s4/I0 |
| 5.030 | 0.609 | tINS | FF | 9 | R15C5[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1640_s4/F |
| 6.363 | 1.333 | tNET | FF | 1 | R18C5[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1598_s4/I2 |
| 7.177 | 0.814 | tINS | FF | 1 | R18C5[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1598_s4/F |
| 7.181 | 0.004 | tNET | FF | 1 | R18C5[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1598_s3/I0 |
| 7.790 | 0.609 | tINS | FF | 1 | R18C5[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1598_s3/F |
| 7.790 | 0.000 | tNET | FF | 1 | R18C5[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_0_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R18C5[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_0_s0/CLK |
| 39.884 | -0.296 | tSu | 1 | R18C5[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_fifo_in_0_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 3.562, 46.807%; route: 3.708, 48.730%; tC2Q: 0.340, 4.463% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path24
Path Summary:
| Slack | 32.119 |
| Data Arrival Time | 8.029 |
| Data Required Time | 40.148 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/counter_10_s2 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_14_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R15C13[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/counter_10_s2/CLK |
| 0.520 | 0.340 | tC2Q | RF | 4 | R15C13[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/counter_10_s2/Q |
| 1.379 | 0.859 | tNET | FF | 1 | R18C13[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n557_s5/I1 |
| 1.988 | 0.609 | tINS | FF | 2 | R18C13[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n557_s5/F |
| 2.600 | 0.612 | tNET | FF | 1 | R16C13[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_7_s6/I2 |
| 3.365 | 0.765 | tINS | FF | 18 | R16C13[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_7_s6/F |
| 4.709 | 1.344 | tNET | FF | 1 | R12C11[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_15_s4/I0 |
| 5.318 | 0.609 | tINS | FF | 9 | R12C11[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_15_s4/F |
| 6.192 | 0.874 | tNET | FF | 1 | R14C12[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_15_s3/I0 |
| 6.952 | 0.760 | tINS | FR | 8 | R14C12[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_15_s3/F |
| 8.029 | 1.077 | tNET | RR | 1 | R11C11[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_14_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R11C11[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_14_s0/CLK |
| 40.148 | -0.032 | tSu | 1 | R11C11[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_14_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 2.743, 34.952%; route: 4.766, 60.721%; tC2Q: 0.340, 4.327% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path25
Path Summary:
| Slack | 32.123 |
| Data Arrival Time | 8.026 |
| Data Required Time | 40.148 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/counter_10_s2 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_8_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R15C13[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/counter_10_s2/CLK |
| 0.520 | 0.340 | tC2Q | RF | 4 | R15C13[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/counter_10_s2/Q |
| 1.379 | 0.859 | tNET | FF | 1 | R18C13[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n557_s5/I1 |
| 1.988 | 0.609 | tINS | FF | 2 | R18C13[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n557_s5/F |
| 2.600 | 0.612 | tNET | FF | 1 | R16C13[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_7_s6/I2 |
| 3.365 | 0.765 | tINS | FF | 18 | R16C13[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_7_s6/F |
| 4.709 | 1.344 | tNET | FF | 1 | R12C11[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_15_s4/I0 |
| 5.318 | 0.609 | tINS | FF | 9 | R12C11[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_15_s4/F |
| 6.192 | 0.874 | tNET | FF | 1 | R14C12[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_15_s3/I0 |
| 6.952 | 0.760 | tINS | FR | 8 | R14C12[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_15_s3/F |
| 8.026 | 1.073 | tNET | RR | 1 | R11C10[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_8_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R11C10[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_8_s0/CLK |
| 40.148 | -0.032 | tSu | 1 | R11C10[3][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_reg_8_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 2.743, 34.967%; route: 4.762, 60.704%; tC2Q: 0.340, 4.329% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 0.439 |
| Data Arrival Time | 0.584 |
| Data Required Time | 0.146 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/in_reg_enable_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/in_reg_0_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R14C17[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/in_reg_enable_s0/CLK |
| 0.383 | 0.247 | tC2Q | RR | 16 | R14C17[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/in_reg_enable_s0/Q |
| 0.584 | 0.201 | tNET | RR | 1 | R16C17[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/in_reg_0_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R16C17[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/in_reg_0_s0/CLK |
| 0.146 | 0.009 | tHld | 1 | R16C17[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/in_reg_0_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.201, 44.847%; tC2Q: 0.247, 55.153% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path2
Path Summary:
| Slack | 0.524 |
| Data Arrival Time | 0.661 |
| Data Required Time | 0.136 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_13_s1 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_13_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R17C6[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_13_s1/CLK |
| 0.383 | 0.247 | tC2Q | RR | 2 | R17C6[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_13_s1/Q |
| 0.385 | 0.002 | tNET | RR | 1 | R17C6[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1363_s4/I1 |
| 0.661 | 0.276 | tINS | RF | 1 | R17C6[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1363_s4/F |
| 0.661 | 0.000 | tNET | FF | 1 | R17C6[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_13_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R17C6[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_13_s1/CLK |
| 0.136 | 0.000 | tHld | 1 | R17C6[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_13_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path3
Path Summary:
| Slack | 0.524 |
| Data Arrival Time | 0.661 |
| Data Required Time | 0.136 |
| From | led_s1 |
| To | led_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R12C3[0][A] | led_s1/CLK |
| 0.383 | 0.247 | tC2Q | RR | 2 | R12C3[0][A] | led_s1/Q |
| 0.385 | 0.002 | tNET | RR | 1 | R12C3[0][A] | n144_s2/I0 |
| 0.661 | 0.276 | tINS | RF | 1 | R12C3[0][A] | n144_s2/F |
| 0.661 | 0.000 | tNET | FF | 1 | R12C3[0][A] | led_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R12C3[0][A] | led_s1/CLK |
| 0.136 | 0.000 | tHld | 1 | R12C3[0][A] | led_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path4
Path Summary:
| Slack | 0.524 |
| Data Arrival Time | 0.661 |
| Data Required Time | 0.136 |
| From | led_cnt_31_s0 |
| To | led_cnt_31_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R15C2[1][A] | led_cnt_31_s0/CLK |
| 0.383 | 0.247 | tC2Q | RR | 2 | R15C2[1][A] | led_cnt_31_s0/Q |
| 0.385 | 0.002 | tNET | RR | 1 | R15C2[1][A] | n58_s2/I2 |
| 0.661 | 0.276 | tINS | RF | 1 | R15C2[1][A] | n58_s2/F |
| 0.661 | 0.000 | tNET | FF | 1 | R15C2[1][A] | led_cnt_31_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R15C2[1][A] | led_cnt_31_s0/CLK |
| 0.136 | 0.000 | tHld | 1 | R15C2[1][A] | led_cnt_31_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path5
Path Summary:
| Slack | 0.524 |
| Data Arrival Time | 0.661 |
| Data Required Time | 0.136 |
| From | led_cnt_1_s0 |
| To | led_cnt_1_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R11C2[0][A] | led_cnt_1_s0/CLK |
| 0.383 | 0.247 | tC2Q | RR | 4 | R11C2[0][A] | led_cnt_1_s0/Q |
| 0.385 | 0.002 | tNET | RR | 1 | R11C2[0][A] | n88_s2/I1 |
| 0.661 | 0.276 | tINS | RF | 1 | R11C2[0][A] | n88_s2/F |
| 0.661 | 0.000 | tNET | FF | 1 | R11C2[0][A] | led_cnt_1_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R11C2[0][A] | led_cnt_1_s0/CLK |
| 0.136 | 0.000 | tHld | 1 | R11C2[0][A] | led_cnt_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path6
Path Summary:
| Slack | 0.524 |
| Data Arrival Time | 0.661 |
| Data Required Time | 0.136 |
| From | led_cnt_2_s0 |
| To | led_cnt_2_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R11C2[1][A] | led_cnt_2_s0/CLK |
| 0.383 | 0.247 | tC2Q | RR | 3 | R11C2[1][A] | led_cnt_2_s0/Q |
| 0.385 | 0.002 | tNET | RR | 1 | R11C2[1][A] | n87_s2/I2 |
| 0.661 | 0.276 | tINS | RF | 1 | R11C2[1][A] | n87_s2/F |
| 0.661 | 0.000 | tNET | FF | 1 | R11C2[1][A] | led_cnt_2_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R11C2[1][A] | led_cnt_2_s0/CLK |
| 0.136 | 0.000 | tHld | 1 | R11C2[1][A] | led_cnt_2_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path7
Path Summary:
| Slack | 0.524 |
| Data Arrival Time | 0.661 |
| Data Required Time | 0.136 |
| From | led_cnt_5_s0 |
| To | led_cnt_5_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R15C2[0][A] | led_cnt_5_s0/CLK |
| 0.383 | 0.247 | tC2Q | RR | 3 | R15C2[0][A] | led_cnt_5_s0/Q |
| 0.385 | 0.002 | tNET | RR | 1 | R15C2[0][A] | n84_s2/I2 |
| 0.661 | 0.276 | tINS | RF | 1 | R15C2[0][A] | n84_s2/F |
| 0.661 | 0.000 | tNET | FF | 1 | R15C2[0][A] | led_cnt_5_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R15C2[0][A] | led_cnt_5_s0/CLK |
| 0.136 | 0.000 | tHld | 1 | R15C2[0][A] | led_cnt_5_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path8
Path Summary:
| Slack | 0.524 |
| Data Arrival Time | 0.661 |
| Data Required Time | 0.136 |
| From | led_cnt_7_s0 |
| To | led_cnt_7_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R18C2[0][A] | led_cnt_7_s0/CLK |
| 0.383 | 0.247 | tC2Q | RR | 3 | R18C2[0][A] | led_cnt_7_s0/Q |
| 0.385 | 0.002 | tNET | RR | 1 | R18C2[0][A] | n82_s2/I2 |
| 0.661 | 0.276 | tINS | RF | 1 | R18C2[0][A] | n82_s2/F |
| 0.661 | 0.000 | tNET | FF | 1 | R18C2[0][A] | led_cnt_7_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R18C2[0][A] | led_cnt_7_s0/CLK |
| 0.136 | 0.000 | tHld | 1 | R18C2[0][A] | led_cnt_7_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path9
Path Summary:
| Slack | 0.524 |
| Data Arrival Time | 0.661 |
| Data Required Time | 0.136 |
| From | led_cnt_13_s0 |
| To | led_cnt_13_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R18C2[1][A] | led_cnt_13_s0/CLK |
| 0.383 | 0.247 | tC2Q | RR | 6 | R18C2[1][A] | led_cnt_13_s0/Q |
| 0.385 | 0.002 | tNET | RR | 1 | R18C2[1][A] | n76_s2/I1 |
| 0.661 | 0.276 | tINS | RF | 1 | R18C2[1][A] | n76_s2/F |
| 0.661 | 0.000 | tNET | FF | 1 | R18C2[1][A] | led_cnt_13_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R18C2[1][A] | led_cnt_13_s0/CLK |
| 0.136 | 0.000 | tHld | 1 | R18C2[1][A] | led_cnt_13_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path10
Path Summary:
| Slack | 0.524 |
| Data Arrival Time | 0.661 |
| Data Required Time | 0.136 |
| From | led_cnt_14_s0 |
| To | led_cnt_14_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R14C3[1][A] | led_cnt_14_s0/CLK |
| 0.383 | 0.247 | tC2Q | RR | 5 | R14C3[1][A] | led_cnt_14_s0/Q |
| 0.385 | 0.002 | tNET | RR | 1 | R14C3[1][A] | n75_s2/I3 |
| 0.661 | 0.276 | tINS | RF | 1 | R14C3[1][A] | n75_s2/F |
| 0.661 | 0.000 | tNET | FF | 1 | R14C3[1][A] | led_cnt_14_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R14C3[1][A] | led_cnt_14_s0/CLK |
| 0.136 | 0.000 | tHld | 1 | R14C3[1][A] | led_cnt_14_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path11
Path Summary:
| Slack | 0.524 |
| Data Arrival Time | 0.661 |
| Data Required Time | 0.136 |
| From | led_cnt_16_s0 |
| To | led_cnt_16_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R17C2[0][A] | led_cnt_16_s0/CLK |
| 0.383 | 0.247 | tC2Q | RR | 3 | R17C2[0][A] | led_cnt_16_s0/Q |
| 0.385 | 0.002 | tNET | RR | 1 | R17C2[0][A] | n73_s2/I1 |
| 0.661 | 0.276 | tINS | RF | 1 | R17C2[0][A] | n73_s2/F |
| 0.661 | 0.000 | tNET | FF | 1 | R17C2[0][A] | led_cnt_16_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R17C2[0][A] | led_cnt_16_s0/CLK |
| 0.136 | 0.000 | tHld | 1 | R17C2[0][A] | led_cnt_16_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path12
Path Summary:
| Slack | 0.524 |
| Data Arrival Time | 0.661 |
| Data Required Time | 0.136 |
| From | led_cnt_21_s0 |
| To | led_cnt_21_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R12C2[0][A] | led_cnt_21_s0/CLK |
| 0.383 | 0.247 | tC2Q | RR | 2 | R12C2[0][A] | led_cnt_21_s0/Q |
| 0.385 | 0.002 | tNET | RR | 1 | R12C2[0][A] | n68_s2/I3 |
| 0.661 | 0.276 | tINS | RF | 1 | R12C2[0][A] | n68_s2/F |
| 0.661 | 0.000 | tNET | FF | 1 | R12C2[0][A] | led_cnt_21_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R12C2[0][A] | led_cnt_21_s0/CLK |
| 0.136 | 0.000 | tHld | 1 | R12C2[0][A] | led_cnt_21_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path13
Path Summary:
| Slack | 0.524 |
| Data Arrival Time | 0.661 |
| Data Required Time | 0.136 |
| From | led_cnt_25_s0 |
| To | led_cnt_25_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R14C2[0][A] | led_cnt_25_s0/CLK |
| 0.383 | 0.247 | tC2Q | RR | 4 | R14C2[0][A] | led_cnt_25_s0/Q |
| 0.385 | 0.002 | tNET | RR | 1 | R14C2[0][A] | n64_s4/I3 |
| 0.661 | 0.276 | tINS | RF | 1 | R14C2[0][A] | n64_s4/F |
| 0.661 | 0.000 | tNET | FF | 1 | R14C2[0][A] | led_cnt_25_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R14C2[0][A] | led_cnt_25_s0/CLK |
| 0.136 | 0.000 | tHld | 1 | R14C2[0][A] | led_cnt_25_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path14
Path Summary:
| Slack | 0.525 |
| Data Arrival Time | 0.662 |
| Data Required Time | 0.136 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/RXRDY_s5 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/RXRDY_s5 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R17C10[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/RXRDY_s5/CLK |
| 0.383 | 0.247 | tC2Q | RR | 6 | R17C10[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/RXRDY_s5/Q |
| 0.386 | 0.003 | tNET | RR | 1 | R17C10[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n614_s47/I1 |
| 0.662 | 0.276 | tINS | RF | 1 | R17C10[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n614_s47/F |
| 0.662 | 0.000 | tNET | FF | 1 | R17C10[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/RXRDY_s5/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R17C10[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/RXRDY_s5/CLK |
| 0.136 | 0.000 | tHld | 1 | R17C10[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/RXRDY_s5 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path15
Path Summary:
| Slack | 0.525 |
| Data Arrival Time | 0.662 |
| Data Required Time | 0.136 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/length_flag_s2 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/length_flag_s2 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R18C10[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/length_flag_s2/CLK |
| 0.383 | 0.247 | tC2Q | RR | 7 | R18C10[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/length_flag_s2/Q |
| 0.386 | 0.003 | tNET | RR | 1 | R18C10[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n674_s3/I3 |
| 0.662 | 0.276 | tINS | RF | 1 | R18C10[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n674_s3/F |
| 0.662 | 0.000 | tNET | FF | 1 | R18C10[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/length_flag_s2/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R18C10[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/length_flag_s2/CLK |
| 0.136 | 0.000 | tHld | 1 | R18C10[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/length_flag_s2 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path16
Path Summary:
| Slack | 0.525 |
| Data Arrival Time | 0.662 |
| Data Required Time | 0.136 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_add_0_s1 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_add_0_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R15C5[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_add_0_s1/CLK |
| 0.383 | 0.247 | tC2Q | RR | 4 | R15C5[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_add_0_s1/Q |
| 0.386 | 0.003 | tNET | RR | 1 | R15C5[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1640_s5/I2 |
| 0.662 | 0.276 | tINS | RF | 1 | R15C5[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1640_s5/F |
| 0.662 | 0.000 | tNET | FF | 1 | R15C5[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_add_0_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R15C5[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_add_0_s1/CLK |
| 0.136 | 0.000 | tHld | 1 | R15C5[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_add_0_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path17
Path Summary:
| Slack | 0.525 |
| Data Arrival Time | 0.662 |
| Data Required Time | 0.136 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_bit_cnt_2_s1 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_bit_cnt_2_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R17C3[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_bit_cnt_2_s1/CLK |
| 0.383 | 0.247 | tC2Q | RR | 5 | R17C3[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_bit_cnt_2_s1/Q |
| 0.386 | 0.003 | tNET | RR | 1 | R17C3[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1588_s3/I0 |
| 0.662 | 0.276 | tINS | RF | 1 | R17C3[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1588_s3/F |
| 0.662 | 0.000 | tNET | FF | 1 | R17C3[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_bit_cnt_2_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R17C3[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_bit_cnt_2_s1/CLK |
| 0.136 | 0.000 | tHld | 1 | R17C3[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_bit_cnt_2_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path18
Path Summary:
| Slack | 0.525 |
| Data Arrival Time | 0.662 |
| Data Required Time | 0.136 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_10_s1 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_10_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R17C6[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_10_s1/CLK |
| 0.383 | 0.247 | tC2Q | RR | 5 | R17C6[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_10_s1/Q |
| 0.386 | 0.003 | tNET | RR | 1 | R17C6[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1366_s4/I1 |
| 0.662 | 0.276 | tINS | RF | 1 | R17C6[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1366_s4/F |
| 0.662 | 0.000 | tNET | FF | 1 | R17C6[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_10_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R17C6[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_10_s1/CLK |
| 0.136 | 0.000 | tHld | 1 | R17C6[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_10_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path19
Path Summary:
| Slack | 0.525 |
| Data Arrival Time | 0.662 |
| Data Required Time | 0.136 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_14_s1 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_14_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R16C7[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_14_s1/CLK |
| 0.383 | 0.247 | tC2Q | RR | 4 | R16C7[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_14_s1/Q |
| 0.386 | 0.003 | tNET | RR | 1 | R16C7[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1362_s4/I1 |
| 0.662 | 0.276 | tINS | RF | 1 | R16C7[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1362_s4/F |
| 0.662 | 0.000 | tNET | FF | 1 | R16C7[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_14_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R16C7[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_14_s1/CLK |
| 0.136 | 0.000 | tHld | 1 | R16C7[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/send_counter_14_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path20
Path Summary:
| Slack | 0.525 |
| Data Arrival Time | 0.662 |
| Data Required Time | 0.136 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_1_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_1_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R14C7[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_1_s0/CLK |
| 0.383 | 0.247 | tC2Q | RR | 4 | R14C7[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_1_s0/Q |
| 0.386 | 0.003 | tNET | RR | 1 | R14C7[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1435_s2/I1 |
| 0.662 | 0.276 | tINS | RF | 1 | R14C7[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1435_s2/F |
| 0.662 | 0.000 | tNET | FF | 1 | R14C7[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_1_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R14C7[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_1_s0/CLK |
| 0.136 | 0.000 | tHld | 1 | R14C7[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path21
Path Summary:
| Slack | 0.525 |
| Data Arrival Time | 0.662 |
| Data Required Time | 0.136 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_2_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_2_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R13C7[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_2_s0/CLK |
| 0.383 | 0.247 | tC2Q | RR | 4 | R13C7[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_2_s0/Q |
| 0.386 | 0.003 | tNET | RR | 1 | R13C7[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1434_s4/I1 |
| 0.662 | 0.276 | tINS | RF | 1 | R13C7[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1434_s4/F |
| 0.662 | 0.000 | tNET | FF | 1 | R13C7[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_2_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R13C7[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_2_s0/CLK |
| 0.136 | 0.000 | tHld | 1 | R13C7[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/clk_i_2_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path22
Path Summary:
| Slack | 0.525 |
| Data Arrival Time | 0.662 |
| Data Required Time | 0.136 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/counter_1_s3 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/counter_1_s3 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R18C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/counter_1_s3/CLK |
| 0.383 | 0.247 | tC2Q | RR | 6 | R18C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/counter_1_s3/Q |
| 0.386 | 0.003 | tNET | RR | 1 | R18C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/n62_s3/I3 |
| 0.662 | 0.276 | tINS | RF | 1 | R18C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/n62_s3/F |
| 0.662 | 0.000 | tNET | FF | 1 | R18C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/counter_1_s3/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R18C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/counter_1_s3/CLK |
| 0.136 | 0.000 | tHld | 1 | R18C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/counter_1_s3 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path23
Path Summary:
| Slack | 0.525 |
| Data Arrival Time | 0.662 |
| Data Required Time | 0.136 |
| From | led_cnt_10_s0 |
| To | led_cnt_10_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R17C2[1][A] | led_cnt_10_s0/CLK |
| 0.383 | 0.247 | tC2Q | RR | 4 | R17C2[1][A] | led_cnt_10_s0/Q |
| 0.386 | 0.003 | tNET | RR | 1 | R17C2[1][A] | n79_s2/I0 |
| 0.662 | 0.276 | tINS | RF | 1 | R17C2[1][A] | n79_s2/F |
| 0.662 | 0.000 | tNET | FF | 1 | R17C2[1][A] | led_cnt_10_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R17C2[1][A] | led_cnt_10_s0/CLK |
| 0.136 | 0.000 | tHld | 1 | R17C2[1][A] | led_cnt_10_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path24
Path Summary:
| Slack | 0.525 |
| Data Arrival Time | 0.662 |
| Data Required Time | 0.136 |
| From | led_cnt_27_s0 |
| To | led_cnt_27_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R14C2[1][A] | led_cnt_27_s0/CLK |
| 0.383 | 0.247 | tC2Q | RR | 4 | R14C2[1][A] | led_cnt_27_s0/Q |
| 0.386 | 0.003 | tNET | RR | 1 | R14C2[1][A] | n62_s2/I2 |
| 0.662 | 0.276 | tINS | RF | 1 | R14C2[1][A] | n62_s2/F |
| 0.662 | 0.000 | tNET | FF | 1 | R14C2[1][A] | led_cnt_27_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R14C2[1][A] | led_cnt_27_s0/CLK |
| 0.136 | 0.000 | tHld | 1 | R14C2[1][A] | led_cnt_27_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path25
Path Summary:
| Slack | 0.526 |
| Data Arrival Time | 0.663 |
| Data Required Time | 0.136 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_bit_cnt_0_s1 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_bit_cnt_0_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R17C3[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_bit_cnt_0_s1/CLK |
| 0.383 | 0.247 | tC2Q | RR | 8 | R17C3[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_bit_cnt_0_s1/Q |
| 0.387 | 0.003 | tNET | RR | 1 | R17C3[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1590_s4/I0 |
| 0.663 | 0.276 | tINS | RF | 1 | R17C3[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/n1590_s4/F |
| 0.663 | 0.000 | tNET | FF | 1 | R17C3[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_bit_cnt_0_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R17C3[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_bit_cnt_0_s1/CLK |
| 0.136 | 0.000 | tHld | 1 | R17C3[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_bit_cnt_0_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 37.795 |
| Data Arrival Time | 2.234 |
| Data Required Time | 40.029 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/mem_mem_0_0_s |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.520 | 0.340 | tC2Q | RF | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 2.234 | 1.714 | tNET | FF | 8 | BSRAM_R10[2] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/mem_mem_0_0_s/RESETB |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | BSRAM_R10[2] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/mem_mem_0_0_s/CLKB |
| 40.029 | -0.152 | tSu | 1 | BSRAM_R10[2] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/mem_mem_0_0_s |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.714, 83.462%; tC2Q: 0.340, 16.538% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path2
Path Summary:
| Slack | 37.914 |
| Data Arrival Time | 2.234 |
| Data Required Time | 40.148 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_0_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.520 | 0.340 | tC2Q | RF | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 2.234 | 1.714 | tNET | FF | 1 | R11C3[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_0_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R11C3[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_0_s1/CLK |
| 40.148 | -0.032 | tSu | 1 | R11C3[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_0_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.714, 83.462%; tC2Q: 0.340, 16.538% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path3
Path Summary:
| Slack | 37.914 |
| Data Arrival Time | 2.234 |
| Data Required Time | 40.148 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_1_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.520 | 0.340 | tC2Q | RF | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 2.234 | 1.714 | tNET | FF | 1 | R11C3[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_1_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R11C3[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_1_s1/CLK |
| 40.148 | -0.032 | tSu | 1 | R11C3[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_1_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.714, 83.462%; tC2Q: 0.340, 16.538% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path4
Path Summary:
| Slack | 37.914 |
| Data Arrival Time | 2.234 |
| Data Required Time | 40.148 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.520 | 0.340 | tC2Q | RF | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 2.234 | 1.714 | tNET | FF | 1 | R11C3[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R11C3[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/CLK |
| 40.148 | -0.032 | tSu | 1 | R11C3[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.714, 83.462%; tC2Q: 0.340, 16.538% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path5
Path Summary:
| Slack | 37.914 |
| Data Arrival Time | 2.234 |
| Data Required Time | 40.148 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_3_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.520 | 0.340 | tC2Q | RF | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 2.234 | 1.714 | tNET | FF | 1 | R11C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_3_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R11C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_3_s1/CLK |
| 40.148 | -0.032 | tSu | 1 | R11C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_3_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.714, 83.462%; tC2Q: 0.340, 16.538% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path6
Path Summary:
| Slack | 37.914 |
| Data Arrival Time | 2.234 |
| Data Required Time | 40.148 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_4_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.520 | 0.340 | tC2Q | RF | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 2.234 | 1.714 | tNET | FF | 1 | R11C3[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_4_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R11C3[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_4_s1/CLK |
| 40.148 | -0.032 | tSu | 1 | R11C3[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_4_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.714, 83.462%; tC2Q: 0.340, 16.538% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path7
Path Summary:
| Slack | 37.914 |
| Data Arrival Time | 2.234 |
| Data Required Time | 40.148 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_5_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.520 | 0.340 | tC2Q | RF | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 2.234 | 1.714 | tNET | FF | 1 | R11C3[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_5_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R11C3[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_5_s1/CLK |
| 40.148 | -0.032 | tSu | 1 | R11C3[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_5_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.714, 83.462%; tC2Q: 0.340, 16.538% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path8
Path Summary:
| Slack | 37.914 |
| Data Arrival Time | 2.234 |
| Data Required Time | 40.148 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_6_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.520 | 0.340 | tC2Q | RF | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 2.234 | 1.714 | tNET | FF | 1 | R11C4[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_6_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R11C4[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_6_s1/CLK |
| 40.148 | -0.032 | tSu | 1 | R11C4[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_6_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.714, 83.462%; tC2Q: 0.340, 16.538% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path9
Path Summary:
| Slack | 37.914 |
| Data Arrival Time | 2.234 |
| Data Required Time | 40.148 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_7_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.520 | 0.340 | tC2Q | RF | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 2.234 | 1.714 | tNET | FF | 1 | R11C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_7_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R11C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_7_s1/CLK |
| 40.148 | -0.032 | tSu | 1 | R11C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_7_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.714, 83.462%; tC2Q: 0.340, 16.538% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path10
Path Summary:
| Slack | 37.914 |
| Data Arrival Time | 2.234 |
| Data Required Time | 40.148 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_8_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.520 | 0.340 | tC2Q | RF | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 2.234 | 1.714 | tNET | FF | 1 | R11C4[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_8_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R11C4[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_8_s1/CLK |
| 40.148 | -0.032 | tSu | 1 | R11C4[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_8_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.714, 83.462%; tC2Q: 0.340, 16.538% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path11
Path Summary:
| Slack | 37.914 |
| Data Arrival Time | 2.234 |
| Data Required Time | 40.148 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_9_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.520 | 0.340 | tC2Q | RF | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 2.234 | 1.714 | tNET | FF | 1 | R11C4[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_9_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R11C4[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_9_s1/CLK |
| 40.148 | -0.032 | tSu | 1 | R11C4[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_9_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.714, 83.462%; tC2Q: 0.340, 16.538% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path12
Path Summary:
| Slack | 37.914 |
| Data Arrival Time | 2.234 |
| Data Required Time | 40.148 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_10_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.520 | 0.340 | tC2Q | RF | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 2.234 | 1.714 | tNET | FF | 1 | R11C4[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_10_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R11C4[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_10_s1/CLK |
| 40.148 | -0.032 | tSu | 1 | R11C4[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_10_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.714, 83.462%; tC2Q: 0.340, 16.538% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path13
Path Summary:
| Slack | 37.914 |
| Data Arrival Time | 2.234 |
| Data Required Time | 40.148 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.520 | 0.340 | tC2Q | RF | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 2.234 | 1.714 | tNET | FF | 1 | R11C4[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R11C4[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1/CLK |
| 40.148 | -0.032 | tSu | 1 | R11C4[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.714, 83.462%; tC2Q: 0.340, 16.538% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path14
Path Summary:
| Slack | 37.914 |
| Data Arrival Time | 2.234 |
| Data Required Time | 40.148 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.520 | 0.340 | tC2Q | RF | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 2.234 | 1.714 | tNET | FF | 1 | R12C9[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0/PRESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R12C9[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0/CLK |
| 40.148 | -0.032 | tSu | 1 | R12C9[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.714, 83.462%; tC2Q: 0.340, 16.538% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path15
Path Summary:
| Slack | 37.914 |
| Data Arrival Time | 2.234 |
| Data Required Time | 40.148 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_0_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.520 | 0.340 | tC2Q | RF | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 2.234 | 1.714 | tNET | FF | 1 | R12C4[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R12C4[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_0_s0/CLK |
| 40.148 | -0.032 | tSu | 1 | R12C4[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_0_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.714, 83.462%; tC2Q: 0.340, 16.538% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path16
Path Summary:
| Slack | 37.914 |
| Data Arrival Time | 2.234 |
| Data Required Time | 40.148 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_1_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.520 | 0.340 | tC2Q | RF | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 2.234 | 1.714 | tNET | FF | 1 | R12C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R12C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_1_s0/CLK |
| 40.148 | -0.032 | tSu | 1 | R12C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.714, 83.462%; tC2Q: 0.340, 16.538% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path17
Path Summary:
| Slack | 37.914 |
| Data Arrival Time | 2.234 |
| Data Required Time | 40.148 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_2_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.520 | 0.340 | tC2Q | RF | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 2.234 | 1.714 | tNET | FF | 1 | R12C4[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_2_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R12C4[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_2_s0/CLK |
| 40.148 | -0.032 | tSu | 1 | R12C4[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_2_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.714, 83.462%; tC2Q: 0.340, 16.538% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path18
Path Summary:
| Slack | 37.914 |
| Data Arrival Time | 2.234 |
| Data Required Time | 40.148 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_3_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.520 | 0.340 | tC2Q | RF | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 2.234 | 1.714 | tNET | FF | 1 | R12C4[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_3_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R12C4[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_3_s0/CLK |
| 40.148 | -0.032 | tSu | 1 | R12C4[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_3_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.714, 83.462%; tC2Q: 0.340, 16.538% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path19
Path Summary:
| Slack | 37.914 |
| Data Arrival Time | 2.234 |
| Data Required Time | 40.148 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_4_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.520 | 0.340 | tC2Q | RF | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 2.234 | 1.714 | tNET | FF | 1 | R12C4[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_4_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R12C4[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_4_s0/CLK |
| 40.148 | -0.032 | tSu | 1 | R12C4[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_4_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.714, 83.462%; tC2Q: 0.340, 16.538% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path20
Path Summary:
| Slack | 37.914 |
| Data Arrival Time | 2.234 |
| Data Required Time | 40.148 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_5_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.520 | 0.340 | tC2Q | RF | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 2.234 | 1.714 | tNET | FF | 1 | R12C4[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_5_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R12C4[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_5_s0/CLK |
| 40.148 | -0.032 | tSu | 1 | R12C4[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_5_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.714, 83.462%; tC2Q: 0.340, 16.538% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path21
Path Summary:
| Slack | 37.914 |
| Data Arrival Time | 2.234 |
| Data Required Time | 40.148 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_6_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.520 | 0.340 | tC2Q | RF | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 2.234 | 1.714 | tNET | FF | 1 | R12C5[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_6_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R12C5[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_6_s0/CLK |
| 40.148 | -0.032 | tSu | 1 | R12C5[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_6_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.714, 83.462%; tC2Q: 0.340, 16.538% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path22
Path Summary:
| Slack | 37.914 |
| Data Arrival Time | 2.234 |
| Data Required Time | 40.148 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_7_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.520 | 0.340 | tC2Q | RF | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 2.234 | 1.714 | tNET | FF | 1 | R12C5[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_7_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R12C5[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_7_s0/CLK |
| 40.148 | -0.032 | tSu | 1 | R12C5[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_7_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.714, 83.462%; tC2Q: 0.340, 16.538% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path23
Path Summary:
| Slack | 37.914 |
| Data Arrival Time | 2.234 |
| Data Required Time | 40.148 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_8_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.520 | 0.340 | tC2Q | RF | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 2.234 | 1.714 | tNET | FF | 1 | R12C5[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_8_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R12C5[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_8_s0/CLK |
| 40.148 | -0.032 | tSu | 1 | R12C5[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_8_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.714, 83.462%; tC2Q: 0.340, 16.538% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path24
Path Summary:
| Slack | 37.914 |
| Data Arrival Time | 2.234 |
| Data Required Time | 40.148 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_9_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.520 | 0.340 | tC2Q | RF | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 2.234 | 1.714 | tNET | FF | 1 | R12C5[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_9_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R12C5[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_9_s0/CLK |
| 40.148 | -0.032 | tSu | 1 | R12C5[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_9_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.714, 83.462%; tC2Q: 0.340, 16.538% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path25
Path Summary:
| Slack | 37.914 |
| Data Arrival Time | 2.234 |
| Data Required Time | 40.148 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_10_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.180 | 0.180 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.520 | 0.340 | tC2Q | RF | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 2.234 | 1.714 | tNET | FF | 1 | R12C5[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_10_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 40.000 | 40.000 | active clock edge time | ||||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 40.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.180 | 0.180 | tNET | RR | 1 | R12C5[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_10_s0/CLK |
| 40.148 | -0.032 | tSu | 1 | R12C5[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_10_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 40.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.714, 83.462%; tC2Q: 0.340, 16.538% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 1.330 |
| Data Arrival Time | 1.476 |
| Data Required Time | 0.146 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/mem_mem_0_0_s |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.383 | 0.247 | tC2Q | RR | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 1.476 | 1.092 | tNET | RR | 8 | BSRAM_R10[2] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/mem_mem_0_0_s/RESETB |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | BSRAM_R10[2] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/mem_mem_0_0_s/CLKB |
| 0.146 | 0.009 | tHld | 1 | BSRAM_R10[2] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/mem_mem_0_0_s |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.092, 81.556%; tC2Q: 0.247, 18.444% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path2
Path Summary:
| Slack | 1.330 |
| Data Arrival Time | 1.476 |
| Data Required Time | 0.146 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_0_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.383 | 0.247 | tC2Q | RR | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 1.476 | 1.092 | tNET | RR | 1 | R11C3[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_0_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R11C3[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_0_s1/CLK |
| 0.146 | 0.009 | tHld | 1 | R11C3[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_0_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.092, 81.556%; tC2Q: 0.247, 18.444% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path3
Path Summary:
| Slack | 1.330 |
| Data Arrival Time | 1.476 |
| Data Required Time | 0.146 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_1_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.383 | 0.247 | tC2Q | RR | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 1.476 | 1.092 | tNET | RR | 1 | R11C3[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_1_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R11C3[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_1_s1/CLK |
| 0.146 | 0.009 | tHld | 1 | R11C3[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_1_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.092, 81.556%; tC2Q: 0.247, 18.444% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path4
Path Summary:
| Slack | 1.330 |
| Data Arrival Time | 1.476 |
| Data Required Time | 0.146 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.383 | 0.247 | tC2Q | RR | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 1.476 | 1.092 | tNET | RR | 1 | R11C3[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R11C3[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1/CLK |
| 0.146 | 0.009 | tHld | 1 | R11C3[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_2_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.092, 81.556%; tC2Q: 0.247, 18.444% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path5
Path Summary:
| Slack | 1.330 |
| Data Arrival Time | 1.476 |
| Data Required Time | 0.146 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_3_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.383 | 0.247 | tC2Q | RR | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 1.476 | 1.092 | tNET | RR | 1 | R11C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_3_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R11C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_3_s1/CLK |
| 0.146 | 0.009 | tHld | 1 | R11C3[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_3_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.092, 81.556%; tC2Q: 0.247, 18.444% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path6
Path Summary:
| Slack | 1.330 |
| Data Arrival Time | 1.476 |
| Data Required Time | 0.146 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_4_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.383 | 0.247 | tC2Q | RR | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 1.476 | 1.092 | tNET | RR | 1 | R11C3[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_4_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R11C3[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_4_s1/CLK |
| 0.146 | 0.009 | tHld | 1 | R11C3[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_4_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.092, 81.556%; tC2Q: 0.247, 18.444% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path7
Path Summary:
| Slack | 1.330 |
| Data Arrival Time | 1.476 |
| Data Required Time | 0.146 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_5_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.383 | 0.247 | tC2Q | RR | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 1.476 | 1.092 | tNET | RR | 1 | R11C3[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_5_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R11C3[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_5_s1/CLK |
| 0.146 | 0.009 | tHld | 1 | R11C3[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_5_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.092, 81.556%; tC2Q: 0.247, 18.444% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path8
Path Summary:
| Slack | 1.330 |
| Data Arrival Time | 1.476 |
| Data Required Time | 0.146 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_6_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.383 | 0.247 | tC2Q | RR | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 1.476 | 1.092 | tNET | RR | 1 | R11C4[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_6_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R11C4[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_6_s1/CLK |
| 0.146 | 0.009 | tHld | 1 | R11C4[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_6_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.092, 81.556%; tC2Q: 0.247, 18.444% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path9
Path Summary:
| Slack | 1.330 |
| Data Arrival Time | 1.476 |
| Data Required Time | 0.146 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_7_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.383 | 0.247 | tC2Q | RR | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 1.476 | 1.092 | tNET | RR | 1 | R11C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_7_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R11C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_7_s1/CLK |
| 0.146 | 0.009 | tHld | 1 | R11C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_7_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.092, 81.556%; tC2Q: 0.247, 18.444% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path10
Path Summary:
| Slack | 1.330 |
| Data Arrival Time | 1.476 |
| Data Required Time | 0.146 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_8_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.383 | 0.247 | tC2Q | RR | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 1.476 | 1.092 | tNET | RR | 1 | R11C4[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_8_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R11C4[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_8_s1/CLK |
| 0.146 | 0.009 | tHld | 1 | R11C4[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_8_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.092, 81.556%; tC2Q: 0.247, 18.444% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path11
Path Summary:
| Slack | 1.330 |
| Data Arrival Time | 1.476 |
| Data Required Time | 0.146 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_9_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.383 | 0.247 | tC2Q | RR | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 1.476 | 1.092 | tNET | RR | 1 | R11C4[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_9_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R11C4[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_9_s1/CLK |
| 0.146 | 0.009 | tHld | 1 | R11C4[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_9_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.092, 81.556%; tC2Q: 0.247, 18.444% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path12
Path Summary:
| Slack | 1.330 |
| Data Arrival Time | 1.476 |
| Data Required Time | 0.146 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_10_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.383 | 0.247 | tC2Q | RR | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 1.476 | 1.092 | tNET | RR | 1 | R11C4[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_10_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R11C4[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_10_s1/CLK |
| 0.146 | 0.009 | tHld | 1 | R11C4[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_10_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.092, 81.556%; tC2Q: 0.247, 18.444% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path13
Path Summary:
| Slack | 1.330 |
| Data Arrival Time | 1.476 |
| Data Required Time | 0.146 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.383 | 0.247 | tC2Q | RR | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 1.476 | 1.092 | tNET | RR | 1 | R11C4[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R11C4[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1/CLK |
| 0.146 | 0.009 | tHld | 1 | R11C4[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Wnum_11_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.092, 81.556%; tC2Q: 0.247, 18.444% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path14
Path Summary:
| Slack | 1.330 |
| Data Arrival Time | 1.476 |
| Data Required Time | 0.146 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.383 | 0.247 | tC2Q | RR | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 1.476 | 1.092 | tNET | RR | 1 | R12C9[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0/PRESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R12C9[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0/CLK |
| 0.146 | 0.009 | tHld | 1 | R12C9[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/Empty_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.092, 81.556%; tC2Q: 0.247, 18.444% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path15
Path Summary:
| Slack | 1.330 |
| Data Arrival Time | 1.476 |
| Data Required Time | 0.146 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_0_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.383 | 0.247 | tC2Q | RR | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 1.476 | 1.092 | tNET | RR | 1 | R12C4[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_0_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R12C4[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_0_s0/CLK |
| 0.146 | 0.009 | tHld | 1 | R12C4[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_0_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.092, 81.556%; tC2Q: 0.247, 18.444% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path16
Path Summary:
| Slack | 1.330 |
| Data Arrival Time | 1.476 |
| Data Required Time | 0.146 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_1_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.383 | 0.247 | tC2Q | RR | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 1.476 | 1.092 | tNET | RR | 1 | R12C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_1_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R12C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_1_s0/CLK |
| 0.146 | 0.009 | tHld | 1 | R12C4[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.092, 81.556%; tC2Q: 0.247, 18.444% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path17
Path Summary:
| Slack | 1.330 |
| Data Arrival Time | 1.476 |
| Data Required Time | 0.146 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_2_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.383 | 0.247 | tC2Q | RR | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 1.476 | 1.092 | tNET | RR | 1 | R12C4[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_2_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R12C4[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_2_s0/CLK |
| 0.146 | 0.009 | tHld | 1 | R12C4[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_2_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.092, 81.556%; tC2Q: 0.247, 18.444% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path18
Path Summary:
| Slack | 1.330 |
| Data Arrival Time | 1.476 |
| Data Required Time | 0.146 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_3_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.383 | 0.247 | tC2Q | RR | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 1.476 | 1.092 | tNET | RR | 1 | R12C4[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_3_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R12C4[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_3_s0/CLK |
| 0.146 | 0.009 | tHld | 1 | R12C4[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_3_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.092, 81.556%; tC2Q: 0.247, 18.444% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path19
Path Summary:
| Slack | 1.330 |
| Data Arrival Time | 1.476 |
| Data Required Time | 0.146 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_4_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.383 | 0.247 | tC2Q | RR | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 1.476 | 1.092 | tNET | RR | 1 | R12C4[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_4_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R12C4[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_4_s0/CLK |
| 0.146 | 0.009 | tHld | 1 | R12C4[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_4_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.092, 81.556%; tC2Q: 0.247, 18.444% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path20
Path Summary:
| Slack | 1.330 |
| Data Arrival Time | 1.476 |
| Data Required Time | 0.146 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_5_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.383 | 0.247 | tC2Q | RR | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 1.476 | 1.092 | tNET | RR | 1 | R12C4[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_5_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R12C4[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_5_s0/CLK |
| 0.146 | 0.009 | tHld | 1 | R12C4[2][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_5_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.092, 81.556%; tC2Q: 0.247, 18.444% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path21
Path Summary:
| Slack | 1.330 |
| Data Arrival Time | 1.476 |
| Data Required Time | 0.146 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_6_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.383 | 0.247 | tC2Q | RR | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 1.476 | 1.092 | tNET | RR | 1 | R12C5[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_6_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R12C5[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_6_s0/CLK |
| 0.146 | 0.009 | tHld | 1 | R12C5[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_6_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.092, 81.556%; tC2Q: 0.247, 18.444% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path22
Path Summary:
| Slack | 1.330 |
| Data Arrival Time | 1.476 |
| Data Required Time | 0.146 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_7_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.383 | 0.247 | tC2Q | RR | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 1.476 | 1.092 | tNET | RR | 1 | R12C5[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_7_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R12C5[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_7_s0/CLK |
| 0.146 | 0.009 | tHld | 1 | R12C5[0][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_7_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.092, 81.556%; tC2Q: 0.247, 18.444% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path23
Path Summary:
| Slack | 1.330 |
| Data Arrival Time | 1.476 |
| Data Required Time | 0.146 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_8_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.383 | 0.247 | tC2Q | RR | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 1.476 | 1.092 | tNET | RR | 1 | R12C5[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_8_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R12C5[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_8_s0/CLK |
| 0.146 | 0.009 | tHld | 1 | R12C5[1][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_8_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.092, 81.556%; tC2Q: 0.247, 18.444% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path24
Path Summary:
| Slack | 1.330 |
| Data Arrival Time | 1.476 |
| Data Required Time | 0.146 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_9_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.383 | 0.247 | tC2Q | RR | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 1.476 | 1.092 | tNET | RR | 1 | R12C5[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_9_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R12C5[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_9_s0/CLK |
| 0.146 | 0.009 | tHld | 1 | R12C5[1][B] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_9_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.092, 81.556%; tC2Q: 0.247, 18.444% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Path25
Path Summary:
| Slack | 1.330 |
| Data Arrival Time | 1.476 |
| Data Required Time | 0.146 |
| From | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0 |
| To | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_10_s0 |
| Launch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
| Latch Clk | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/CLK |
| 0.383 | 0.247 | tC2Q | RR | 202 | R17C15[0][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N_s0/Q |
| 1.476 | 1.092 | tNET | RR | 1 | R12C5[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_10_s0/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||||
| 0.000 | 0.000 | tCL | RR | 277 | R20C0 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 0.136 | 0.136 | tNET | RR | 1 | R12C5[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_10_s0/CLK |
| 0.146 | 0.009 | tHld | 1 | R12C5[2][A] | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_10_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.092, 81.556%; tC2Q: 0.247, 18.444% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.136, 100.000% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
| Slack: | 19.017 |
| Actual Width: | 19.943 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk |
| Objects: | led_cnt_30_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 20.000 | 0.000 | active clock edge time | ||
| 20.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||
| 20.000 | 0.000 | tCL | FF | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 20.193 | 0.193 | tNET | FF | led_cnt_30_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 40.000 | 0.000 | active clock edge time | ||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||
| 40.000 | 0.000 | tCL | RR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.136 | 0.136 | tNET | RR | led_cnt_30_s0/CLK |
MPW2
MPW Summary:
| Slack: | 19.017 |
| Actual Width: | 19.943 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk |
| Objects: | led_cnt_28_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 20.000 | 0.000 | active clock edge time | ||
| 20.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||
| 20.000 | 0.000 | tCL | FF | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 20.193 | 0.193 | tNET | FF | led_cnt_28_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 40.000 | 0.000 | active clock edge time | ||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||
| 40.000 | 0.000 | tCL | RR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.136 | 0.136 | tNET | RR | led_cnt_28_s0/CLK |
MPW3
MPW Summary:
| Slack: | 19.017 |
| Actual Width: | 19.943 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk |
| Objects: | led_cnt_24_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 20.000 | 0.000 | active clock edge time | ||
| 20.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||
| 20.000 | 0.000 | tCL | FF | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 20.193 | 0.193 | tNET | FF | led_cnt_24_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 40.000 | 0.000 | active clock edge time | ||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||
| 40.000 | 0.000 | tCL | RR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.136 | 0.136 | tNET | RR | led_cnt_24_s0/CLK |
MPW4
MPW Summary:
| Slack: | 19.017 |
| Actual Width: | 19.943 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk |
| Objects: | led_cnt_16_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 20.000 | 0.000 | active clock edge time | ||
| 20.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||
| 20.000 | 0.000 | tCL | FF | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 20.193 | 0.193 | tNET | FF | led_cnt_16_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 40.000 | 0.000 | active clock edge time | ||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||
| 40.000 | 0.000 | tCL | RR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.136 | 0.136 | tNET | RR | led_cnt_16_s0/CLK |
MPW5
MPW Summary:
| Slack: | 19.017 |
| Actual Width: | 19.943 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk |
| Objects: | led_cnt_0_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 20.000 | 0.000 | active clock edge time | ||
| 20.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||
| 20.000 | 0.000 | tCL | FF | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 20.193 | 0.193 | tNET | FF | led_cnt_0_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 40.000 | 0.000 | active clock edge time | ||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||
| 40.000 | 0.000 | tCL | RR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.136 | 0.136 | tNET | RR | led_cnt_0_s0/CLK |
MPW6
MPW Summary:
| Slack: | 19.017 |
| Actual Width: | 19.943 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk |
| Objects: | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_3_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 20.000 | 0.000 | active clock edge time | ||
| 20.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||
| 20.000 | 0.000 | tCL | FF | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 20.193 | 0.193 | tNET | FF | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_3_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 40.000 | 0.000 | active clock edge time | ||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||
| 40.000 | 0.000 | tCL | RR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.136 | 0.136 | tNET | RR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/bit_counter_3_s0/CLK |
MPW7
MPW Summary:
| Slack: | 19.017 |
| Actual Width: | 19.943 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk |
| Objects: | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_7_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 20.000 | 0.000 | active clock edge time | ||
| 20.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||
| 20.000 | 0.000 | tCL | FF | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 20.193 | 0.193 | tNET | FF | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_7_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 40.000 | 0.000 | active clock edge time | ||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||
| 40.000 | 0.000 | tCL | RR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.136 | 0.136 | tNET | RR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_7_s0/CLK |
MPW8
MPW Summary:
| Slack: | 19.017 |
| Actual Width: | 19.943 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk |
| Objects: | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_6_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 20.000 | 0.000 | active clock edge time | ||
| 20.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||
| 20.000 | 0.000 | tCL | FF | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 20.193 | 0.193 | tNET | FF | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_6_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 40.000 | 0.000 | active clock edge time | ||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||
| 40.000 | 0.000 | tCL | RR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.136 | 0.136 | tNET | RR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_6_s0/CLK |
MPW9
MPW Summary:
| Slack: | 19.017 |
| Actual Width: | 19.943 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk |
| Objects: | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_7_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 20.000 | 0.000 | active clock edge time | ||
| 20.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||
| 20.000 | 0.000 | tCL | FF | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 20.193 | 0.193 | tNET | FF | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_7_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 40.000 | 0.000 | active clock edge time | ||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||
| 40.000 | 0.000 | tCL | RR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.136 | 0.136 | tNET | RR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/u1/fifo_sc_hs_inst/wbin_7_s0/CLK |
MPW10
MPW Summary:
| Slack: | 19.017 |
| Actual Width: | 19.943 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk |
| Objects: | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_8_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 20.000 | 0.000 | active clock edge time | ||
| 20.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||
| 20.000 | 0.000 | tCL | FF | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 20.193 | 0.193 | tNET | FF | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_8_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 40.000 | 0.000 | active clock edge time | ||
| 40.000 | 0.000 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT.default_clk | ||
| 40.000 | 0.000 | tCL | RR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U1/osc_inst/OSCOUT |
| 40.136 | 0.136 | tNET | RR | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/checksum_8_s0/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
| FANOUT | NET NAME | WORST SLACK | MAX DELAY |
|---|---|---|---|
| 277 | GW_OSC_CLK_d | 30.551 | 0.489 |
| 202 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/RST_N | 34.084 | 2.073 |
| 34 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/User_model_state[1] | 33.645 | 2.079 |
| 28 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/full | 30.551 | 3.023 |
| 23 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U3/tdo_bit_cnt[3] | 35.446 | 1.284 |
| 23 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/cstate[2] | 32.992 | 1.600 |
| 23 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/wren_Z | 34.362 | 2.074 |
| 22 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/n1474_4 | 33.308 | 1.255 |
| 22 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/cstate[0] | 32.788 | 1.349 |
| 22 | u_GW_BACKGROUND_I2C/u_GW_BACKGROUND_I2C_0/U2/cstate[1] | 32.622 | 1.728 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
| GRID LOC | ROUTE CONGESTIONS |
|---|---|
| R2C2 | 100.00% |
| R2C7 | 100.00% |
| R2C9 | 100.00% |
| R2C10 | 100.00% |
| R3C8 | 100.00% |
| R5C4 | 100.00% |
| R8C13 | 100.00% |
| R8C12 | 100.00% |
| R5C3 | 100.00% |
| R8C11 | 100.00% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
| SDC Command Type | State | Detail Command |
|---|