Timing Messages

Report Title	Timing Analysis Report
Design File	E:\myWork\IP\releaseVerify\RefDesign\MultMedia\zipFile\1.9.9beta-3\Gowin_Equalizer_RefDesign\proj\impl\gwsynthesis\Equalizer.vg
Physical Constraints File	E:\myWork\IP\releaseVerify\RefDesign\MultMedia\zipFile\1.9.9beta-3\Gowin_Equalizer_RefDesign\proj\src\Equalizer.cst
Timing Constraint File	E:\myWork\IP\releaseVerify\RefDesign\MultMedia\zipFile\1.9.9beta-3\Gowin_Equalizer_RefDesign\proj\src\Equalizer.sdc
Version	V1.9.9 Beta-3
Part Number	GW2A-LV55PG484C8/I7
Device	GW2A-55
Device Version	C
Created Time	Mon Aug 21 15:11:45 2023
Legal Announcement	Copyright (C)2014-2023 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.95V 85C C8/I7
Hold Delay Model	Fast 1.05V 0C C8/I7
Numbers of Paths Analyzed	11292
Numbers of Endpoints Analyzed	11579
Numbers of Falling Endpoints	3
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
clk	Base	20.000	50.000	0.000	10.000			clk
tck_pad_i	Base	50.000	20.000	0.000	25.000			tck_pad_i

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk	50.000(MHz)	60.543(MHz)	5	TOP
2	tck_pad_i	20.000(MHz)	155.581(MHz)	5	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk	Setup	0.000	0
clk	Hold	0.000	0
tck_pad_i	Setup	0.000	0
tck_pad_i	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	3.483	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q	Equalizer_inst/Equalizer_inst_0/prod_x2_20_s0/D	clk:[R]	clk:[R]	20.000	0.000	16.482
2	3.483	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q	Equalizer_inst/Equalizer_inst_0/prod_x2_26_s0/D	clk:[R]	clk:[R]	20.000	0.000	16.482
3	3.561	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q	Equalizer_inst/Equalizer_inst_0/prod_x2_21_s0/D	clk:[R]	clk:[R]	20.000	0.000	16.404
4	3.577	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q	Equalizer_inst/Equalizer_inst_0/prod_x2_29_s0/D	clk:[R]	clk:[R]	20.000	0.000	16.388
5	3.582	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q	Equalizer_inst/Equalizer_inst_0/prod_x2_1_s0/D	clk:[R]	clk:[R]	20.000	0.000	16.383
6	3.591	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q	Equalizer_inst/Equalizer_inst_0/prod_x2_8_s0/D	clk:[R]	clk:[R]	20.000	0.000	16.374
7	3.668	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q	Equalizer_inst/Equalizer_inst_0/prod_x2_4_s0/D	clk:[R]	clk:[R]	20.000	0.000	16.297
8	3.669	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q	Equalizer_inst/Equalizer_inst_0/prod_x2_25_s0/D	clk:[R]	clk:[R]	20.000	0.000	16.296
9	3.743	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q	Equalizer_inst/Equalizer_inst_0/prod_x2_23_s0/D	clk:[R]	clk:[R]	20.000	0.000	16.222
10	3.748	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q	Equalizer_inst/Equalizer_inst_0/prod_x2_17_s0/D	clk:[R]	clk:[R]	20.000	0.000	16.217
11	3.759	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q	Equalizer_inst/Equalizer_inst_0/prod_x2_28_s0/D	clk:[R]	clk:[R]	20.000	0.000	16.206
12	3.760	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q	Equalizer_inst/Equalizer_inst_0/prod_x2_27_s0/D	clk:[R]	clk:[R]	20.000	0.000	16.205
13	3.764	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q	Equalizer_inst/Equalizer_inst_0/prod_x2_3_s0/D	clk:[R]	clk:[R]	20.000	0.000	16.201
14	3.764	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q	Equalizer_inst/Equalizer_inst_0/prod_x2_7_s0/D	clk:[R]	clk:[R]	20.000	0.000	16.201
15	3.819	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q	Equalizer_inst/Equalizer_inst_0/prod_1_2_s0/D	clk:[R]	clk:[R]	20.000	0.000	16.146
16	3.834	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q	Equalizer_inst/Equalizer_inst_0/prod_x2_10_s0/D	clk:[R]	clk:[R]	20.000	0.000	16.131
17	3.834	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q	Equalizer_inst/Equalizer_inst_0/prod_x2_34_s0/D	clk:[R]	clk:[R]	20.000	0.000	16.131
18	3.835	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q	Equalizer_inst/Equalizer_inst_0/prod_x2_5_s0/D	clk:[R]	clk:[R]	20.000	0.000	16.130
19	3.835	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q	Equalizer_inst/Equalizer_inst_0/prod_x2_9_s0/D	clk:[R]	clk:[R]	20.000	0.000	16.130
20	3.840	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q	Equalizer_inst/Equalizer_inst_0/prod_1_4_s0/D	clk:[R]	clk:[R]	20.000	0.000	16.125
21	3.896	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q	Equalizer_inst/Equalizer_inst_0/prod_1_0_s0/D	clk:[R]	clk:[R]	20.000	0.000	16.069
22	3.897	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q	Equalizer_inst/Equalizer_inst_0/prod_1_1_s0/D	clk:[R]	clk:[R]	20.000	0.000	16.068
23	3.897	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q	Equalizer_inst/Equalizer_inst_0/prod_1_5_s0/D	clk:[R]	clk:[R]	20.000	0.000	16.068
24	3.897	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q	Equalizer_inst/Equalizer_inst_0/prod_1_7_s0/D	clk:[R]	clk:[R]	20.000	0.000	16.068
25	3.910	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q	Equalizer_inst/Equalizer_inst_0/prod_x2_16_s0/D	clk:[R]	clk:[R]	20.000	0.000	16.055

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.074	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_4_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[4]	clk:[R]	clk:[R]	0.000	0.000	0.323
2	0.074	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_1_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[1]	clk:[R]	clk:[R]	0.000	0.000	0.323
3	0.198	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_46_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[14]	clk:[R]	clk:[R]	0.000	0.000	0.447
4	0.213	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_56_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[8]	clk:[R]	clk:[R]	0.000	0.000	0.462
5	0.213	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_31_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[15]	clk:[R]	clk:[R]	0.000	0.000	0.462
6	0.213	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_30_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[14]	clk:[R]	clk:[R]	0.000	0.000	0.462
7	0.213	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_29_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[13]	clk:[R]	clk:[R]	0.000	0.000	0.462
8	0.213	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_28_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[12]	clk:[R]	clk:[R]	0.000	0.000	0.462
9	0.213	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_27_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[11]	clk:[R]	clk:[R]	0.000	0.000	0.462
10	0.213	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[10]	clk:[R]	clk:[R]	0.000	0.000	0.462
11	0.213	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_25_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[9]	clk:[R]	clk:[R]	0.000	0.000	0.462
12	0.213	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[8]	clk:[R]	clk:[R]	0.000	0.000	0.462
13	0.213	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_23_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[7]	clk:[R]	clk:[R]	0.000	0.000	0.462
14	0.213	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_22_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[6]	clk:[R]	clk:[R]	0.000	0.000	0.462
15	0.225	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_42_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[10]	clk:[R]	clk:[R]	0.000	0.000	0.474
16	0.225	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[3]	clk:[R]	clk:[R]	0.000	0.000	0.474
17	0.225	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_13_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[13]	clk:[R]	clk:[R]	0.000	0.000	0.474
18	0.335	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_57_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[9]	clk:[R]	clk:[R]	0.000	0.000	0.584
19	0.335	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_51_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[3]	clk:[R]	clk:[R]	0.000	0.000	0.584
20	0.335	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_50_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[2]	clk:[R]	clk:[R]	0.000	0.000	0.584
21	0.335	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_43_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[11]	clk:[R]	clk:[R]	0.000	0.000	0.584
22	0.335	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_39_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[7]	clk:[R]	clk:[R]	0.000	0.000	0.584
23	0.335	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_36_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[4]	clk:[R]	clk:[R]	0.000	0.000	0.584
24	0.335	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_32_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[0]	clk:[R]	clk:[R]	0.000	0.000	0.584
25	0.351	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_38_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[6]	clk:[R]	clk:[R]	0.000	0.000	0.600

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	7.219	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.023	2.723
2	7.219	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.023	2.723
3	7.219	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.023	2.723
4	7.219	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.023	2.723
5	7.236	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET	clk:[F]	clk:[R]	10.000	0.023	2.706
6	7.462	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.023	2.480
7	7.462	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.023	2.480
8	7.462	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.023	2.480
9	7.462	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.023	2.480
10	7.468	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.023	2.474
11	7.468	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.023	2.474
12	7.710	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET	clk:[F]	clk:[R]	10.000	0.023	2.232
13	7.710	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.023	2.232
14	7.710	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.023	2.232
15	7.710	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.023	2.232
16	7.710	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.023	2.232
17	8.456	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.023	1.486
18	8.456	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.023	1.486
19	8.456	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.023	1.486
20	8.461	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.023	1.480
21	8.461	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.023	1.480
22	8.461	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.023	1.480
23	8.461	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0/CLEAR	clk:[F]	clk:[R]	10.000	0.023	1.480
24	8.461	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLEAR	clk:[F]	clk:[R]	10.000	0.023	1.480
25	8.467	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR	clk:[F]	clk:[R]	10.000	0.023	1.475

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	10.469	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR	clk:[F]	clk:[R]	-10.000	0.012	0.467
2	10.472	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR	clk:[F]	clk:[R]	-10.000	0.012	0.470
3	10.472	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR	clk:[F]	clk:[R]	-10.000	0.012	0.470
4	10.472	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR	clk:[F]	clk:[R]	-10.000	0.012	0.470
5	10.473	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.012	0.471
6	10.473	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.012	0.471
7	10.473	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.012	0.471
8	10.591	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR	clk:[F]	clk:[R]	-10.000	0.012	0.589
9	10.594	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR	clk:[F]	clk:[R]	-10.000	0.012	0.592
10	10.594	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR	clk:[F]	clk:[R]	-10.000	0.012	0.592
11	10.594	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR	clk:[F]	clk:[R]	-10.000	0.012	0.592
12	10.623	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR	clk:[F]	clk:[R]	-10.000	0.012	0.622
13	10.623	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR	clk:[F]	clk:[R]	-10.000	0.012	0.622
14	10.623	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR	clk:[F]	clk:[R]	-10.000	0.012	0.622
15	10.626	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.012	0.625
16	10.626	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.012	0.625
17	10.742	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.012	0.741
18	10.754	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR	clk:[F]	clk:[R]	-10.000	0.012	0.753
19	10.754	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.012	0.753
20	10.754	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.012	0.753
21	10.754	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_s0/CLEAR	clk:[F]	clk:[R]	-10.000	0.012	0.753
22	10.919	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.012	0.917
23	10.922	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.012	0.920
24	10.922	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.012	0.920
25	10.922	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR	clk:[F]	clk:[R]	-10.000	0.012	0.920

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	8.911	9.911	1.000	Low Pulse Width	clk	cnt_2_s0
2	8.911	9.911	1.000	Low Pulse Width	clk	gainwe_s2
3	8.911	9.911	1.000	Low Pulse Width	clk	cnt_cycle_2_s0
4	8.911	9.911	1.000	Low Pulse Width	clk	i_data_0_s1
5	8.911	9.911	1.000	Low Pulse Width	clk	addr_4_s1
6	8.911	9.911	1.000	Low Pulse Width	clk	Equalizer_inst/Equalizer_inst_0/gain_addr_1_s0
7	8.911	9.911	1.000	Low Pulse Width	clk	Equalizer_inst/Equalizer_inst_0/coeff_a1_reg[2]_4_s0
8	8.911	9.911	1.000	Low Pulse Width	clk	Equalizer_inst/Equalizer_inst_0/coeff_a1_reg[9]_16_s0
9	8.911	9.911	1.000	Low Pulse Width	clk	Equalizer_inst/Equalizer_inst_0/coeff_a2_reg[5]_0_s0
10	8.911	9.911	1.000	Low Pulse Width	clk	Equalizer_inst/Equalizer_inst_0/coeff_b1_reg[15]_8_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	3.483
Data Arrival Time	17.408
Data Required Time	20.891
From	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0
To	Equalizer_inst/Equalizer_inst_0/prod_x2_20_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/CLK
1.158	0.232	tC2Q	RF	1607	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q
8.174	7.017	tNET	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s52/I2
8.627	0.453	tINS	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s52/F
8.627	0.000	tNET	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s48/I0
8.730	0.103	tINS	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s48/O
8.730	0.000	tNET	FF	1	R31C71[2][B]	Equalizer_inst/Equalizer_inst_0/n12785_s46/I0
8.833	0.103	tINS	FF	1	R31C71[2][B]	Equalizer_inst/Equalizer_inst_0/n12785_s46/O
8.833	0.000	tNET	FF	1	R31C71[1][B]	Equalizer_inst/Equalizer_inst_0/n12785_s45/I0
8.936	0.103	tINS	FF	1	R31C71[1][B]	Equalizer_inst/Equalizer_inst_0/n12785_s45/O
11.880	2.944	tNET	FF	39	DSP_R19[1]	Equalizer_inst/Equalizer_inst_0/mult_12269_s1/A[3]
15.640	3.760	tINS	FF	1	DSP_R19[1]	Equalizer_inst/Equalizer_inst_0/mult_12269_s1/DOUT[20]
16.838	1.198	tNET	FF	1	R27C24[2][A]	Equalizer_inst/Equalizer_inst_0/n13288_s2/I1
17.408	0.570	tINS	FR	1	R27C24[2][A]	Equalizer_inst/Equalizer_inst_0/n13288_s2/F
17.408	0.000	tNET	RR	1	R27C24[2][A]	Equalizer_inst/Equalizer_inst_0/prod_x2_20_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R27C24[2][A]	Equalizer_inst/Equalizer_inst_0/prod_x2_20_s0/CLK
20.891	-0.035	tSu		1	R27C24[2][A]	Equalizer_inst/Equalizer_inst_0/prod_x2_20_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 5.092, 30.894%; route: 11.158, 67.698%; tC2Q: 0.232, 1.408%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path2

Path Summary:

Slack	3.483
Data Arrival Time	17.408
Data Required Time	20.891
From	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0
To	Equalizer_inst/Equalizer_inst_0/prod_x2_26_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/CLK
1.158	0.232	tC2Q	RF	1607	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q
8.174	7.017	tNET	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s52/I2
8.627	0.453	tINS	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s52/F
8.627	0.000	tNET	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s48/I0
8.730	0.103	tINS	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s48/O
8.730	0.000	tNET	FF	1	R31C71[2][B]	Equalizer_inst/Equalizer_inst_0/n12785_s46/I0
8.833	0.103	tINS	FF	1	R31C71[2][B]	Equalizer_inst/Equalizer_inst_0/n12785_s46/O
8.833	0.000	tNET	FF	1	R31C71[1][B]	Equalizer_inst/Equalizer_inst_0/n12785_s45/I0
8.936	0.103	tINS	FF	1	R31C71[1][B]	Equalizer_inst/Equalizer_inst_0/n12785_s45/O
11.880	2.944	tNET	FF	39	DSP_R19[1]	Equalizer_inst/Equalizer_inst_0/mult_12269_s1/A[3]
15.640	3.760	tINS	FF	1	DSP_R19[1]	Equalizer_inst/Equalizer_inst_0/mult_12269_s1/DOUT[26]
16.838	1.198	tNET	FF	1	R27C25[2][A]	Equalizer_inst/Equalizer_inst_0/n13282_s2/I1
17.408	0.570	tINS	FR	1	R27C25[2][A]	Equalizer_inst/Equalizer_inst_0/n13282_s2/F
17.408	0.000	tNET	RR	1	R27C25[2][A]	Equalizer_inst/Equalizer_inst_0/prod_x2_26_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R27C25[2][A]	Equalizer_inst/Equalizer_inst_0/prod_x2_26_s0/CLK
20.891	-0.035	tSu		1	R27C25[2][A]	Equalizer_inst/Equalizer_inst_0/prod_x2_26_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 5.092, 30.894%; route: 11.158, 67.698%; tC2Q: 0.232, 1.408%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path3

Path Summary:

Slack	3.561
Data Arrival Time	17.330
Data Required Time	20.891
From	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0
To	Equalizer_inst/Equalizer_inst_0/prod_x2_21_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/CLK
1.158	0.232	tC2Q	RF	1607	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q
8.174	7.017	tNET	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s52/I2
8.627	0.453	tINS	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s52/F
8.627	0.000	tNET	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s48/I0
8.730	0.103	tINS	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s48/O
8.730	0.000	tNET	FF	1	R31C71[2][B]	Equalizer_inst/Equalizer_inst_0/n12785_s46/I0
8.833	0.103	tINS	FF	1	R31C71[2][B]	Equalizer_inst/Equalizer_inst_0/n12785_s46/O
8.833	0.000	tNET	FF	1	R31C71[1][B]	Equalizer_inst/Equalizer_inst_0/n12785_s45/I0
8.936	0.103	tINS	FF	1	R31C71[1][B]	Equalizer_inst/Equalizer_inst_0/n12785_s45/O
11.880	2.944	tNET	FF	39	DSP_R19[1]	Equalizer_inst/Equalizer_inst_0/mult_12269_s1/A[3]
15.640	3.760	tINS	FF	1	DSP_R19[1]	Equalizer_inst/Equalizer_inst_0/mult_12269_s1/DOUT[21]
16.760	1.120	tNET	FF	1	R27C24[1][B]	Equalizer_inst/Equalizer_inst_0/n13287_s2/I1
17.330	0.570	tINS	FR	1	R27C24[1][B]	Equalizer_inst/Equalizer_inst_0/n13287_s2/F
17.330	0.000	tNET	RR	1	R27C24[1][B]	Equalizer_inst/Equalizer_inst_0/prod_x2_21_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R27C24[1][B]	Equalizer_inst/Equalizer_inst_0/prod_x2_21_s0/CLK
20.891	-0.035	tSu		1	R27C24[1][B]	Equalizer_inst/Equalizer_inst_0/prod_x2_21_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 5.092, 31.040%; route: 11.080, 67.545%; tC2Q: 0.232, 1.414%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path4

Path Summary:

Slack	3.577
Data Arrival Time	17.314
Data Required Time	20.891
From	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0
To	Equalizer_inst/Equalizer_inst_0/prod_x2_29_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/CLK
1.158	0.232	tC2Q	RF	1607	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q
8.174	7.017	tNET	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s52/I2
8.627	0.453	tINS	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s52/F
8.627	0.000	tNET	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s48/I0
8.730	0.103	tINS	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s48/O
8.730	0.000	tNET	FF	1	R31C71[2][B]	Equalizer_inst/Equalizer_inst_0/n12785_s46/I0
8.833	0.103	tINS	FF	1	R31C71[2][B]	Equalizer_inst/Equalizer_inst_0/n12785_s46/O
8.833	0.000	tNET	FF	1	R31C71[1][B]	Equalizer_inst/Equalizer_inst_0/n12785_s45/I0
8.936	0.103	tINS	FF	1	R31C71[1][B]	Equalizer_inst/Equalizer_inst_0/n12785_s45/O
11.880	2.944	tNET	FF	39	DSP_R19[1]	Equalizer_inst/Equalizer_inst_0/mult_12269_s1/A[3]
15.640	3.760	tINS	FF	1	DSP_R19[1]	Equalizer_inst/Equalizer_inst_0/mult_12269_s1/DOUT[29]
16.744	1.104	tNET	FF	1	R27C25[0][B]	Equalizer_inst/Equalizer_inst_0/n13279_s2/I1
17.314	0.570	tINS	FR	1	R27C25[0][B]	Equalizer_inst/Equalizer_inst_0/n13279_s2/F
17.314	0.000	tNET	RR	1	R27C25[0][B]	Equalizer_inst/Equalizer_inst_0/prod_x2_29_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R27C25[0][B]	Equalizer_inst/Equalizer_inst_0/prod_x2_29_s0/CLK
20.891	-0.035	tSu		1	R27C25[0][B]	Equalizer_inst/Equalizer_inst_0/prod_x2_29_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 5.092, 31.071%; route: 11.064, 67.513%; tC2Q: 0.232, 1.416%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path5

Path Summary:

Slack	3.582
Data Arrival Time	17.309
Data Required Time	20.891
From	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0
To	Equalizer_inst/Equalizer_inst_0/prod_x2_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/CLK
1.158	0.232	tC2Q	RF	1607	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q
8.174	7.017	tNET	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s52/I2
8.627	0.453	tINS	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s52/F
8.627	0.000	tNET	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s48/I0
8.730	0.103	tINS	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s48/O
8.730	0.000	tNET	FF	1	R31C71[2][B]	Equalizer_inst/Equalizer_inst_0/n12785_s46/I0
8.833	0.103	tINS	FF	1	R31C71[2][B]	Equalizer_inst/Equalizer_inst_0/n12785_s46/O
8.833	0.000	tNET	FF	1	R31C71[1][B]	Equalizer_inst/Equalizer_inst_0/n12785_s45/I0
8.936	0.103	tINS	FF	1	R31C71[1][B]	Equalizer_inst/Equalizer_inst_0/n12785_s45/O
11.880	2.944	tNET	FF	39	DSP_R19[1]	Equalizer_inst/Equalizer_inst_0/mult_12269_s1/A[3]
15.640	3.760	tINS	FF	1	DSP_R19[1]	Equalizer_inst/Equalizer_inst_0/mult_12269_s1/DOUT[1]
16.760	1.120	tNET	FF	1	R27C21[2][A]	Equalizer_inst/Equalizer_inst_0/n13307_s2/I1
17.309	0.549	tINS	FR	1	R27C21[2][A]	Equalizer_inst/Equalizer_inst_0/n13307_s2/F
17.309	0.000	tNET	RR	1	R27C21[2][A]	Equalizer_inst/Equalizer_inst_0/prod_x2_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R27C21[2][A]	Equalizer_inst/Equalizer_inst_0/prod_x2_1_s0/CLK
20.891	-0.035	tSu		1	R27C21[2][A]	Equalizer_inst/Equalizer_inst_0/prod_x2_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 5.071, 30.952%; route: 11.080, 67.632%; tC2Q: 0.232, 1.416%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path6

Path Summary:

Slack	3.591
Data Arrival Time	17.300
Data Required Time	20.891
From	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0
To	Equalizer_inst/Equalizer_inst_0/prod_x2_8_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/CLK
1.158	0.232	tC2Q	RF	1607	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q
8.174	7.017	tNET	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s52/I2
8.627	0.453	tINS	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s52/F
8.627	0.000	tNET	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s48/I0
8.730	0.103	tINS	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s48/O
8.730	0.000	tNET	FF	1	R31C71[2][B]	Equalizer_inst/Equalizer_inst_0/n12785_s46/I0
8.833	0.103	tINS	FF	1	R31C71[2][B]	Equalizer_inst/Equalizer_inst_0/n12785_s46/O
8.833	0.000	tNET	FF	1	R31C71[1][B]	Equalizer_inst/Equalizer_inst_0/n12785_s45/I0
8.936	0.103	tINS	FF	1	R31C71[1][B]	Equalizer_inst/Equalizer_inst_0/n12785_s45/O
11.880	2.944	tNET	FF	39	DSP_R19[1]	Equalizer_inst/Equalizer_inst_0/mult_12269_s1/A[3]
15.640	3.760	tINS	FF	1	DSP_R19[1]	Equalizer_inst/Equalizer_inst_0/mult_12269_s1/DOUT[8]
16.838	1.198	tNET	FF	1	R27C22[1][A]	Equalizer_inst/Equalizer_inst_0/n13300_s2/I1
17.300	0.462	tINS	FR	1	R27C22[1][A]	Equalizer_inst/Equalizer_inst_0/n13300_s2/F
17.300	0.000	tNET	RR	1	R27C22[1][A]	Equalizer_inst/Equalizer_inst_0/prod_x2_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R27C22[1][A]	Equalizer_inst/Equalizer_inst_0/prod_x2_8_s0/CLK
20.891	-0.035	tSu		1	R27C22[1][A]	Equalizer_inst/Equalizer_inst_0/prod_x2_8_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 4.984, 30.438%; route: 11.158, 68.145%; tC2Q: 0.232, 1.417%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path7

Path Summary:

Slack	3.668
Data Arrival Time	17.223
Data Required Time	20.891
From	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0
To	Equalizer_inst/Equalizer_inst_0/prod_x2_4_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/CLK
1.158	0.232	tC2Q	RF	1607	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q
8.174	7.017	tNET	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s52/I2
8.627	0.453	tINS	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s52/F
8.627	0.000	tNET	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s48/I0
8.730	0.103	tINS	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s48/O
8.730	0.000	tNET	FF	1	R31C71[2][B]	Equalizer_inst/Equalizer_inst_0/n12785_s46/I0
8.833	0.103	tINS	FF	1	R31C71[2][B]	Equalizer_inst/Equalizer_inst_0/n12785_s46/O
8.833	0.000	tNET	FF	1	R31C71[1][B]	Equalizer_inst/Equalizer_inst_0/n12785_s45/I0
8.936	0.103	tINS	FF	1	R31C71[1][B]	Equalizer_inst/Equalizer_inst_0/n12785_s45/O
11.880	2.944	tNET	FF	39	DSP_R19[1]	Equalizer_inst/Equalizer_inst_0/mult_12269_s1/A[3]
15.640	3.760	tINS	FF	1	DSP_R19[1]	Equalizer_inst/Equalizer_inst_0/mult_12269_s1/DOUT[4]
16.761	1.121	tNET	FF	1	R27C21[0][B]	Equalizer_inst/Equalizer_inst_0/n13304_s2/I1
17.223	0.462	tINS	FR	1	R27C21[0][B]	Equalizer_inst/Equalizer_inst_0/n13304_s2/F
17.223	0.000	tNET	RR	1	R27C21[0][B]	Equalizer_inst/Equalizer_inst_0/prod_x2_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R27C21[0][B]	Equalizer_inst/Equalizer_inst_0/prod_x2_4_s0/CLK
20.891	-0.035	tSu		1	R27C21[0][B]	Equalizer_inst/Equalizer_inst_0/prod_x2_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 4.984, 30.581%; route: 11.081, 67.995%; tC2Q: 0.232, 1.424%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path8

Path Summary:

Slack	3.669
Data Arrival Time	17.222
Data Required Time	20.891
From	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0
To	Equalizer_inst/Equalizer_inst_0/prod_x2_25_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/CLK
1.158	0.232	tC2Q	RF	1607	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q
8.174	7.017	tNET	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s52/I2
8.627	0.453	tINS	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s52/F
8.627	0.000	tNET	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s48/I0
8.730	0.103	tINS	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s48/O
8.730	0.000	tNET	FF	1	R31C71[2][B]	Equalizer_inst/Equalizer_inst_0/n12785_s46/I0
8.833	0.103	tINS	FF	1	R31C71[2][B]	Equalizer_inst/Equalizer_inst_0/n12785_s46/O
8.833	0.000	tNET	FF	1	R31C71[1][B]	Equalizer_inst/Equalizer_inst_0/n12785_s45/I0
8.936	0.103	tINS	FF	1	R31C71[1][B]	Equalizer_inst/Equalizer_inst_0/n12785_s45/O
11.880	2.944	tNET	FF	39	DSP_R19[1]	Equalizer_inst/Equalizer_inst_0/mult_12269_s1/A[3]
15.640	3.760	tINS	FF	1	DSP_R19[1]	Equalizer_inst/Equalizer_inst_0/mult_12269_s1/DOUT[25]
16.760	1.120	tNET	FF	1	R27C25[2][B]	Equalizer_inst/Equalizer_inst_0/n13283_s2/I1
17.222	0.462	tINS	FR	1	R27C25[2][B]	Equalizer_inst/Equalizer_inst_0/n13283_s2/F
17.222	0.000	tNET	RR	1	R27C25[2][B]	Equalizer_inst/Equalizer_inst_0/prod_x2_25_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R27C25[2][B]	Equalizer_inst/Equalizer_inst_0/prod_x2_25_s0/CLK
20.891	-0.035	tSu		1	R27C25[2][B]	Equalizer_inst/Equalizer_inst_0/prod_x2_25_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 4.984, 30.583%; route: 11.080, 67.993%; tC2Q: 0.232, 1.424%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path9

Path Summary:

Slack	3.743
Data Arrival Time	17.148
Data Required Time	20.891
From	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0
To	Equalizer_inst/Equalizer_inst_0/prod_x2_23_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/CLK
1.158	0.232	tC2Q	RF	1607	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q
8.174	7.017	tNET	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s52/I2
8.627	0.453	tINS	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s52/F
8.627	0.000	tNET	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s48/I0
8.730	0.103	tINS	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s48/O
8.730	0.000	tNET	FF	1	R31C71[2][B]	Equalizer_inst/Equalizer_inst_0/n12785_s46/I0
8.833	0.103	tINS	FF	1	R31C71[2][B]	Equalizer_inst/Equalizer_inst_0/n12785_s46/O
8.833	0.000	tNET	FF	1	R31C71[1][B]	Equalizer_inst/Equalizer_inst_0/n12785_s45/I0
8.936	0.103	tINS	FF	1	R31C71[1][B]	Equalizer_inst/Equalizer_inst_0/n12785_s45/O
11.880	2.944	tNET	FF	39	DSP_R19[1]	Equalizer_inst/Equalizer_inst_0/mult_12269_s1/A[3]
15.640	3.760	tINS	FF	1	DSP_R19[1]	Equalizer_inst/Equalizer_inst_0/mult_12269_s1/DOUT[23]
16.578	0.938	tNET	FF	1	R27C24[0][B]	Equalizer_inst/Equalizer_inst_0/n13285_s2/I1
17.148	0.570	tINS	FR	1	R27C24[0][B]	Equalizer_inst/Equalizer_inst_0/n13285_s2/F
17.148	0.000	tNET	RR	1	R27C24[0][B]	Equalizer_inst/Equalizer_inst_0/prod_x2_23_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R27C24[0][B]	Equalizer_inst/Equalizer_inst_0/prod_x2_23_s0/CLK
20.891	-0.035	tSu		1	R27C24[0][B]	Equalizer_inst/Equalizer_inst_0/prod_x2_23_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 5.092, 31.389%; route: 10.898, 67.181%; tC2Q: 0.232, 1.430%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path10

Path Summary:

Slack	3.748
Data Arrival Time	17.143
Data Required Time	20.891
From	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0
To	Equalizer_inst/Equalizer_inst_0/prod_x2_17_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/CLK
1.158	0.232	tC2Q	RF	1607	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q
8.174	7.017	tNET	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s52/I2
8.627	0.453	tINS	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s52/F
8.627	0.000	tNET	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s48/I0
8.730	0.103	tINS	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s48/O
8.730	0.000	tNET	FF	1	R31C71[2][B]	Equalizer_inst/Equalizer_inst_0/n12785_s46/I0
8.833	0.103	tINS	FF	1	R31C71[2][B]	Equalizer_inst/Equalizer_inst_0/n12785_s46/O
8.833	0.000	tNET	FF	1	R31C71[1][B]	Equalizer_inst/Equalizer_inst_0/n12785_s45/I0
8.936	0.103	tINS	FF	1	R31C71[1][B]	Equalizer_inst/Equalizer_inst_0/n12785_s45/O
11.880	2.944	tNET	FF	39	DSP_R19[1]	Equalizer_inst/Equalizer_inst_0/mult_12269_s1/A[3]
15.640	3.760	tINS	FF	1	DSP_R19[1]	Equalizer_inst/Equalizer_inst_0/mult_12269_s1/DOUT[17]
16.594	0.954	tNET	FF	1	R27C23[2][B]	Equalizer_inst/Equalizer_inst_0/n13291_s2/I1
17.143	0.549	tINS	FR	1	R27C23[2][B]	Equalizer_inst/Equalizer_inst_0/n13291_s2/F
17.143	0.000	tNET	RR	1	R27C23[2][B]	Equalizer_inst/Equalizer_inst_0/prod_x2_17_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R27C23[2][B]	Equalizer_inst/Equalizer_inst_0/prod_x2_17_s0/CLK
20.891	-0.035	tSu		1	R27C23[2][B]	Equalizer_inst/Equalizer_inst_0/prod_x2_17_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 5.071, 31.269%; route: 10.914, 67.300%; tC2Q: 0.232, 1.431%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path11

Path Summary:

Slack	3.759
Data Arrival Time	17.132
Data Required Time	20.891
From	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0
To	Equalizer_inst/Equalizer_inst_0/prod_x2_28_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/CLK
1.158	0.232	tC2Q	RF	1607	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q
8.174	7.017	tNET	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s52/I2
8.627	0.453	tINS	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s52/F
8.627	0.000	tNET	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s48/I0
8.730	0.103	tINS	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s48/O
8.730	0.000	tNET	FF	1	R31C71[2][B]	Equalizer_inst/Equalizer_inst_0/n12785_s46/I0
8.833	0.103	tINS	FF	1	R31C71[2][B]	Equalizer_inst/Equalizer_inst_0/n12785_s46/O
8.833	0.000	tNET	FF	1	R31C71[1][B]	Equalizer_inst/Equalizer_inst_0/n12785_s45/I0
8.936	0.103	tINS	FF	1	R31C71[1][B]	Equalizer_inst/Equalizer_inst_0/n12785_s45/O
11.880	2.944	tNET	FF	39	DSP_R19[1]	Equalizer_inst/Equalizer_inst_0/mult_12269_s1/A[3]
15.640	3.760	tINS	FF	1	DSP_R19[1]	Equalizer_inst/Equalizer_inst_0/mult_12269_s1/DOUT[28]
16.761	1.121	tNET	FF	1	R27C25[1][A]	Equalizer_inst/Equalizer_inst_0/n13280_s2/I1
17.132	0.371	tINS	FF	1	R27C25[1][A]	Equalizer_inst/Equalizer_inst_0/n13280_s2/F
17.132	0.000	tNET	FF	1	R27C25[1][A]	Equalizer_inst/Equalizer_inst_0/prod_x2_28_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R27C25[1][A]	Equalizer_inst/Equalizer_inst_0/prod_x2_28_s0/CLK
20.891	-0.035	tSu		1	R27C25[1][A]	Equalizer_inst/Equalizer_inst_0/prod_x2_28_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 4.893, 30.192%; route: 11.081, 68.377%; tC2Q: 0.232, 1.432%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path12

Path Summary:

Slack	3.760
Data Arrival Time	17.131
Data Required Time	20.891
From	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0
To	Equalizer_inst/Equalizer_inst_0/prod_x2_27_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/CLK
1.158	0.232	tC2Q	RF	1607	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q
8.174	7.017	tNET	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s52/I2
8.627	0.453	tINS	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s52/F
8.627	0.000	tNET	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s48/I0
8.730	0.103	tINS	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s48/O
8.730	0.000	tNET	FF	1	R31C71[2][B]	Equalizer_inst/Equalizer_inst_0/n12785_s46/I0
8.833	0.103	tINS	FF	1	R31C71[2][B]	Equalizer_inst/Equalizer_inst_0/n12785_s46/O
8.833	0.000	tNET	FF	1	R31C71[1][B]	Equalizer_inst/Equalizer_inst_0/n12785_s45/I0
8.936	0.103	tINS	FF	1	R31C71[1][B]	Equalizer_inst/Equalizer_inst_0/n12785_s45/O
11.880	2.944	tNET	FF	39	DSP_R19[1]	Equalizer_inst/Equalizer_inst_0/mult_12269_s1/A[3]
15.640	3.760	tINS	FF	1	DSP_R19[1]	Equalizer_inst/Equalizer_inst_0/mult_12269_s1/DOUT[27]
16.760	1.120	tNET	FF	1	R27C25[1][B]	Equalizer_inst/Equalizer_inst_0/n13281_s2/I1
17.131	0.371	tINS	FF	1	R27C25[1][B]	Equalizer_inst/Equalizer_inst_0/n13281_s2/F
17.131	0.000	tNET	FF	1	R27C25[1][B]	Equalizer_inst/Equalizer_inst_0/prod_x2_27_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R27C25[1][B]	Equalizer_inst/Equalizer_inst_0/prod_x2_27_s0/CLK
20.891	-0.035	tSu		1	R27C25[1][B]	Equalizer_inst/Equalizer_inst_0/prod_x2_27_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 4.893, 30.194%; route: 11.080, 68.375%; tC2Q: 0.232, 1.432%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path13

Path Summary:

Slack	3.764
Data Arrival Time	17.127
Data Required Time	20.891
From	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0
To	Equalizer_inst/Equalizer_inst_0/prod_x2_3_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/CLK
1.158	0.232	tC2Q	RF	1607	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q
8.174	7.017	tNET	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s52/I2
8.627	0.453	tINS	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s52/F
8.627	0.000	tNET	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s48/I0
8.730	0.103	tINS	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s48/O
8.730	0.000	tNET	FF	1	R31C71[2][B]	Equalizer_inst/Equalizer_inst_0/n12785_s46/I0
8.833	0.103	tINS	FF	1	R31C71[2][B]	Equalizer_inst/Equalizer_inst_0/n12785_s46/O
8.833	0.000	tNET	FF	1	R31C71[1][B]	Equalizer_inst/Equalizer_inst_0/n12785_s45/I0
8.936	0.103	tINS	FF	1	R31C71[1][B]	Equalizer_inst/Equalizer_inst_0/n12785_s45/O
11.880	2.944	tNET	FF	39	DSP_R19[1]	Equalizer_inst/Equalizer_inst_0/mult_12269_s1/A[3]
15.640	3.760	tINS	FF	1	DSP_R19[1]	Equalizer_inst/Equalizer_inst_0/mult_12269_s1/DOUT[3]
16.578	0.938	tNET	FF	1	R27C21[1][A]	Equalizer_inst/Equalizer_inst_0/n13305_s2/I1
17.127	0.549	tINS	FR	1	R27C21[1][A]	Equalizer_inst/Equalizer_inst_0/n13305_s2/F
17.127	0.000	tNET	RR	1	R27C21[1][A]	Equalizer_inst/Equalizer_inst_0/prod_x2_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R27C21[1][A]	Equalizer_inst/Equalizer_inst_0/prod_x2_3_s0/CLK
20.891	-0.035	tSu		1	R27C21[1][A]	Equalizer_inst/Equalizer_inst_0/prod_x2_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 5.071, 31.300%; route: 10.898, 67.268%; tC2Q: 0.232, 1.432%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path14

Path Summary:

Slack	3.764
Data Arrival Time	17.127
Data Required Time	20.891
From	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0
To	Equalizer_inst/Equalizer_inst_0/prod_x2_7_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/CLK
1.158	0.232	tC2Q	RF	1607	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q
8.174	7.017	tNET	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s52/I2
8.627	0.453	tINS	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s52/F
8.627	0.000	tNET	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s48/I0
8.730	0.103	tINS	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s48/O
8.730	0.000	tNET	FF	1	R31C71[2][B]	Equalizer_inst/Equalizer_inst_0/n12785_s46/I0
8.833	0.103	tINS	FF	1	R31C71[2][B]	Equalizer_inst/Equalizer_inst_0/n12785_s46/O
8.833	0.000	tNET	FF	1	R31C71[1][B]	Equalizer_inst/Equalizer_inst_0/n12785_s45/I0
8.936	0.103	tINS	FF	1	R31C71[1][B]	Equalizer_inst/Equalizer_inst_0/n12785_s45/O
11.880	2.944	tNET	FF	39	DSP_R19[1]	Equalizer_inst/Equalizer_inst_0/mult_12269_s1/A[3]
15.640	3.760	tINS	FF	1	DSP_R19[1]	Equalizer_inst/Equalizer_inst_0/mult_12269_s1/DOUT[7]
16.578	0.938	tNET	FF	1	R27C22[1][B]	Equalizer_inst/Equalizer_inst_0/n13301_s2/I1
17.127	0.549	tINS	FR	1	R27C22[1][B]	Equalizer_inst/Equalizer_inst_0/n13301_s2/F
17.127	0.000	tNET	RR	1	R27C22[1][B]	Equalizer_inst/Equalizer_inst_0/prod_x2_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R27C22[1][B]	Equalizer_inst/Equalizer_inst_0/prod_x2_7_s0/CLK
20.891	-0.035	tSu		1	R27C22[1][B]	Equalizer_inst/Equalizer_inst_0/prod_x2_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 5.071, 31.300%; route: 10.898, 67.268%; tC2Q: 0.232, 1.432%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path15

Path Summary:

Slack	3.819
Data Arrival Time	17.071
Data Required Time	20.891
From	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0
To	Equalizer_inst/Equalizer_inst_0/prod_1_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/CLK
1.158	0.232	tC2Q	RF	1607	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q
7.066	5.908	tNET	FF	1	R25C70[0][A]	Equalizer_inst/Equalizer_inst_0/n12518_s58/I2
7.583	0.517	tINS	FF	1	R25C70[0][A]	Equalizer_inst/Equalizer_inst_0/n12518_s58/F
7.583	0.000	tNET	FF	1	R25C70[0][A]	Equalizer_inst/Equalizer_inst_0/n12518_s51/I0
7.686	0.103	tINS	FF	1	R25C70[0][A]	Equalizer_inst/Equalizer_inst_0/n12518_s51/O
7.686	0.000	tNET	FF	1	R25C70[0][B]	Equalizer_inst/Equalizer_inst_0/n12518_s47/I1
7.789	0.103	tINS	FF	1	R25C70[0][B]	Equalizer_inst/Equalizer_inst_0/n12518_s47/O
7.789	0.000	tNET	FF	1	R25C70[1][B]	Equalizer_inst/Equalizer_inst_0/n12518_s45/I1
7.892	0.103	tINS	FF	1	R25C70[1][B]	Equalizer_inst/Equalizer_inst_0/n12518_s45/O
11.030	3.138	tNET	FF	39	DSP_R19[0]	Equalizer_inst/Equalizer_inst_0/mult_12140_s2/A[1]
14.790	3.760	tINS	FF	1	DSP_R19[0]	Equalizer_inst/Equalizer_inst_0/mult_12140_s2/DOUT[2]
16.501	1.711	tNET	FF	1	R22C29[1][B]	Equalizer_inst/Equalizer_inst_0/n13189_s2/I1
17.071	0.570	tINS	FR	1	R22C29[1][B]	Equalizer_inst/Equalizer_inst_0/n13189_s2/F
17.071	0.000	tNET	RR	1	R22C29[1][B]	Equalizer_inst/Equalizer_inst_0/prod_1_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R22C29[1][B]	Equalizer_inst/Equalizer_inst_0/prod_1_2_s0/CLK
20.891	-0.035	tSu		1	R22C29[1][B]	Equalizer_inst/Equalizer_inst_0/prod_1_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 5.156, 31.934%; route: 10.758, 66.629%; tC2Q: 0.232, 1.437%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path16

Path Summary:

Slack	3.834
Data Arrival Time	17.057
Data Required Time	20.891
From	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0
To	Equalizer_inst/Equalizer_inst_0/prod_x2_10_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/CLK
1.158	0.232	tC2Q	RF	1607	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q
8.174	7.017	tNET	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s52/I2
8.627	0.453	tINS	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s52/F
8.627	0.000	tNET	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s48/I0
8.730	0.103	tINS	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s48/O
8.730	0.000	tNET	FF	1	R31C71[2][B]	Equalizer_inst/Equalizer_inst_0/n12785_s46/I0
8.833	0.103	tINS	FF	1	R31C71[2][B]	Equalizer_inst/Equalizer_inst_0/n12785_s46/O
8.833	0.000	tNET	FF	1	R31C71[1][B]	Equalizer_inst/Equalizer_inst_0/n12785_s45/I0
8.936	0.103	tINS	FF	1	R31C71[1][B]	Equalizer_inst/Equalizer_inst_0/n12785_s45/O
11.880	2.944	tNET	FF	39	DSP_R19[1]	Equalizer_inst/Equalizer_inst_0/mult_12269_s1/A[3]
15.640	3.760	tINS	FF	1	DSP_R19[1]	Equalizer_inst/Equalizer_inst_0/mult_12269_s1/DOUT[10]
16.595	0.955	tNET	FF	1	R27C22[0][A]	Equalizer_inst/Equalizer_inst_0/n13298_s2/I1
17.057	0.462	tINS	FR	1	R27C22[0][A]	Equalizer_inst/Equalizer_inst_0/n13298_s2/F
17.057	0.000	tNET	RR	1	R27C22[0][A]	Equalizer_inst/Equalizer_inst_0/prod_x2_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R27C22[0][A]	Equalizer_inst/Equalizer_inst_0/prod_x2_10_s0/CLK
20.891	-0.035	tSu		1	R27C22[0][A]	Equalizer_inst/Equalizer_inst_0/prod_x2_10_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 4.984, 30.896%; route: 10.915, 67.666%; tC2Q: 0.232, 1.438%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path17

Path Summary:

Slack	3.834
Data Arrival Time	17.057
Data Required Time	20.891
From	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0
To	Equalizer_inst/Equalizer_inst_0/prod_x2_34_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/CLK
1.158	0.232	tC2Q	RF	1607	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q
8.174	7.017	tNET	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s52/I2
8.627	0.453	tINS	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s52/F
8.627	0.000	tNET	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s48/I0
8.730	0.103	tINS	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s48/O
8.730	0.000	tNET	FF	1	R31C71[2][B]	Equalizer_inst/Equalizer_inst_0/n12785_s46/I0
8.833	0.103	tINS	FF	1	R31C71[2][B]	Equalizer_inst/Equalizer_inst_0/n12785_s46/O
8.833	0.000	tNET	FF	1	R31C71[1][B]	Equalizer_inst/Equalizer_inst_0/n12785_s45/I0
8.936	0.103	tINS	FF	1	R31C71[1][B]	Equalizer_inst/Equalizer_inst_0/n12785_s45/O
11.880	2.944	tNET	FF	39	DSP_R19[1]	Equalizer_inst/Equalizer_inst_0/mult_12269_s1/A[3]
15.640	3.760	tINS	FF	1	DSP_R19[1]	Equalizer_inst/Equalizer_inst_0/mult_12269_s1/DOUT[34]
16.595	0.955	tNET	FF	1	R28C24[1][A]	Equalizer_inst/Equalizer_inst_0/n13274_s2/I1
17.057	0.462	tINS	FR	1	R28C24[1][A]	Equalizer_inst/Equalizer_inst_0/n13274_s2/F
17.057	0.000	tNET	RR	1	R28C24[1][A]	Equalizer_inst/Equalizer_inst_0/prod_x2_34_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R28C24[1][A]	Equalizer_inst/Equalizer_inst_0/prod_x2_34_s0/CLK
20.891	-0.035	tSu		1	R28C24[1][A]	Equalizer_inst/Equalizer_inst_0/prod_x2_34_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 4.984, 30.896%; route: 10.915, 67.666%; tC2Q: 0.232, 1.438%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path18

Path Summary:

Slack	3.835
Data Arrival Time	17.056
Data Required Time	20.891
From	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0
To	Equalizer_inst/Equalizer_inst_0/prod_x2_5_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/CLK
1.158	0.232	tC2Q	RF	1607	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q
8.174	7.017	tNET	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s52/I2
8.627	0.453	tINS	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s52/F
8.627	0.000	tNET	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s48/I0
8.730	0.103	tINS	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s48/O
8.730	0.000	tNET	FF	1	R31C71[2][B]	Equalizer_inst/Equalizer_inst_0/n12785_s46/I0
8.833	0.103	tINS	FF	1	R31C71[2][B]	Equalizer_inst/Equalizer_inst_0/n12785_s46/O
8.833	0.000	tNET	FF	1	R31C71[1][B]	Equalizer_inst/Equalizer_inst_0/n12785_s45/I0
8.936	0.103	tINS	FF	1	R31C71[1][B]	Equalizer_inst/Equalizer_inst_0/n12785_s45/O
11.880	2.944	tNET	FF	39	DSP_R19[1]	Equalizer_inst/Equalizer_inst_0/mult_12269_s1/A[3]
15.640	3.760	tINS	FF	1	DSP_R19[1]	Equalizer_inst/Equalizer_inst_0/mult_12269_s1/DOUT[5]
16.594	0.954	tNET	FF	1	R27C21[0][A]	Equalizer_inst/Equalizer_inst_0/n13303_s2/I1
17.056	0.462	tINS	FR	1	R27C21[0][A]	Equalizer_inst/Equalizer_inst_0/n13303_s2/F
17.056	0.000	tNET	RR	1	R27C21[0][A]	Equalizer_inst/Equalizer_inst_0/prod_x2_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R27C21[0][A]	Equalizer_inst/Equalizer_inst_0/prod_x2_5_s0/CLK
20.891	-0.035	tSu		1	R27C21[0][A]	Equalizer_inst/Equalizer_inst_0/prod_x2_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 4.984, 30.898%; route: 10.914, 67.663%; tC2Q: 0.232, 1.438%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path19

Path Summary:

Slack	3.835
Data Arrival Time	17.056
Data Required Time	20.891
From	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0
To	Equalizer_inst/Equalizer_inst_0/prod_x2_9_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/CLK
1.158	0.232	tC2Q	RF	1607	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q
8.174	7.017	tNET	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s52/I2
8.627	0.453	tINS	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s52/F
8.627	0.000	tNET	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s48/I0
8.730	0.103	tINS	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s48/O
8.730	0.000	tNET	FF	1	R31C71[2][B]	Equalizer_inst/Equalizer_inst_0/n12785_s46/I0
8.833	0.103	tINS	FF	1	R31C71[2][B]	Equalizer_inst/Equalizer_inst_0/n12785_s46/O
8.833	0.000	tNET	FF	1	R31C71[1][B]	Equalizer_inst/Equalizer_inst_0/n12785_s45/I0
8.936	0.103	tINS	FF	1	R31C71[1][B]	Equalizer_inst/Equalizer_inst_0/n12785_s45/O
11.880	2.944	tNET	FF	39	DSP_R19[1]	Equalizer_inst/Equalizer_inst_0/mult_12269_s1/A[3]
15.640	3.760	tINS	FF	1	DSP_R19[1]	Equalizer_inst/Equalizer_inst_0/mult_12269_s1/DOUT[9]
16.594	0.954	tNET	FF	1	R27C22[0][B]	Equalizer_inst/Equalizer_inst_0/n13299_s2/I1
17.056	0.462	tINS	FR	1	R27C22[0][B]	Equalizer_inst/Equalizer_inst_0/n13299_s2/F
17.056	0.000	tNET	RR	1	R27C22[0][B]	Equalizer_inst/Equalizer_inst_0/prod_x2_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R27C22[0][B]	Equalizer_inst/Equalizer_inst_0/prod_x2_9_s0/CLK
20.891	-0.035	tSu		1	R27C22[0][B]	Equalizer_inst/Equalizer_inst_0/prod_x2_9_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 4.984, 30.898%; route: 10.914, 67.663%; tC2Q: 0.232, 1.438%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path20

Path Summary:

Slack	3.840
Data Arrival Time	17.050
Data Required Time	20.891
From	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0
To	Equalizer_inst/Equalizer_inst_0/prod_1_4_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/CLK
1.158	0.232	tC2Q	RF	1607	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q
7.066	5.908	tNET	FF	1	R25C70[0][A]	Equalizer_inst/Equalizer_inst_0/n12518_s58/I2
7.583	0.517	tINS	FF	1	R25C70[0][A]	Equalizer_inst/Equalizer_inst_0/n12518_s58/F
7.583	0.000	tNET	FF	1	R25C70[0][A]	Equalizer_inst/Equalizer_inst_0/n12518_s51/I0
7.686	0.103	tINS	FF	1	R25C70[0][A]	Equalizer_inst/Equalizer_inst_0/n12518_s51/O
7.686	0.000	tNET	FF	1	R25C70[0][B]	Equalizer_inst/Equalizer_inst_0/n12518_s47/I1
7.789	0.103	tINS	FF	1	R25C70[0][B]	Equalizer_inst/Equalizer_inst_0/n12518_s47/O
7.789	0.000	tNET	FF	1	R25C70[1][B]	Equalizer_inst/Equalizer_inst_0/n12518_s45/I1
7.892	0.103	tINS	FF	1	R25C70[1][B]	Equalizer_inst/Equalizer_inst_0/n12518_s45/O
11.030	3.138	tNET	FF	39	DSP_R19[0]	Equalizer_inst/Equalizer_inst_0/mult_12140_s2/A[1]
14.790	3.760	tINS	FF	1	DSP_R19[0]	Equalizer_inst/Equalizer_inst_0/mult_12140_s2/DOUT[4]
16.501	1.711	tNET	FF	1	R22C29[0][B]	Equalizer_inst/Equalizer_inst_0/n13187_s2/I1
17.050	0.549	tINS	FR	1	R22C29[0][B]	Equalizer_inst/Equalizer_inst_0/n13187_s2/F
17.050	0.000	tNET	RR	1	R22C29[0][B]	Equalizer_inst/Equalizer_inst_0/prod_1_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R22C29[0][B]	Equalizer_inst/Equalizer_inst_0/prod_1_4_s0/CLK
20.891	-0.035	tSu		1	R22C29[0][B]	Equalizer_inst/Equalizer_inst_0/prod_1_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 5.135, 31.846%; route: 10.758, 66.715%; tC2Q: 0.232, 1.439%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path21

Path Summary:

Slack	3.896
Data Arrival Time	16.995
Data Required Time	20.891
From	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0
To	Equalizer_inst/Equalizer_inst_0/prod_1_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/CLK
1.158	0.232	tC2Q	RF	1607	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q
7.066	5.908	tNET	FF	1	R25C70[0][A]	Equalizer_inst/Equalizer_inst_0/n12518_s58/I2
7.583	0.517	tINS	FF	1	R25C70[0][A]	Equalizer_inst/Equalizer_inst_0/n12518_s58/F
7.583	0.000	tNET	FF	1	R25C70[0][A]	Equalizer_inst/Equalizer_inst_0/n12518_s51/I0
7.686	0.103	tINS	FF	1	R25C70[0][A]	Equalizer_inst/Equalizer_inst_0/n12518_s51/O
7.686	0.000	tNET	FF	1	R25C70[0][B]	Equalizer_inst/Equalizer_inst_0/n12518_s47/I1
7.789	0.103	tINS	FF	1	R25C70[0][B]	Equalizer_inst/Equalizer_inst_0/n12518_s47/O
7.789	0.000	tNET	FF	1	R25C70[1][B]	Equalizer_inst/Equalizer_inst_0/n12518_s45/I1
7.892	0.103	tINS	FF	1	R25C70[1][B]	Equalizer_inst/Equalizer_inst_0/n12518_s45/O
11.030	3.138	tNET	FF	39	DSP_R19[0]	Equalizer_inst/Equalizer_inst_0/mult_12140_s2/A[1]
14.790	3.760	tINS	FF	1	DSP_R19[0]	Equalizer_inst/Equalizer_inst_0/mult_12140_s2/DOUT[0]
16.425	1.635	tNET	FF	1	R22C29[2][B]	Equalizer_inst/Equalizer_inst_0/n13191_s2/I1
16.995	0.570	tINS	FR	1	R22C29[2][B]	Equalizer_inst/Equalizer_inst_0/n13191_s2/F
16.995	0.000	tNET	RR	1	R22C29[2][B]	Equalizer_inst/Equalizer_inst_0/prod_1_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R22C29[2][B]	Equalizer_inst/Equalizer_inst_0/prod_1_0_s0/CLK
20.891	-0.035	tSu		1	R22C29[2][B]	Equalizer_inst/Equalizer_inst_0/prod_1_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 5.156, 32.087%; route: 10.681, 66.469%; tC2Q: 0.232, 1.444%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path22

Path Summary:

Slack	3.897
Data Arrival Time	16.994
Data Required Time	20.891
From	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0
To	Equalizer_inst/Equalizer_inst_0/prod_1_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/CLK
1.158	0.232	tC2Q	RF	1607	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q
7.066	5.908	tNET	FF	1	R25C70[0][A]	Equalizer_inst/Equalizer_inst_0/n12518_s58/I2
7.583	0.517	tINS	FF	1	R25C70[0][A]	Equalizer_inst/Equalizer_inst_0/n12518_s58/F
7.583	0.000	tNET	FF	1	R25C70[0][A]	Equalizer_inst/Equalizer_inst_0/n12518_s51/I0
7.686	0.103	tINS	FF	1	R25C70[0][A]	Equalizer_inst/Equalizer_inst_0/n12518_s51/O
7.686	0.000	tNET	FF	1	R25C70[0][B]	Equalizer_inst/Equalizer_inst_0/n12518_s47/I1
7.789	0.103	tINS	FF	1	R25C70[0][B]	Equalizer_inst/Equalizer_inst_0/n12518_s47/O
7.789	0.000	tNET	FF	1	R25C70[1][B]	Equalizer_inst/Equalizer_inst_0/n12518_s45/I1
7.892	0.103	tINS	FF	1	R25C70[1][B]	Equalizer_inst/Equalizer_inst_0/n12518_s45/O
11.030	3.138	tNET	FF	39	DSP_R19[0]	Equalizer_inst/Equalizer_inst_0/mult_12140_s2/A[1]
14.790	3.760	tINS	FF	1	DSP_R19[0]	Equalizer_inst/Equalizer_inst_0/mult_12140_s2/DOUT[1]
16.424	1.633	tNET	FF	1	R22C29[2][A]	Equalizer_inst/Equalizer_inst_0/n13190_s2/I1
16.994	0.570	tINS	FR	1	R22C29[2][A]	Equalizer_inst/Equalizer_inst_0/n13190_s2/F
16.994	0.000	tNET	RR	1	R22C29[2][A]	Equalizer_inst/Equalizer_inst_0/prod_1_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R22C29[2][A]	Equalizer_inst/Equalizer_inst_0/prod_1_1_s0/CLK
20.891	-0.035	tSu		1	R22C29[2][A]	Equalizer_inst/Equalizer_inst_0/prod_1_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 5.156, 32.089%; route: 10.680, 66.467%; tC2Q: 0.232, 1.444%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path23

Path Summary:

Slack	3.897
Data Arrival Time	16.994
Data Required Time	20.891
From	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0
To	Equalizer_inst/Equalizer_inst_0/prod_1_5_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/CLK
1.158	0.232	tC2Q	RF	1607	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q
7.066	5.908	tNET	FF	1	R25C70[0][A]	Equalizer_inst/Equalizer_inst_0/n12518_s58/I2
7.583	0.517	tINS	FF	1	R25C70[0][A]	Equalizer_inst/Equalizer_inst_0/n12518_s58/F
7.583	0.000	tNET	FF	1	R25C70[0][A]	Equalizer_inst/Equalizer_inst_0/n12518_s51/I0
7.686	0.103	tINS	FF	1	R25C70[0][A]	Equalizer_inst/Equalizer_inst_0/n12518_s51/O
7.686	0.000	tNET	FF	1	R25C70[0][B]	Equalizer_inst/Equalizer_inst_0/n12518_s47/I1
7.789	0.103	tINS	FF	1	R25C70[0][B]	Equalizer_inst/Equalizer_inst_0/n12518_s47/O
7.789	0.000	tNET	FF	1	R25C70[1][B]	Equalizer_inst/Equalizer_inst_0/n12518_s45/I1
7.892	0.103	tINS	FF	1	R25C70[1][B]	Equalizer_inst/Equalizer_inst_0/n12518_s45/O
11.030	3.138	tNET	FF	39	DSP_R19[0]	Equalizer_inst/Equalizer_inst_0/mult_12140_s2/A[1]
14.790	3.760	tINS	FF	1	DSP_R19[0]	Equalizer_inst/Equalizer_inst_0/mult_12140_s2/DOUT[5]
16.424	1.633	tNET	FF	1	R22C29[0][A]	Equalizer_inst/Equalizer_inst_0/n13186_s2/I1
16.994	0.570	tINS	FR	1	R22C29[0][A]	Equalizer_inst/Equalizer_inst_0/n13186_s2/F
16.994	0.000	tNET	RR	1	R22C29[0][A]	Equalizer_inst/Equalizer_inst_0/prod_1_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R22C29[0][A]	Equalizer_inst/Equalizer_inst_0/prod_1_5_s0/CLK
20.891	-0.035	tSu		1	R22C29[0][A]	Equalizer_inst/Equalizer_inst_0/prod_1_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 5.156, 32.089%; route: 10.680, 66.467%; tC2Q: 0.232, 1.444%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path24

Path Summary:

Slack	3.897
Data Arrival Time	16.994
Data Required Time	20.891
From	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0
To	Equalizer_inst/Equalizer_inst_0/prod_1_7_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/CLK
1.158	0.232	tC2Q	RF	1607	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q
7.066	5.908	tNET	FF	1	R25C70[0][A]	Equalizer_inst/Equalizer_inst_0/n12518_s58/I2
7.583	0.517	tINS	FF	1	R25C70[0][A]	Equalizer_inst/Equalizer_inst_0/n12518_s58/F
7.583	0.000	tNET	FF	1	R25C70[0][A]	Equalizer_inst/Equalizer_inst_0/n12518_s51/I0
7.686	0.103	tINS	FF	1	R25C70[0][A]	Equalizer_inst/Equalizer_inst_0/n12518_s51/O
7.686	0.000	tNET	FF	1	R25C70[0][B]	Equalizer_inst/Equalizer_inst_0/n12518_s47/I1
7.789	0.103	tINS	FF	1	R25C70[0][B]	Equalizer_inst/Equalizer_inst_0/n12518_s47/O
7.789	0.000	tNET	FF	1	R25C70[1][B]	Equalizer_inst/Equalizer_inst_0/n12518_s45/I1
7.892	0.103	tINS	FF	1	R25C70[1][B]	Equalizer_inst/Equalizer_inst_0/n12518_s45/O
11.030	3.138	tNET	FF	39	DSP_R19[0]	Equalizer_inst/Equalizer_inst_0/mult_12140_s2/A[1]
14.790	3.760	tINS	FF	1	DSP_R19[0]	Equalizer_inst/Equalizer_inst_0/mult_12140_s2/DOUT[7]
16.424	1.633	tNET	FF	1	R22C30[0][B]	Equalizer_inst/Equalizer_inst_0/n13184_s2/I1
16.994	0.570	tINS	FR	1	R22C30[0][B]	Equalizer_inst/Equalizer_inst_0/n13184_s2/F
16.994	0.000	tNET	RR	1	R22C30[0][B]	Equalizer_inst/Equalizer_inst_0/prod_1_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R22C30[0][B]	Equalizer_inst/Equalizer_inst_0/prod_1_7_s0/CLK
20.891	-0.035	tSu		1	R22C30[0][B]	Equalizer_inst/Equalizer_inst_0/prod_1_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 5.156, 32.089%; route: 10.680, 66.467%; tC2Q: 0.232, 1.444%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path25

Path Summary:

Slack	3.910
Data Arrival Time	16.981
Data Required Time	20.891
From	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0
To	Equalizer_inst/Equalizer_inst_0/prod_x2_16_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/CLK
1.158	0.232	tC2Q	RF	1607	R20C18[0][A]	Equalizer_inst/Equalizer_inst_0/cnt_band_0_s0/Q
8.174	7.017	tNET	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s52/I2
8.627	0.453	tINS	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s52/F
8.627	0.000	tNET	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s48/I0
8.730	0.103	tINS	FF	1	R31C71[3][A]	Equalizer_inst/Equalizer_inst_0/n12785_s48/O
8.730	0.000	tNET	FF	1	R31C71[2][B]	Equalizer_inst/Equalizer_inst_0/n12785_s46/I0
8.833	0.103	tINS	FF	1	R31C71[2][B]	Equalizer_inst/Equalizer_inst_0/n12785_s46/O
8.833	0.000	tNET	FF	1	R31C71[1][B]	Equalizer_inst/Equalizer_inst_0/n12785_s45/I0
8.936	0.103	tINS	FF	1	R31C71[1][B]	Equalizer_inst/Equalizer_inst_0/n12785_s45/O
11.880	2.944	tNET	FF	39	DSP_R19[1]	Equalizer_inst/Equalizer_inst_0/mult_12269_s1/A[3]
15.640	3.760	tINS	FF	1	DSP_R19[1]	Equalizer_inst/Equalizer_inst_0/mult_12269_s1/DOUT[16]
16.519	0.878	tNET	FF	1	R28C21[0][A]	Equalizer_inst/Equalizer_inst_0/n13292_s2/I1
16.981	0.462	tINS	FR	1	R28C21[0][A]	Equalizer_inst/Equalizer_inst_0/n13292_s2/F
16.981	0.000	tNET	RR	1	R28C21[0][A]	Equalizer_inst/Equalizer_inst_0/prod_x2_16_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R28C21[0][A]	Equalizer_inst/Equalizer_inst_0/prod_x2_16_s0/CLK
20.891	-0.035	tSu		1	R28C21[0][A]	Equalizer_inst/Equalizer_inst_0/prod_x2_16_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 4.984, 31.044%; route: 10.839, 67.511%; tC2Q: 0.232, 1.445%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.074
Data Arrival Time	1.183
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_4_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R11C71[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_4_s0/CLK
1.061	0.201	tC2Q	RF	1	R11C71[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_4_s0/Q
1.183	0.122	tNET	FF	1	BSRAM_R10[22]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[4]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[22]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.109	0.249	tHld		1	BSRAM_R10[22]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path2

Path Summary:

Slack	0.074
Data Arrival Time	1.183
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_1_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R11C71[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_1_s0/CLK
1.061	0.201	tC2Q	RF	1	R11C71[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_1_s0/Q
1.183	0.122	tNET	FF	1	BSRAM_R10[22]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[22]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.109	0.249	tHld		1	BSRAM_R10[22]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path3

Path Summary:

Slack	0.198
Data Arrival Time	1.307
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_46_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R14C78[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_46_s0/CLK
1.062	0.202	tC2Q	RR	1	R14C78[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_46_s0/Q
1.307	0.245	tNET	RR	1	BSRAM_R10[24]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[14]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[24]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.109	0.249	tHld		1	BSRAM_R10[24]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.245, 54.832%; tC2Q: 0.202, 45.168%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path4

Path Summary:

Slack	0.213
Data Arrival Time	1.322
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_56_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R11C78[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_56_s0/CLK
1.062	0.202	tC2Q	RR	1	R11C78[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_56_s0/Q
1.322	0.260	tNET	RR	1	BSRAM_R10[25]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[8]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[25]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA
1.109	0.249	tHld		1	BSRAM_R10[25]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path5

Path Summary:

Slack	0.213
Data Arrival Time	1.322
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_31_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R12C74[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_31_s0/CLK
1.062	0.202	tC2Q	RR	1	R12C74[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_31_s0/Q
1.322	0.260	tNET	RR	1	BSRAM_R10[23]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[15]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[23]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.109	0.249	tHld		1	BSRAM_R10[23]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path6

Path Summary:

Slack	0.213
Data Arrival Time	1.322
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_30_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R12C74[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_30_s0/CLK
1.062	0.202	tC2Q	RR	1	R12C74[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_30_s0/Q
1.322	0.260	tNET	RR	1	BSRAM_R10[23]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[14]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[23]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.109	0.249	tHld		1	BSRAM_R10[23]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path7

Path Summary:

Slack	0.213
Data Arrival Time	1.322
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_29_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R12C74[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_29_s0/CLK
1.062	0.202	tC2Q	RR	1	R12C74[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_29_s0/Q
1.322	0.260	tNET	RR	1	BSRAM_R10[23]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[13]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[23]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.109	0.249	tHld		1	BSRAM_R10[23]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path8

Path Summary:

Slack	0.213
Data Arrival Time	1.322
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_28_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R12C74[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_28_s0/CLK
1.062	0.202	tC2Q	RR	1	R12C74[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_28_s0/Q
1.322	0.260	tNET	RR	1	BSRAM_R10[23]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[12]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[23]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.109	0.249	tHld		1	BSRAM_R10[23]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path9

Path Summary:

Slack	0.213
Data Arrival Time	1.322
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_27_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R11C74[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_27_s0/CLK
1.062	0.202	tC2Q	RR	1	R11C74[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_27_s0/Q
1.322	0.260	tNET	RR	1	BSRAM_R10[23]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[11]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[23]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.109	0.249	tHld		1	BSRAM_R10[23]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path10

Path Summary:

Slack	0.213
Data Arrival Time	1.322
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R11C74[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0/CLK
1.062	0.202	tC2Q	RR	1	R11C74[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0/Q
1.322	0.260	tNET	RR	1	BSRAM_R10[23]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[10]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[23]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.109	0.249	tHld		1	BSRAM_R10[23]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path11

Path Summary:

Slack	0.213
Data Arrival Time	1.322
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_25_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R11C74[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_25_s0/CLK
1.062	0.202	tC2Q	RR	1	R11C74[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_25_s0/Q
1.322	0.260	tNET	RR	1	BSRAM_R10[23]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[9]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[23]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.109	0.249	tHld		1	BSRAM_R10[23]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path12

Path Summary:

Slack	0.213
Data Arrival Time	1.322
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R11C74[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0/CLK
1.062	0.202	tC2Q	RR	1	R11C74[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0/Q
1.322	0.260	tNET	RR	1	BSRAM_R10[23]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[8]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[23]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.109	0.249	tHld		1	BSRAM_R10[23]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path13

Path Summary:

Slack	0.213
Data Arrival Time	1.322
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_23_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R12C73[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_23_s0/CLK
1.062	0.202	tC2Q	RR	1	R12C73[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_23_s0/Q
1.322	0.260	tNET	RR	1	BSRAM_R10[23]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[7]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[23]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.109	0.249	tHld		1	BSRAM_R10[23]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path14

Path Summary:

Slack	0.213
Data Arrival Time	1.322
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_22_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R12C73[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_22_s0/CLK
1.062	0.202	tC2Q	RR	1	R12C73[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_22_s0/Q
1.322	0.260	tNET	RR	1	BSRAM_R10[23]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[6]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[23]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.109	0.249	tHld		1	BSRAM_R10[23]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path15

Path Summary:

Slack	0.225
Data Arrival Time	1.334
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_42_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R14C76[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_42_s0/CLK
1.062	0.202	tC2Q	RR	1	R14C76[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_42_s0/Q
1.334	0.272	tNET	RR	1	BSRAM_R10[24]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[10]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[24]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.109	0.249	tHld		1	BSRAM_R10[24]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path16

Path Summary:

Slack	0.225
Data Arrival Time	1.334
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R14C73[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0/CLK
1.062	0.202	tC2Q	RR	1	R14C73[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_19_s0/Q
1.334	0.272	tNET	RR	1	BSRAM_R10[23]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[23]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.109	0.249	tHld		1	BSRAM_R10[23]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path17

Path Summary:

Slack	0.225
Data Arrival Time	1.334
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_13_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R14C73[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_13_s0/CLK
1.062	0.202	tC2Q	RR	1	R14C73[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_13_s0/Q
1.334	0.272	tNET	RR	1	BSRAM_R10[22]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/DI[13]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[22]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
1.109	0.249	tHld		1	BSRAM_R10[22]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path18

Path Summary:

Slack	0.335
Data Arrival Time	1.444
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_57_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R11C78[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_57_s0/CLK
1.062	0.202	tC2Q	RR	1	R11C78[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_57_s0/Q
1.444	0.382	tNET	RR	1	BSRAM_R10[25]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[9]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[25]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA
1.109	0.249	tHld		1	BSRAM_R10[25]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.382, 65.434%; tC2Q: 0.202, 34.566%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path19

Path Summary:

Slack	0.335
Data Arrival Time	1.444
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_51_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R13C78[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_51_s0/CLK
1.062	0.202	tC2Q	RR	1	R13C78[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_51_s0/Q
1.444	0.382	tNET	RR	1	BSRAM_R10[25]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[25]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA
1.109	0.249	tHld		1	BSRAM_R10[25]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.382, 65.434%; tC2Q: 0.202, 34.566%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path20

Path Summary:

Slack	0.335
Data Arrival Time	1.444
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_50_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R13C79[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_50_s0/CLK
1.062	0.202	tC2Q	RR	1	R13C79[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_50_s0/Q
1.444	0.382	tNET	RR	1	BSRAM_R10[25]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[25]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA
1.109	0.249	tHld		1	BSRAM_R10[25]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.382, 65.434%; tC2Q: 0.202, 34.566%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path21

Path Summary:

Slack	0.335
Data Arrival Time	1.444
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_43_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R14C79[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_43_s0/CLK
1.062	0.202	tC2Q	RR	1	R14C79[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_43_s0/Q
1.444	0.382	tNET	RR	1	BSRAM_R10[24]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[11]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[24]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.109	0.249	tHld		1	BSRAM_R10[24]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.382, 65.434%; tC2Q: 0.202, 34.566%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path22

Path Summary:

Slack	0.335
Data Arrival Time	1.444
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_39_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R11C73[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_39_s0/CLK
1.062	0.202	tC2Q	RR	1	R11C73[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_39_s0/Q
1.444	0.382	tNET	RR	1	BSRAM_R10[24]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[7]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[24]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.109	0.249	tHld		1	BSRAM_R10[24]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.382, 65.434%; tC2Q: 0.202, 34.566%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path23

Path Summary:

Slack	0.335
Data Arrival Time	1.444
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_36_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R11C73[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_36_s0/CLK
1.062	0.202	tC2Q	RR	1	R11C73[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_36_s0/Q
1.444	0.382	tNET	RR	1	BSRAM_R10[24]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[4]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[24]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.109	0.249	tHld		1	BSRAM_R10[24]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.382, 65.434%; tC2Q: 0.202, 34.566%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path24

Path Summary:

Slack	0.335
Data Arrival Time	1.444
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_32_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R11C74[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_32_s0/CLK
1.062	0.202	tC2Q	RR	1	R11C74[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_32_s0/Q
1.444	0.382	tNET	RR	1	BSRAM_R10[24]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[24]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.109	0.249	tHld		1	BSRAM_R10[24]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.382, 65.434%; tC2Q: 0.202, 34.566%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path25

Path Summary:

Slack	0.351
Data Arrival Time	1.460
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_38_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R11C73[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_38_s0/CLK
1.062	0.202	tC2Q	RR	1	R11C73[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_38_s0/Q
1.460	0.398	tNET	RR	1	BSRAM_R10[24]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[6]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[24]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.109	0.249	tHld		1	BSRAM_R10[24]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.398, 66.358%; tC2Q: 0.202, 33.642%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	7.219
Data Arrival Time	13.672
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.688	0.688	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.949	0.261	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.181	0.232	tC2Q	FF	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.672	2.491	tNET	FF	1	R18C79[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R18C79[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
20.891	-0.035	tSu		1	R18C79[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.491, 91.479%; tC2Q: 0.232, 8.521%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path2

Path Summary:

Slack	7.219
Data Arrival Time	13.672
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.688	0.688	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.949	0.261	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.181	0.232	tC2Q	FF	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.672	2.491	tNET	FF	1	R17C79[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R17C79[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
20.891	-0.035	tSu		1	R17C79[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.491, 91.479%; tC2Q: 0.232, 8.521%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path3

Path Summary:

Slack	7.219
Data Arrival Time	13.672
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.688	0.688	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.949	0.261	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.181	0.232	tC2Q	FF	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.672	2.491	tNET	FF	1	R17C79[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R17C79[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
20.891	-0.035	tSu		1	R17C79[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.491, 91.479%; tC2Q: 0.232, 8.521%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path4

Path Summary:

Slack	7.219
Data Arrival Time	13.672
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.688	0.688	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.949	0.261	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.181	0.232	tC2Q	FF	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.672	2.491	tNET	FF	1	R17C79[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R17C79[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
20.891	-0.035	tSu		1	R17C79[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.491, 91.479%; tC2Q: 0.232, 8.521%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path5

Path Summary:

Slack	7.236
Data Arrival Time	13.654
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_end_dly_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.688	0.688	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.949	0.261	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.181	0.232	tC2Q	FF	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.654	2.474	tNET	FF	1	R14C76[2][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R14C76[2][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK
20.891	-0.035	tSu		1	R14C76[2][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.474, 91.425%; tC2Q: 0.232, 8.575%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path6

Path Summary:

Slack	7.462
Data Arrival Time	13.429
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.688	0.688	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.949	0.261	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.181	0.232	tC2Q	FF	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.429	2.248	tNET	FF	1	R18C78[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R18C78[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
20.891	-0.035	tSu		1	R18C78[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.248, 90.645%; tC2Q: 0.232, 9.355%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path7

Path Summary:

Slack	7.462
Data Arrival Time	13.429
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.688	0.688	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.949	0.261	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.181	0.232	tC2Q	FF	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.429	2.248	tNET	FF	1	R18C78[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R18C78[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
20.891	-0.035	tSu		1	R18C78[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.248, 90.645%; tC2Q: 0.232, 9.355%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path8

Path Summary:

Slack	7.462
Data Arrival Time	13.429
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.688	0.688	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.949	0.261	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.181	0.232	tC2Q	FF	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.429	2.248	tNET	FF	1	R18C78[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R18C78[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
20.891	-0.035	tSu		1	R18C78[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.248, 90.645%; tC2Q: 0.232, 9.355%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path9

Path Summary:

Slack	7.462
Data Arrival Time	13.429
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.688	0.688	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.949	0.261	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.181	0.232	tC2Q	FF	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.429	2.248	tNET	FF	1	R18C78[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R18C78[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
20.891	-0.035	tSu		1	R18C78[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.248, 90.645%; tC2Q: 0.232, 9.355%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path10

Path Summary:

Slack	7.468
Data Arrival Time	13.423
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.688	0.688	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.949	0.261	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.181	0.232	tC2Q	FF	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.423	2.242	tNET	FF	1	R17C78[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R17C78[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
20.891	-0.035	tSu		1	R17C78[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.242, 90.624%; tC2Q: 0.232, 9.376%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path11

Path Summary:

Slack	7.468
Data Arrival Time	13.423
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.688	0.688	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.949	0.261	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.181	0.232	tC2Q	FF	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.423	2.242	tNET	FF	1	R17C78[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R17C78[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
20.891	-0.035	tSu		1	R17C78[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.242, 90.624%; tC2Q: 0.232, 9.376%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path12

Path Summary:

Slack	7.710
Data Arrival Time	13.180
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.688	0.688	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.949	0.261	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.181	0.232	tC2Q	FF	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.180	2.000	tNET	FF	1	R16C80[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R16C80[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
20.891	-0.035	tSu		1	R16C80[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.000, 89.604%; tC2Q: 0.232, 10.396%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path13

Path Summary:

Slack	7.710
Data Arrival Time	13.180
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.688	0.688	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.949	0.261	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.181	0.232	tC2Q	FF	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.180	2.000	tNET	FF	1	R16C80[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R16C80[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
20.891	-0.035	tSu		1	R16C80[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.000, 89.604%; tC2Q: 0.232, 10.396%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path14

Path Summary:

Slack	7.710
Data Arrival Time	13.180
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.688	0.688	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.949	0.261	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.181	0.232	tC2Q	FF	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.180	2.000	tNET	FF	1	R16C80[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R16C80[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
20.891	-0.035	tSu		1	R16C80[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.000, 89.604%; tC2Q: 0.232, 10.396%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path15

Path Summary:

Slack	7.710
Data Arrival Time	13.180
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.688	0.688	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.949	0.261	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.181	0.232	tC2Q	FF	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.180	2.000	tNET	FF	1	R16C80[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R16C80[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
20.891	-0.035	tSu		1	R16C80[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.000, 89.604%; tC2Q: 0.232, 10.396%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path16

Path Summary:

Slack	7.710
Data Arrival Time	13.180
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.688	0.688	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.949	0.261	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.181	0.232	tC2Q	FF	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
13.180	2.000	tNET	FF	1	R16C80[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R16C80[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
20.891	-0.035	tSu		1	R16C80[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.000, 89.604%; tC2Q: 0.232, 10.396%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path17

Path Summary:

Slack	8.456
Data Arrival Time	12.435
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.688	0.688	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.949	0.261	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.181	0.232	tC2Q	FF	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.435	1.254	tNET	FF	1	R17C80[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R17C80[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
20.891	-0.035	tSu		1	R17C80[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.254, 84.390%; tC2Q: 0.232, 15.610%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path18

Path Summary:

Slack	8.456
Data Arrival Time	12.435
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.688	0.688	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.949	0.261	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.181	0.232	tC2Q	FF	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.435	1.254	tNET	FF	1	R17C80[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R17C80[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
20.891	-0.035	tSu		1	R17C80[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.254, 84.390%; tC2Q: 0.232, 15.610%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path19

Path Summary:

Slack	8.456
Data Arrival Time	12.435
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.688	0.688	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.949	0.261	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.181	0.232	tC2Q	FF	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.435	1.254	tNET	FF	1	R17C80[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R17C80[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
20.891	-0.035	tSu		1	R17C80[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.254, 84.390%; tC2Q: 0.232, 15.610%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path20

Path Summary:

Slack	8.461
Data Arrival Time	12.429
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.688	0.688	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.949	0.261	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.181	0.232	tC2Q	FF	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.429	1.248	tNET	FF	1	R15C80[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R15C80[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
20.891	-0.035	tSu		1	R15C80[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.248, 84.329%; tC2Q: 0.232, 15.671%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path21

Path Summary:

Slack	8.461
Data Arrival Time	12.429
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.688	0.688	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.949	0.261	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.181	0.232	tC2Q	FF	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.429	1.248	tNET	FF	1	R15C80[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R15C80[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
20.891	-0.035	tSu		1	R15C80[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.248, 84.329%; tC2Q: 0.232, 15.671%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path22

Path Summary:

Slack	8.461
Data Arrival Time	12.429
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.688	0.688	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.949	0.261	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.181	0.232	tC2Q	FF	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.429	1.248	tNET	FF	1	R15C80[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R15C80[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
20.891	-0.035	tSu		1	R15C80[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.248, 84.329%; tC2Q: 0.232, 15.671%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path23

Path Summary:

Slack	8.461
Data Arrival Time	12.429
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.688	0.688	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.949	0.261	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.181	0.232	tC2Q	FF	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.429	1.248	tNET	FF	1	R14C80[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R14C80[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0/CLK
20.891	-0.035	tSu		1	R14C80[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.248, 84.329%; tC2Q: 0.232, 15.671%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path24

Path Summary:

Slack	8.461
Data Arrival Time	12.429
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.688	0.688	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.949	0.261	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.181	0.232	tC2Q	FF	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.429	1.248	tNET	FF	1	R14C80[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R14C80[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLK
20.891	-0.035	tSu		1	R14C80[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.248, 84.329%; tC2Q: 0.232, 15.671%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path25

Path Summary:

Slack	8.467
Data Arrival Time	12.424
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.688	0.688	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.949	0.261	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.181	0.232	tC2Q	FF	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.424	1.243	tNET	FF	1	R18C80[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
20.683	0.683	tINS	RR	3571	IOR44[A]	clk_ibuf/O
20.926	0.243	tNET	RR	1	R18C80[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
20.891	-0.035	tSu		1	R18C80[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.243, 84.268%; tC2Q: 0.232, 15.732%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	10.469
Data Arrival Time	11.339
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.677	0.678	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.872	0.195	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.074	0.202	tC2Q	FR	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.339	0.265	tNET	RR	1	R29C73[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R29C73[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK
0.871	0.011	tHld		1	R29C73[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.265, 56.771%; tC2Q: 0.202, 43.229%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path2

Path Summary:

Slack	10.472
Data Arrival Time	11.342
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.677	0.678	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.872	0.195	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.074	0.202	tC2Q	FR	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.342	0.268	tNET	RR	1	R29C76[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R29C76[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLK
0.871	0.011	tHld		1	R29C76[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.268, 57.047%; tC2Q: 0.202, 42.953%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path3

Path Summary:

Slack	10.472
Data Arrival Time	11.342
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.677	0.678	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.872	0.195	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.074	0.202	tC2Q	FR	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.342	0.268	tNET	RR	1	R29C76[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R29C76[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK
0.871	0.011	tHld		1	R29C76[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.268, 57.047%; tC2Q: 0.202, 42.953%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path4

Path Summary:

Slack	10.472
Data Arrival Time	11.342
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.677	0.678	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.872	0.195	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.074	0.202	tC2Q	FR	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.342	0.268	tNET	RR	1	R29C76[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R29C76[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK
0.871	0.011	tHld		1	R29C76[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.268, 57.047%; tC2Q: 0.202, 42.953%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path5

Path Summary:

Slack	10.473
Data Arrival Time	11.343
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.677	0.678	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.872	0.195	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.074	0.202	tC2Q	FR	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.343	0.269	tNET	RR	1	R29C74[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R29C74[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
0.871	0.011	tHld		1	R29C74[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.269, 57.153%; tC2Q: 0.202, 42.847%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path6

Path Summary:

Slack	10.473
Data Arrival Time	11.343
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.677	0.678	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.872	0.195	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.074	0.202	tC2Q	FR	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.343	0.269	tNET	RR	1	R29C74[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R29C74[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK
0.871	0.011	tHld		1	R29C74[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.269, 57.153%; tC2Q: 0.202, 42.847%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path7

Path Summary:

Slack	10.473
Data Arrival Time	11.343
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.677	0.678	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.872	0.195	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.074	0.202	tC2Q	FR	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.343	0.269	tNET	RR	1	R29C74[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R29C74[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK
0.871	0.011	tHld		1	R29C74[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.269, 57.153%; tC2Q: 0.202, 42.847%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path8

Path Summary:

Slack	10.591
Data Arrival Time	11.461
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/start_reg_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.677	0.678	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.872	0.195	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.074	0.202	tC2Q	FR	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.461	0.387	tNET	RR	1	R30C78[0][A]	gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C78[0][A]	gw_gao_inst_0/u_la0_top/start_reg_s0/CLK
0.871	0.011	tHld		1	R30C78[0][A]	gw_gao_inst_0/u_la0_top/start_reg_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.387, 65.721%; tC2Q: 0.202, 34.279%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path9

Path Summary:

Slack	10.594
Data Arrival Time	11.464
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.677	0.678	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.872	0.195	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.074	0.202	tC2Q	FR	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.464	0.390	tNET	RR	1	R30C77[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C77[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK
0.871	0.011	tHld		1	R30C77[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.390, 65.894%; tC2Q: 0.202, 34.106%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path10

Path Summary:

Slack	10.594
Data Arrival Time	11.464
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.677	0.678	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.872	0.195	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.074	0.202	tC2Q	FR	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.464	0.390	tNET	RR	1	R30C77[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C77[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK
0.871	0.011	tHld		1	R30C77[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.390, 65.894%; tC2Q: 0.202, 34.106%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path11

Path Summary:

Slack	10.594
Data Arrival Time	11.464
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.677	0.678	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.872	0.195	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.074	0.202	tC2Q	FR	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.464	0.390	tNET	RR	1	R30C77[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C77[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK
0.871	0.011	tHld		1	R30C77[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.390, 65.894%; tC2Q: 0.202, 34.106%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path12

Path Summary:

Slack	10.623
Data Arrival Time	11.494
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.677	0.678	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.872	0.195	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.074	0.202	tC2Q	FR	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.494	0.420	tNET	RR	1	R30C79[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C79[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK
0.871	0.011	tHld		1	R30C79[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.420, 67.513%; tC2Q: 0.202, 32.487%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path13

Path Summary:

Slack	10.623
Data Arrival Time	11.494
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.677	0.678	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.872	0.195	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.074	0.202	tC2Q	FR	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.494	0.420	tNET	RR	1	R30C79[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C79[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
0.871	0.011	tHld		1	R30C79[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.420, 67.513%; tC2Q: 0.202, 32.487%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path14

Path Summary:

Slack	10.623
Data Arrival Time	11.494
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.677	0.678	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.872	0.195	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.074	0.202	tC2Q	FR	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.494	0.420	tNET	RR	1	R30C79[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C79[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK
0.871	0.011	tHld		1	R30C79[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.420, 67.513%; tC2Q: 0.202, 32.487%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path15

Path Summary:

Slack	10.626
Data Arrival Time	11.497
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.677	0.678	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.872	0.195	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.074	0.202	tC2Q	FR	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.497	0.423	tNET	RR	1	R29C79[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R29C79[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK
0.871	0.011	tHld		1	R29C79[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.423, 67.669%; tC2Q: 0.202, 32.331%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path16

Path Summary:

Slack	10.626
Data Arrival Time	11.497
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.677	0.678	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.872	0.195	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.074	0.202	tC2Q	FR	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.497	0.423	tNET	RR	1	R29C79[2][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R29C79[2][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK
0.871	0.011	tHld		1	R29C79[2][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.423, 67.669%; tC2Q: 0.202, 32.331%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path17

Path Summary:

Slack	10.742
Data Arrival Time	11.613
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.677	0.678	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.872	0.195	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.074	0.202	tC2Q	FR	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.613	0.539	tNET	RR	1	R24C79[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R24C79[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
0.871	0.011	tHld		1	R24C79[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.539, 72.732%; tC2Q: 0.202, 27.268%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path18

Path Summary:

Slack	10.754
Data Arrival Time	11.625
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.677	0.678	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.872	0.195	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.074	0.202	tC2Q	FR	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.625	0.551	tNET	RR	1	R29C80[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R29C80[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK
0.871	0.011	tHld		1	R29C80[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.551, 73.166%; tC2Q: 0.202, 26.834%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path19

Path Summary:

Slack	10.754
Data Arrival Time	11.625
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.677	0.678	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.872	0.195	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.074	0.202	tC2Q	FR	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.625	0.551	tNET	RR	1	R29C80[0][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R29C80[0][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK
0.871	0.011	tHld		1	R29C80[0][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.551, 73.166%; tC2Q: 0.202, 26.834%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path20

Path Summary:

Slack	10.754
Data Arrival Time	11.625
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.677	0.678	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.872	0.195	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.074	0.202	tC2Q	FR	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.625	0.551	tNET	RR	1	R29C80[1][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R29C80[1][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK
0.871	0.011	tHld		1	R29C80[1][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.551, 73.166%; tC2Q: 0.202, 26.834%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path21

Path Summary:

Slack	10.754
Data Arrival Time	11.625
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.677	0.678	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.872	0.195	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.074	0.202	tC2Q	FR	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.625	0.551	tNET	RR	1	R29C80[2][B]	gw_gao_inst_0/u_la0_top/triger_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R29C80[2][B]	gw_gao_inst_0/u_la0_top/triger_s0/CLK
0.871	0.011	tHld		1	R29C80[2][B]	gw_gao_inst_0/u_la0_top/triger_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.551, 73.166%; tC2Q: 0.202, 26.834%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path22

Path Summary:

Slack	10.919
Data Arrival Time	11.789
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.677	0.678	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.872	0.195	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.074	0.202	tC2Q	FR	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.789	0.715	tNET	RR	1	R18C80[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C80[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
0.871	0.011	tHld		1	R18C80[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.715, 77.979%; tC2Q: 0.202, 22.021%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path23

Path Summary:

Slack	10.922
Data Arrival Time	11.792
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.677	0.678	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.872	0.195	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.074	0.202	tC2Q	FR	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.792	0.718	tNET	RR	1	R15C80[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R15C80[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
0.871	0.011	tHld		1	R15C80[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.718, 78.050%; tC2Q: 0.202, 21.950%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path24

Path Summary:

Slack	10.922
Data Arrival Time	11.792
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.677	0.678	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.872	0.195	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.074	0.202	tC2Q	FR	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.792	0.718	tNET	RR	1	R15C80[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R15C80[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
0.871	0.011	tHld		1	R15C80[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.718, 78.050%; tC2Q: 0.202, 21.950%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path25

Path Summary:

Slack	10.922
Data Arrival Time	11.792
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	FF	1	IOR44[A]	clk_ibuf/I
10.677	0.678	tINS	FF	3571	IOR44[A]	clk_ibuf/O
10.872	0.195	tNET	FF	1	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.074	0.202	tC2Q	FR	49	R28C75[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.792	0.718	tNET	RR	1	R15C80[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOR44[A]	clk_ibuf/I
0.675	0.675	tINS	RR	3571	IOR44[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R15C80[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
0.871	0.011	tHld		1	R15C80[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.718, 78.050%; tC2Q: 0.202, 21.950%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	8.911
Actual Width:	9.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	cnt_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
10.688	0.688	tINS	FF	clk_ibuf/O
10.949	0.261	tNET	FF	cnt_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk
20.000	0.000	tCL	RR	clk_ibuf/I
20.676	0.675	tINS	RR	clk_ibuf/O
20.860	0.184	tNET	RR	cnt_2_s0/CLK

MPW2

MPW Summary:

Slack:	8.911
Actual Width:	9.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	gainwe_s2

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
10.688	0.688	tINS	FF	clk_ibuf/O
10.949	0.261	tNET	FF	gainwe_s2/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk
20.000	0.000	tCL	RR	clk_ibuf/I
20.676	0.675	tINS	RR	clk_ibuf/O
20.860	0.184	tNET	RR	gainwe_s2/CLK

MPW3

MPW Summary:

Slack:	8.911
Actual Width:	9.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	cnt_cycle_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
10.688	0.688	tINS	FF	clk_ibuf/O
10.949	0.261	tNET	FF	cnt_cycle_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk
20.000	0.000	tCL	RR	clk_ibuf/I
20.676	0.675	tINS	RR	clk_ibuf/O
20.860	0.184	tNET	RR	cnt_cycle_2_s0/CLK

MPW4

MPW Summary:

Slack:	8.911
Actual Width:	9.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	i_data_0_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
10.688	0.688	tINS	FF	clk_ibuf/O
10.949	0.261	tNET	FF	i_data_0_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk
20.000	0.000	tCL	RR	clk_ibuf/I
20.676	0.675	tINS	RR	clk_ibuf/O
20.860	0.184	tNET	RR	i_data_0_s1/CLK

MPW5

MPW Summary:

Slack:	8.911
Actual Width:	9.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	addr_4_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
10.688	0.688	tINS	FF	clk_ibuf/O
10.949	0.261	tNET	FF	addr_4_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk
20.000	0.000	tCL	RR	clk_ibuf/I
20.676	0.675	tINS	RR	clk_ibuf/O
20.860	0.184	tNET	RR	addr_4_s1/CLK

MPW6

MPW Summary:

Slack:	8.911
Actual Width:	9.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	Equalizer_inst/Equalizer_inst_0/gain_addr_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
10.688	0.688	tINS	FF	clk_ibuf/O
10.949	0.261	tNET	FF	Equalizer_inst/Equalizer_inst_0/gain_addr_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk
20.000	0.000	tCL	RR	clk_ibuf/I
20.676	0.675	tINS	RR	clk_ibuf/O
20.860	0.184	tNET	RR	Equalizer_inst/Equalizer_inst_0/gain_addr_1_s0/CLK

MPW7

MPW Summary:

Slack:	8.911
Actual Width:	9.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	Equalizer_inst/Equalizer_inst_0/coeff_a1_reg[2]_4_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
10.688	0.688	tINS	FF	clk_ibuf/O
10.949	0.261	tNET	FF	Equalizer_inst/Equalizer_inst_0/coeff_a1_reg[2]_4_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk
20.000	0.000	tCL	RR	clk_ibuf/I
20.676	0.675	tINS	RR	clk_ibuf/O
20.860	0.184	tNET	RR	Equalizer_inst/Equalizer_inst_0/coeff_a1_reg[2]_4_s0/CLK

MPW8

MPW Summary:

Slack:	8.911
Actual Width:	9.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	Equalizer_inst/Equalizer_inst_0/coeff_a1_reg[9]_16_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
10.688	0.688	tINS	FF	clk_ibuf/O
10.949	0.261	tNET	FF	Equalizer_inst/Equalizer_inst_0/coeff_a1_reg[9]_16_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk
20.000	0.000	tCL	RR	clk_ibuf/I
20.676	0.675	tINS	RR	clk_ibuf/O
20.860	0.184	tNET	RR	Equalizer_inst/Equalizer_inst_0/coeff_a1_reg[9]_16_s0/CLK

MPW9

MPW Summary:

Slack:	8.911
Actual Width:	9.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	Equalizer_inst/Equalizer_inst_0/coeff_a2_reg[5]_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
10.688	0.688	tINS	FF	clk_ibuf/O
10.949	0.261	tNET	FF	Equalizer_inst/Equalizer_inst_0/coeff_a2_reg[5]_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk
20.000	0.000	tCL	RR	clk_ibuf/I
20.676	0.675	tINS	RR	clk_ibuf/O
20.860	0.184	tNET	RR	Equalizer_inst/Equalizer_inst_0/coeff_a2_reg[5]_0_s0/CLK

MPW10

MPW Summary:

Slack:	8.911
Actual Width:	9.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	Equalizer_inst/Equalizer_inst_0/coeff_b1_reg[15]_8_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
10.688	0.688	tINS	FF	clk_ibuf/O
10.949	0.261	tNET	FF	Equalizer_inst/Equalizer_inst_0/coeff_b1_reg[15]_8_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			clk
20.000	0.000	tCL	RR	clk_ibuf/I
20.676	0.675	tINS	RR	clk_ibuf/O
20.860	0.184	tNET	RR	Equalizer_inst/Equalizer_inst_0/coeff_b1_reg[15]_8_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
3571	clk_d	3.483	0.261
1607	cnt_band[0]	3.483	7.017
855	cnt_band[1]	4.945	5.859
390	cnt_band[2]	5.816	4.087
371	gainwe_d	12.647	3.815
323	control0[0]	4.400	0.912
233	dout_y_reg_38_9	14.182	3.491
196	cnt_band[3]	6.528	3.245
100	n21355_5	15.513	2.270
100	n21335_5	15.634	2.315

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R20C33	88.89%
R26C17	88.89%
R31C16	87.50%
R26C48	87.50%
R15C23	86.11%
R14C35	86.11%
R16C42	86.11%
R17C22	86.11%
R24C78	86.11%
R22C70	86.11%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name clk -period 20 -waveform {0 10} [get_ports {clk}]
TC_CLOCK	Actived	create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_ports {tck_pad_i}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {clk}] -to [get_clocks {tck_pad_i}]