| Report Title |
Power Analysis Report |
| Design File |
E:\myWork\IP\releaseVerify\RefDesign\MultMedia\zipFile\1.9.9beta-3\Gowin_Equalizer_RefDesign\proj\impl\gwsynthesis\Equalizer.vg |
| Physical Constraints File |
E:\myWork\IP\releaseVerify\RefDesign\MultMedia\zipFile\1.9.9beta-3\Gowin_Equalizer_RefDesign\proj\src\Equalizer.cst |
| Timing Constraints File |
E:\myWork\IP\releaseVerify\RefDesign\MultMedia\zipFile\1.9.9beta-3\Gowin_Equalizer_RefDesign\proj\src\Equalizer.sdc |
| Version |
V1.9.9 Beta-3 |
| Part Number |
GW2A-LV55PG484C8/I7 |
| Device |
GW2A-55 |
| Device Version |
C |
| Created Time |
Mon Aug 21 15:11:45 2023
|
| Legal Announcement |
Copyright (C)2014-2023 Gowin Semiconductor Corporation. All rights reserved. |
| Total Power (mW) |
241.882 |
| Quiescent Power (mW) |
199.656 |
| Dynamic Power (mW) |
42.226 |
| Junction Temperature |
29.526 |
| Theta JA |
18.710 |
| Max Allowed Ambient Temperature |
80.474 |
| Default IO Toggle Rate |
0.125 |
Default Remain Toggle Rate |
0.125 |
| Use Vectorless Estimation |
false |
| Filter Glitches |
false |
| Related Vcd File |
|
| Related Saif File |
|
| Use Custom Theta JA |
false |
| Air Flow |
LFM_0 |
| Heat Sink |
None |
| Use Custom Theta SA |
false |
| Board Thermal Model |
None |
| Use Custom Theta JB |
false |
| Ambient Temperature |
25.000
|
| Voltage Source |
Voltage |
Dynamic Current(mA) |
Quiescent Current(mA) |
Power(mW) |
| VCC |
1.000 |
35.167 |
131.698 |
166.866 |
| VCCX |
2.500 |
1.684 |
26.515 |
70.497 |
| VCCIO12 |
1.200 |
0.300 |
0.093 |
0.471 |
| VCCIO18 |
1.800 |
1.384 |
0.865 |
4.048 |
| Block Type |
Total Power(mW) |
Static Power(mW) |
Average Toggle Rate(millions of transitions/sec) |
| Logic |
2.984 |
NA |
5.895 |
| IO |
18.774
| 10.032
| 7.182
|
| BSRAM |
30.492
| NA |
NA |
| Hierarchy Entity |
Total Power(mW) |
Block Dynamic Power(mW) |
| top |
33.476 |
33.476(32.671) |
| top/Equalizer_inst/ |
6.326 |
6.326(6.326) |
| top/Equalizer_inst/Equalizer_inst_0/ |
6.326 |
6.326(3.749) |
| top/Equalizer_inst/Equalizer_inst_0/coeff_a_rom/ |
1.488 |
1.488(0.000) |
| top/Equalizer_inst/Equalizer_inst_0/coeff_b_rom/ |
2.259 |
2.259(0.000) |
| top/Equalizer_inst/Equalizer_inst_0/syn_gainwe/ |
0.000 |
0.000(0.000) |
| top/Equalizer_inst/Equalizer_inst_0/syn_in_valid/ |
0.001 |
0.001(0.000) |
| top/gw_gao_inst_0/ |
26.345 |
26.345(26.345) |
| top/gw_gao_inst_0/u_icon_top/ |
0.005 |
0.005(0.000) |
| top/gw_gao_inst_0/u_la0_top/ |
26.340 |
26.340(26.228) |
| top/gw_gao_inst_0/u_la0_top/u_ao_crc32/ |
0.010 |
0.010(0.000) |
| top/gw_gao_inst_0/u_la0_top/u_ao_match_0/ |
0.003 |
0.003(0.000) |
| top/gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/ |
26.215 |
26.215(0.000) |
| Clock Domain |
Clock Frequency(Mhz) |
Total Dynamic Power(mW) |
| clk |
50.000 |
25.908 |
| tck_pad_i |
20.000 |
7.575 |
| NO CLOCK DOMAIN |
0.000 |
0.000 |