Project Settings
Project Name lossy_ex Device Name rev_1: GOWIN-GW2A : GW2A_55
Implementation Name rev_1 Top Module TOP
Pipelining 1 Retiming 0
Resource Sharing 1 Fanout Guide 10000
Disable I/O Insertion 0 Disable Sequential Optimizations 0
Clock Conversion 1 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 12 1 0 - 00m:01s - 2018/9/17
18:51:45
(premap)Complete 13 0 0 0m:01s 0m:01s 191MB 2018/9/17
18:51:48
(fpga_mapper)Complete 12 2 0 0m:03s 0m:02s 191MB 2018/9/17
18:51:51
Multi-srs Generator Complete2018/9/17
18:51:46

Area Summary
I/O ports (io_port) 9 Non I/O Register bits (non_io_reg) 36 (0%)
I/O Register bits (total_io_reg) 0 Block Rams (v_ram) 1 (140)
Block Multipliers (dsp_used) 0 (20) LUTs (total_luts) 31 (0%)

Timing Summary
Clock NameReq FreqEst FreqSlack
GW_PLL|clkout_inferred_clock242.7 MHz206.3 MHz-0.727
System2199.3 MHz1869.2 MHz-0.080

Optimizations Summary
Combined Clock Conversion 0 / 1