Timing Messages
| Report Title | Gowin Timing Analysis Report |
| Tool Version | v1.8.1.01Beta |
| Series, Device, Package, Speed, Operating Conditions | GW2A, GW2A-55, PBGA484, 8, COMMERCIAL |
| Design Name | TOP |
| Design File | E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossless_ex\project\impl\synthesize\rev_1\lossless_ex.vm |
| Timing Constraint File | --- |
| Timing Report File | E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossless_ex\project\impl\pnr\lossless_ex.tr.html |
| Created Time | Wed Sep 19 08:47:03 2018 |
| Command Line | D:\Gowin\1.8\Pnr\bin\gowin.exe -do E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Lossless_ex\project\impl\pnr\cmd.do |
| Legal Announcement | Copyright (C)2014-2018 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
| Setup Delay Model | Slow 0.95V 85C |
| Hold Delay Model | Fast 1.05V 0C |
| Numbers of Paths Analyzed | 707 |
| Numbers of Endpoints Analyzed | 1283 |
| Numbers of Falling Endpoints | 1 |
| Numbers of Setup Violated Endpoints | 86 |
| Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
|---|---|---|---|---|---|---|---|---|
| osc_inst/osc_inst/OSCOUT.default_clk | Base | 40.000 | 25.000 | 0.000 | 20.000 | |||
| GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk | Generated | 5.556 | 180.000 | 0.000 | 2.778 | osc_inst/osc_inst/OSCOUT.default_clk | ||
| GW_PLL_inst/pll_inst/CLKOUTP.default_gen_clk | Generated | 5.556 | 180.000 | 0.000 | 2.778 | osc_inst/osc_inst/OSCOUT.default_clk | ||
| GW_PLL_inst/pll_inst/CLKOUTD.default_gen_clk | Generated | 11.111 | 90.000 | 0.000 | 5.556 | osc_inst/osc_inst/OSCOUT.default_clk | ||
| GW_PLL_inst/pll_inst/CLKOUTD3.default_gen_clk | Generated | 16.667 | 60.000 | 0.000 | 8.333 | osc_inst/osc_inst/OSCOUT.default_clk |
Max Frequency Summary:
| NO. | Clock Name | Fmax | Entity |
|---|---|---|---|
| 1 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk | 117.100(MHz) | TOP |
No timing paths to get frequency of osc_inst/osc_inst/OSCOUT.default_clk!
No timing paths to get frequency of GW_PLL_inst/pll_inst/CLKOUTP.default_gen_clk!
No timing paths to get frequency of GW_PLL_inst/pll_inst/CLKOUTD.default_gen_clk!
No timing paths to get frequency of GW_PLL_inst/pll_inst/CLKOUTD3.default_gen_clk!
Total Negative Slack Summary:
| Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
|---|---|---|---|
| osc_inst/osc_inst/OSCOUT.default_clk | Setup | 0.000 | 0 |
| osc_inst/osc_inst/OSCOUT.default_clk | Hold | 0.000 | 0 |
| GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk | Setup | -111.979 | 86 |
| GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk | Hold | 0.000 | 0 |
| GW_PLL_inst/pll_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0 |
| GW_PLL_inst/pll_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0 |
| GW_PLL_inst/pll_inst/CLKOUTD.default_gen_clk | Setup | 0.000 | 0 |
| GW_PLL_inst/pll_inst/CLKOUTD.default_gen_clk | Hold | 0.000 | 0 |
| GW_PLL_inst/pll_inst/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0 |
| GW_PLL_inst/pll_inst/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | -2.984 | ADDR_Z[5]/Q | u_la0_top/genblk1.u_ao_match_0/match_sep/D | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 5.556 | 0.000 | 8.305 |
| 2 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 3 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 4 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 5 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 6 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/trigger_seq_start_Z/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 7 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 8 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/capture_window_sel_Z[1]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 9 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 10 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/triger_level_cnt_Z[1]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 11 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 12 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/capture_window_sel_Z[0]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 13 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 14 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/internal_reg_start_syn_Z[1]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 15 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 16 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 17 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 18 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/triger_level_cnt_Z[0]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 19 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 20 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 21 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 22 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 23 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 24 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 25 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/triger_level_cnt_Z[3]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 0.333 | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[3]/Q | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/ADA6 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.451 |
| 2 | 0.336 | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[8]/Q | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/ADA11 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.454 |
| 3 | 0.336 | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[6]/Q | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/ADA9 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.454 |
| 4 | 0.336 | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[5]/Q | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/ADA8 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.454 |
| 5 | 0.347 | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[7]/Q | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/ADA10 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.465 |
| 6 | 0.358 | u_RAM_based_shift_reg/u_RAM_based_shift_reg/rbin_num_Z[7]/Q | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/ADB10 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.476 |
| 7 | 0.359 | u_RAM_based_shift_reg/u_RAM_based_shift_reg/rbin_num_Z[8]/Q | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/ADB11 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.477 |
| 8 | 0.458 | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[2]/Q | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/ADA5 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.576 |
| 9 | 0.458 | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[1]/Q | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/ADA4 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.576 |
| 10 | 0.458 | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[0]/Q | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/ADA3 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.576 |
| 11 | 0.469 | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[4]/Q | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/ADA7 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.587 |
| 12 | 0.496 | u_RAM_based_shift_reg/u_RAM_based_shift_reg/rbin_num_Z[5]/Q | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/ADB8 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.614 |
| 13 | 0.496 | u_RAM_based_shift_reg/u_RAM_based_shift_reg/rbin_num_Z[6]/Q | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/ADB9 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.614 |
| 14 | 0.496 | u_RAM_based_shift_reg/u_RAM_based_shift_reg/rbin_num_Z[2]/Q | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/ADB5 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.614 |
| 15 | 0.496 | u_RAM_based_shift_reg/u_RAM_based_shift_reg/rbin_num_Z[0]/Q | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/ADB3 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.614 |
| 16 | 0.511 | u_RAM_based_shift_reg/u_RAM_based_shift_reg/rbin_num_Z[1]/Q | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/ADB4 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.629 |
| 17 | 0.546 | ADDR[0]/Q | ADDR[0]/D | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.557 |
| 18 | 0.557 | cnt_Z[0]/Q | cnt_Z[0]/D | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.568 |
| 19 | 0.557 | Din_Z[0]/Q | Din_Z[0]/D | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.568 |
| 20 | 0.557 | Din_Z[2]/Q | Din_Z[2]/D | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.568 |
| 21 | 0.557 | Din_Z[6]/Q | Din_Z[6]/D | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.568 |
| 22 | 0.559 | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[6]/Q | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[6]/D | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.570 |
| 23 | 0.559 | ADDR_Z[6]/Q | ADDR_Z[6]/D | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.570 |
| 24 | 0.559 | ADDR_Z[8]/Q | ADDR_Z[8]/D | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.570 |
| 25 | 0.559 | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[0]/Q | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[0]/D | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.570 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 2 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 3 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 4 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 5 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 6 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 7 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/trigger_seq_start_Z/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 8 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 9 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 10 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 11 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 12 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 13 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 14 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/capture_window_sel_Z[0]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 15 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/capture_window_sel_Z[1]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 16 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/capture_window_sel_Z[2]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 17 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 18 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 19 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 20 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 21 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/internal_reg_start_syn_Z[1]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 22 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/capture_window_sel[3]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 23 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 24 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
| 25 | -0.865 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | 2.778 | 0.423 | 2.984 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 4.931 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.958 |
| 2 | 4.931 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.958 |
| 3 | 4.931 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.958 |
| 4 | 4.931 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.958 |
| 5 | 4.931 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.958 |
| 6 | 4.931 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.958 |
| 7 | 4.931 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.958 |
| 8 | 4.931 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.958 |
| 9 | 4.931 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.958 |
| 10 | 4.931 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.958 |
| 11 | 4.931 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.958 |
| 12 | 4.931 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.958 |
| 13 | 4.931 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.958 |
| 14 | 4.931 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.958 |
| 15 | 4.931 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.958 |
| 16 | 4.931 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.958 |
| 17 | 4.931 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.958 |
| 18 | 4.931 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.958 |
| 19 | 4.931 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.958 |
| 20 | 4.931 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.958 |
| 21 | 4.931 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.958 |
| 22 | 4.931 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.958 |
| 23 | 4.931 | u_la0_top/rst_ao_Z/Q | u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.958 |
| 24 | 4.931 | u_la0_top/rst_ao_Z/Q | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.958 |
| 25 | 4.931 | u_la0_top/rst_ao_Z/Q | u_la0_top/internal_reg_start_syn_Z[1]/CLEAR | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] | -2.778 | 0.406 | 1.958 |
Minimum Pulse Width Table:
| Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
|---|---|---|---|---|---|---|
| 1 | 1.056 | 2.056 | 1.000 | Low Pulse Width | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk | Din_Z[7] |
| 2 | 1.056 | 2.056 | 1.000 | Low Pulse Width | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk | Din_Z[5] |
| 3 | 1.056 | 2.056 | 1.000 | Low Pulse Width | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk | Din_Z[1] |
| 4 | 1.056 | 2.056 | 1.000 | Low Pulse Width | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk | cnt_Z[0] |
| 5 | 1.056 | 2.056 | 1.000 | Low Pulse Width | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk | u_RAM_based_shift_reg/u_RAM_based_shift_reg/rbin_num_Z[0] |
| 6 | 1.056 | 2.056 | 1.000 | Low Pulse Width | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk | u_la0_top/triger_level_cnt_Z[0] |
| 7 | 1.056 | 2.056 | 1.000 | Low Pulse Width | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk | u_la0_top/u_ao_mem_ctrl/mem_mem_0_1 |
| 8 | 1.056 | 2.056 | 1.000 | Low Pulse Width | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk | u_la0_top/u_ao_mem_ctrl/mem_mem_0_0 |
| 9 | 1.056 | 2.056 | 1.000 | Low Pulse Width | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk | u_la0_top/triger_level_cnt_Z[1] |
| 10 | 1.056 | 2.056 | 1.000 | Low Pulse Width | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | -2.984 |
| Data Arrival Time | 11.237 |
| Data Required Time | 8.253 |
| From | ADDR_Z[5] |
| To | u_la0_top/genblk1.u_ao_match_0/match_sep |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.933 | 1.201 | tNET | RR | 1 | R47C39[0][A] | ADDR_Z[5]/CLK |
| 3.165 | 0.232 | tC2Q | RF | 9 | R47C39[0][A] | ADDR_Z[5]/Q |
| 5.938 | 2.773 | tNET | FF | 1 | R14C4[3][A] | u_la0_top/genblk1.u_ao_match_0/trig_eqmin_5_cZ/I1 |
| 6.493 | 0.555 | tINS | FF | 2 | R14C4[3][A] | u_la0_top/genblk1.u_ao_match_0/trig_eqmin_5_cZ/F |
| 7.286 | 0.793 | tNET | FF | 1 | R3C6[3][A] | u_la0_top/genblk1.u_ao_match_0/trig_eqmin_NE_4_cZ/I3 |
| 7.657 | 0.371 | tINS | FF | 1 | R3C6[3][A] | u_la0_top/genblk1.u_ao_match_0/trig_eqmin_NE_4_cZ/F |
| 8.175 | 0.518 | tNET | FF | 1 | R6C7[3][B] | u_la0_top/genblk1.u_ao_match_0/trig_eqmin_NE_6_cZ/I3 |
| 8.546 | 0.371 | tINS | FF | 1 | R6C7[3][B] | u_la0_top/genblk1.u_ao_match_0/trig_eqmin_NE_6_cZ/F |
| 8.716 | 0.170 | tNET | FF | 1 | R7C7[3][B] | u_la0_top/genblk1.u_ao_match_0/trig_eqmin_NE_1_RNISVUH/I2 |
| 9.169 | 0.453 | tINS | FF | 2 | R7C7[3][B] | u_la0_top/genblk1.u_ao_match_0/trig_eqmin_NE_1_RNISVUH/F |
| 9.587 | 0.418 | tNET | FF | 1 | R6C6[2][B] | u_la0_top/genblk1.u_ao_match_0/match_sep_RNO_3/I1 |
| 10.142 | 0.555 | tINS | FF | 1 | R6C6[2][B] | u_la0_top/genblk1.u_ao_match_0/match_sep_RNO_3/F |
| 10.555 | 0.413 | tNET | FF | 1 | R8C7[2][A] | u_la0_top/genblk1.u_ao_match_0/match_sep_RNO_0/I1 |
| 11.125 | 0.570 | tINS | FR | 1 | R8C7[2][A] | u_la0_top/genblk1.u_ao_match_0/match_sep_RNO_0/F |
| 11.125 | 0.000 | tNET | RR | 1 | R8C7[2][A] | u_la0_top/genblk1.u_ao_match_0/match_sep_RNO/I0 |
| 11.230 | 0.105 | tINS | RR | 1 | R8C7[2][A] | u_la0_top/genblk1.u_ao_match_0/match_sep_RNO/O |
| 11.237 | 0.007 | tNET | RR | 1 | R8C7[2][A] | u_la0_top/genblk1.u_ao_match_0/match_sep/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R8C7[2][A] | u_la0_top/genblk1.u_ao_match_0/match_sep/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/genblk1.u_ao_match_0/match_sep | |||
| 8.253 | -0.035 | tSu | 1 | R8C7[2][A] | u_la0_top/genblk1.u_ao_match_0/match_sep |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 5.556 |
| Logic Level | 7 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
| Arrival Data Path Delay | cell: 2.980, 35.883%; route: 5.093, 61.323%; tC2Q: 0.232, 2.794% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path2
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/genblk1.u_ao_match_0/match_sep |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R8C7[2][A] | u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R8C7[2][A] | u_la0_top/genblk1.u_ao_match_0/match_sep/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/genblk1.u_ao_match_0/match_sep | |||
| 8.253 | -0.035 | tSu | 1 | R8C7[2][A] | u_la0_top/genblk1.u_ao_match_0/match_sep |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path3
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R5C3[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R5C3[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9] | |||
| 8.253 | -0.035 | tSu | 1 | R5C3[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9] |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path4
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R8C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R8C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4] | |||
| 8.253 | -0.035 | tSu | 1 | R8C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4] |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path5
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R8C9[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R8C9[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5] | |||
| 8.253 | -0.035 | tSu | 1 | R8C9[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5] |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path6
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/trigger_seq_start_Z |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R7C10[0][A] | u_la0_top/trigger_seq_start_Z/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R7C10[0][A] | u_la0_top/trigger_seq_start_Z/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/trigger_seq_start_Z | |||
| 8.253 | -0.035 | tSu | 1 | R7C10[0][A] | u_la0_top/trigger_seq_start_Z |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path7
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R9C10[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R9C10[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8] | |||
| 8.253 | -0.035 | tSu | 1 | R9C10[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8] |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path8
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/capture_window_sel_Z[1] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R12C9[1][B] | u_la0_top/capture_window_sel_Z[1]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R12C9[1][B] | u_la0_top/capture_window_sel_Z[1]/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/capture_window_sel_Z[1] | |||
| 8.253 | -0.035 | tSu | 1 | R12C9[1][B] | u_la0_top/capture_window_sel_Z[1] |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path9
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R8C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R8C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7] | |||
| 8.253 | -0.035 | tSu | 1 | R8C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7] |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path10
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/triger_level_cnt_Z[1] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R4C2[1][A] | u_la0_top/triger_level_cnt_Z[1]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R4C2[1][A] | u_la0_top/triger_level_cnt_Z[1]/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/triger_level_cnt_Z[1] | |||
| 8.253 | -0.035 | tSu | 1 | R4C2[1][A] | u_la0_top/triger_level_cnt_Z[1] |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path11
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R11C10[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R11C10[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2] | |||
| 8.253 | -0.035 | tSu | 1 | R11C10[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2] |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path12
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/capture_window_sel_Z[0] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R12C9[1][A] | u_la0_top/capture_window_sel_Z[0]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R12C9[1][A] | u_la0_top/capture_window_sel_Z[0]/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/capture_window_sel_Z[0] | |||
| 8.253 | -0.035 | tSu | 1 | R12C9[1][A] | u_la0_top/capture_window_sel_Z[0] |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path13
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R9C10[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R9C10[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1] | |||
| 8.253 | -0.035 | tSu | 1 | R9C10[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1] |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path14
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/internal_reg_start_syn_Z[1] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R9C3[2][B] | u_la0_top/internal_reg_start_syn_Z[1]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/internal_reg_start_syn_Z[1]/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/internal_reg_start_syn_Z[1] | |||
| 8.253 | -0.035 | tSu | 1 | R9C3[2][B] | u_la0_top/internal_reg_start_syn_Z[1] |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path15
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_loop_Z |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R9C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R9C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_loop_Z | |||
| 8.253 | -0.035 | tSu | 1 | R9C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_Z |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path16
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R5C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R5C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6] | |||
| 8.253 | -0.035 | tSu | 1 | R5C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6] |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path17
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R8C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R8C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3] | |||
| 8.253 | -0.035 | tSu | 1 | R8C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3] |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path18
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/triger_level_cnt_Z[0] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R6C3[2][B] | u_la0_top/triger_level_cnt_Z[0]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R6C3[2][B] | u_la0_top/triger_level_cnt_Z[0]/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/triger_level_cnt_Z[0] | |||
| 8.253 | -0.035 | tSu | 1 | R6C3[2][B] | u_la0_top/triger_level_cnt_Z[0] |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path19
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R8C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R8C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5] | |||
| 8.253 | -0.035 | tSu | 1 | R8C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5] |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path20
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R4C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R4C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9] | |||
| 8.253 | -0.035 | tSu | 1 | R4C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9] |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path21
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R5C11[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R5C11[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0] | |||
| 8.253 | -0.035 | tSu | 1 | R5C11[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0] |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path22
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R4C2[2][A] | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R4C2[2][A] | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z | |||
| 8.253 | -0.035 | tSu | 1 | R4C2[2][A] | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path23
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R8C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R8C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6] | |||
| 8.253 | -0.035 | tSu | 1 | R8C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6] |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path24
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R9C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R9C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z | |||
| 8.253 | -0.035 | tSu | 1 | R9C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path25
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/triger_level_cnt_Z[3] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R6C3[2][A] | u_la0_top/triger_level_cnt_Z[3]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R6C3[2][A] | u_la0_top/triger_level_cnt_Z[3]/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/triger_level_cnt_Z[3] | |||
| 8.253 | -0.035 | tSu | 1 | R6C3[2][A] | u_la0_top/triger_level_cnt_Z[3] |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 0.333 |
| Data Arrival Time | 3.085 |
| Data Required Time | 2.752 |
| From | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[3] |
| To | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R47C52[2][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[3]/CLK |
| 2.836 | 0.202 | tC2Q | RR | 3 | R47C52[2][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[3]/Q |
| 3.085 | 0.249 | tNET | RR | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/ADA6 |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/CLKA |
| 2.634 | 0.000 | tUnc | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 | |||
| 2.752 | 0.118 | tHld | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.249, 55.255%; tC2Q: 0.202, 44.745% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path2
Path Summary:
| Slack | 0.336 |
| Data Arrival Time | 3.087 |
| Data Required Time | 2.752 |
| From | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[8] |
| To | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R47C53[1][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[8]/CLK |
| 2.836 | 0.202 | tC2Q | RR | 3 | R47C53[1][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[8]/Q |
| 3.087 | 0.252 | tNET | RR | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/ADA11 |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/CLKA |
| 2.634 | 0.000 | tUnc | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 | |||
| 2.752 | 0.118 | tHld | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.252, 55.471%; tC2Q: 0.202, 44.529% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path3
Path Summary:
| Slack | 0.336 |
| Data Arrival Time | 3.087 |
| Data Required Time | 2.752 |
| From | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[6] |
| To | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R47C53[0][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[6]/CLK |
| 2.836 | 0.202 | tC2Q | RR | 3 | R47C53[0][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[6]/Q |
| 3.087 | 0.252 | tNET | RR | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/ADA9 |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/CLKA |
| 2.634 | 0.000 | tUnc | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 | |||
| 2.752 | 0.118 | tHld | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.252, 55.471%; tC2Q: 0.202, 44.529% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path4
Path Summary:
| Slack | 0.336 |
| Data Arrival Time | 3.087 |
| Data Required Time | 2.752 |
| From | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[5] |
| To | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R47C53[0][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[5]/CLK |
| 2.836 | 0.202 | tC2Q | RR | 3 | R47C53[0][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[5]/Q |
| 3.087 | 0.252 | tNET | RR | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/ADA8 |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/CLKA |
| 2.634 | 0.000 | tUnc | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 | |||
| 2.752 | 0.118 | tHld | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.252, 55.471%; tC2Q: 0.202, 44.529% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path5
Path Summary:
| Slack | 0.347 |
| Data Arrival Time | 3.099 |
| Data Required Time | 2.752 |
| From | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[7] |
| To | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R47C53[1][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[7]/CLK |
| 2.836 | 0.202 | tC2Q | RR | 3 | R47C53[1][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[7]/Q |
| 3.099 | 0.263 | tNET | RR | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/ADA10 |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/CLKA |
| 2.634 | 0.000 | tUnc | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 | |||
| 2.752 | 0.118 | tHld | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.263, 56.544%; tC2Q: 0.202, 43.456% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path6
Path Summary:
| Slack | 0.358 |
| Data Arrival Time | 3.109 |
| Data Required Time | 2.752 |
| From | u_RAM_based_shift_reg/u_RAM_based_shift_reg/rbin_num_Z[7] |
| To | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R46C49[0][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/rbin_num_Z[7]/CLK |
| 2.836 | 0.202 | tC2Q | RR | 3 | R46C49[0][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/rbin_num_Z[7]/Q |
| 3.109 | 0.274 | tNET | RR | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/ADB10 |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/CLKB |
| 2.634 | 0.000 | tUnc | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 | |||
| 2.752 | 0.118 | tHld | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.274, 57.536%; tC2Q: 0.202, 42.464% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path7
Path Summary:
| Slack | 0.359 |
| Data Arrival Time | 3.111 |
| Data Required Time | 2.752 |
| From | u_RAM_based_shift_reg/u_RAM_based_shift_reg/rbin_num_Z[8] |
| To | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R46C49[0][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/rbin_num_Z[8]/CLK |
| 2.836 | 0.202 | tC2Q | RR | 4 | R46C49[0][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/rbin_num_Z[8]/Q |
| 3.111 | 0.275 | tNET | RR | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/ADB11 |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/CLKB |
| 2.634 | 0.000 | tUnc | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 | |||
| 2.752 | 0.118 | tHld | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.275, 57.645%; tC2Q: 0.202, 42.355% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path8
Path Summary:
| Slack | 0.458 |
| Data Arrival Time | 3.209 |
| Data Required Time | 2.752 |
| From | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[2] |
| To | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R47C52[1][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[2]/CLK |
| 2.836 | 0.202 | tC2Q | RR | 3 | R47C52[1][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[2]/Q |
| 3.209 | 0.374 | tNET | RR | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/ADA5 |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/CLKA |
| 2.634 | 0.000 | tUnc | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 | |||
| 2.752 | 0.118 | tHld | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.374, 64.908%; tC2Q: 0.202, 35.092% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path9
Path Summary:
| Slack | 0.458 |
| Data Arrival Time | 3.209 |
| Data Required Time | 2.752 |
| From | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[1] |
| To | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R47C52[1][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[1]/CLK |
| 2.836 | 0.202 | tC2Q | RR | 6 | R47C52[1][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[1]/Q |
| 3.209 | 0.374 | tNET | RR | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/ADA4 |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/CLKA |
| 2.634 | 0.000 | tUnc | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 | |||
| 2.752 | 0.118 | tHld | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.374, 64.908%; tC2Q: 0.202, 35.092% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path10
Path Summary:
| Slack | 0.458 |
| Data Arrival Time | 3.209 |
| Data Required Time | 2.752 |
| From | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[0] |
| To | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R47C52[0][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[0]/CLK |
| 2.836 | 0.202 | tC2Q | RR | 3 | R47C52[0][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[0]/Q |
| 3.209 | 0.374 | tNET | RR | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/ADA3 |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/CLKA |
| 2.634 | 0.000 | tUnc | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 | |||
| 2.752 | 0.118 | tHld | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.374, 64.908%; tC2Q: 0.202, 35.092% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path11
Path Summary:
| Slack | 0.469 |
| Data Arrival Time | 3.221 |
| Data Required Time | 2.752 |
| From | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[4] |
| To | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R47C52[2][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[4]/CLK |
| 2.836 | 0.202 | tC2Q | RR | 3 | R47C52[2][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[4]/Q |
| 3.221 | 0.385 | tNET | RR | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/ADA7 |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/CLKA |
| 2.634 | 0.000 | tUnc | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 | |||
| 2.752 | 0.118 | tHld | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.385, 65.578%; tC2Q: 0.202, 34.422% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path12
Path Summary:
| Slack | 0.496 |
| Data Arrival Time | 3.248 |
| Data Required Time | 2.752 |
| From | u_RAM_based_shift_reg/u_RAM_based_shift_reg/rbin_num_Z[5] |
| To | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R46C48[2][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/rbin_num_Z[5]/CLK |
| 2.836 | 0.202 | tC2Q | RR | 3 | R46C48[2][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/rbin_num_Z[5]/Q |
| 3.248 | 0.412 | tNET | RR | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/ADB8 |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/CLKB |
| 2.634 | 0.000 | tUnc | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 | |||
| 2.752 | 0.118 | tHld | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.412, 67.100%; tC2Q: 0.202, 32.900% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path13
Path Summary:
| Slack | 0.496 |
| Data Arrival Time | 3.248 |
| Data Required Time | 2.752 |
| From | u_RAM_based_shift_reg/u_RAM_based_shift_reg/rbin_num_Z[6] |
| To | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R46C48[2][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/rbin_num_Z[6]/CLK |
| 2.836 | 0.202 | tC2Q | RR | 3 | R46C48[2][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/rbin_num_Z[6]/Q |
| 3.248 | 0.412 | tNET | RR | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/ADB9 |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/CLKB |
| 2.634 | 0.000 | tUnc | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 | |||
| 2.752 | 0.118 | tHld | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.412, 67.103%; tC2Q: 0.202, 32.897% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path14
Path Summary:
| Slack | 0.496 |
| Data Arrival Time | 3.248 |
| Data Required Time | 2.752 |
| From | u_RAM_based_shift_reg/u_RAM_based_shift_reg/rbin_num_Z[2] |
| To | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R46C48[0][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/rbin_num_Z[2]/CLK |
| 2.836 | 0.202 | tC2Q | RR | 3 | R46C48[0][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/rbin_num_Z[2]/Q |
| 3.248 | 0.412 | tNET | RR | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/ADB5 |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/CLKB |
| 2.634 | 0.000 | tUnc | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 | |||
| 2.752 | 0.118 | tHld | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.412, 67.103%; tC2Q: 0.202, 32.897% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path15
Path Summary:
| Slack | 0.496 |
| Data Arrival Time | 3.248 |
| Data Required Time | 2.752 |
| From | u_RAM_based_shift_reg/u_RAM_based_shift_reg/rbin_num_Z[0] |
| To | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R47C48[0][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/rbin_num_Z[0]/CLK |
| 2.836 | 0.202 | tC2Q | RR | 3 | R47C48[0][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/rbin_num_Z[0]/Q |
| 3.248 | 0.412 | tNET | RR | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/ADB3 |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/CLKB |
| 2.634 | 0.000 | tUnc | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 | |||
| 2.752 | 0.118 | tHld | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.412, 67.106%; tC2Q: 0.202, 32.894% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path16
Path Summary:
| Slack | 0.511 |
| Data Arrival Time | 3.263 |
| Data Required Time | 2.752 |
| From | u_RAM_based_shift_reg/u_RAM_based_shift_reg/rbin_num_Z[1] |
| To | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R46C47[1][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/rbin_num_Z[1]/CLK |
| 2.836 | 0.202 | tC2Q | RR | 6 | R46C47[1][A] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/rbin_num_Z[1]/Q |
| 3.263 | 0.427 | tNET | RR | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/ADB4 |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0/CLKB |
| 2.634 | 0.000 | tUnc | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 | |||
| 2.752 | 0.118 | tHld | 1 | BSRAM_R45[15] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/mem_mem_0_0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.427, 67.898%; tC2Q: 0.202, 32.102% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path17
Path Summary:
| Slack | 0.546 |
| Data Arrival Time | 3.190 |
| Data Required Time | 2.645 |
| From | ADDR[0] |
| To | ADDR[0] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R47C38[0][B] | ADDR[0]/CLK |
| 2.835 | 0.201 | tC2Q | RF | 9 | R47C38[0][B] | ADDR[0]/Q |
| 2.958 | 0.124 | tNET | FF | 2 | R47C38[0][B] | ADDR_3_cry_0_0/I1 |
| 3.190 | 0.232 | tINS | FF | 1 | R47C38[0][B] | ADDR_3_cry_0_0/SUM |
| 3.190 | 0.000 | tNET | FF | 1 | R47C38[0][B] | ADDR[0]/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R47C38[0][B] | ADDR[0]/CLK |
| 2.634 | 0.000 | tUnc | ADDR[0] | |||
| 2.645 | 0.011 | tHld | 1 | R47C38[0][B] | ADDR[0] |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
| Arrival Data Path Delay | cell: 0.232, 41.687%; route: 0.124, 22.197%; tC2Q: 0.201, 36.117% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path18
Path Summary:
| Slack | 0.557 |
| Data Arrival Time | 3.202 |
| Data Required Time | 2.645 |
| From | cnt_Z[0] |
| To | cnt_Z[0] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R46C37[0][B] | cnt_Z[0]/CLK |
| 2.836 | 0.202 | tC2Q | RR | 2 | R46C37[0][B] | cnt_Z[0]/Q |
| 2.838 | 0.002 | tNET | RR | 2 | R46C37[0][B] | un5_cnt_cry_0_0/I0 |
| 3.202 | 0.364 | tINS | RF | 1 | R46C37[0][B] | un5_cnt_cry_0_0/SUM |
| 3.202 | 0.000 | tNET | FF | 1 | R46C37[0][B] | cnt_Z[0]/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R46C37[0][B] | cnt_Z[0]/CLK |
| 2.634 | 0.000 | tUnc | cnt_Z[0] | |||
| 2.645 | 0.011 | tHld | 1 | R46C37[0][B] | cnt_Z[0] |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
| Arrival Data Path Delay | cell: 0.364, 64.034%; route: 0.002, 0.430%; tC2Q: 0.202, 35.536% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path19
Path Summary:
| Slack | 0.557 |
| Data Arrival Time | 3.202 |
| Data Required Time | 2.645 |
| From | Din_Z[0] |
| To | Din_Z[0] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R47C42[0][B] | Din_Z[0]/CLK |
| 2.836 | 0.202 | tC2Q | RR | 3 | R47C42[0][B] | Din_Z[0]/Q |
| 2.838 | 0.002 | tNET | RR | 2 | R47C42[0][B] | Din_cry_0[0]/I0 |
| 3.202 | 0.364 | tINS | RF | 1 | R47C42[0][B] | Din_cry_0[0]/SUM |
| 3.202 | 0.000 | tNET | FF | 1 | R47C42[0][B] | Din_Z[0]/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R47C42[0][B] | Din_Z[0]/CLK |
| 2.634 | 0.000 | tUnc | Din_Z[0] | |||
| 2.645 | 0.011 | tHld | 1 | R47C42[0][B] | Din_Z[0] |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
| Arrival Data Path Delay | cell: 0.364, 64.034%; route: 0.002, 0.430%; tC2Q: 0.202, 35.536% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path20
Path Summary:
| Slack | 0.557 |
| Data Arrival Time | 3.202 |
| Data Required Time | 2.645 |
| From | Din_Z[2] |
| To | Din_Z[2] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R47C42[1][B] | Din_Z[2]/CLK |
| 2.836 | 0.202 | tC2Q | RR | 3 | R47C42[1][B] | Din_Z[2]/Q |
| 2.838 | 0.002 | tNET | RR | 2 | R47C42[1][B] | Din_cry_0[2]/I0 |
| 3.202 | 0.364 | tINS | RF | 1 | R47C42[1][B] | Din_cry_0[2]/SUM |
| 3.202 | 0.000 | tNET | FF | 1 | R47C42[1][B] | Din_Z[2]/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R47C42[1][B] | Din_Z[2]/CLK |
| 2.634 | 0.000 | tUnc | Din_Z[2] | |||
| 2.645 | 0.011 | tHld | 1 | R47C42[1][B] | Din_Z[2] |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
| Arrival Data Path Delay | cell: 0.364, 64.034%; route: 0.002, 0.430%; tC2Q: 0.202, 35.536% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path21
Path Summary:
| Slack | 0.557 |
| Data Arrival Time | 3.202 |
| Data Required Time | 2.645 |
| From | Din_Z[6] |
| To | Din_Z[6] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R47C43[0][B] | Din_Z[6]/CLK |
| 2.836 | 0.202 | tC2Q | RR | 3 | R47C43[0][B] | Din_Z[6]/Q |
| 2.838 | 0.002 | tNET | RR | 2 | R47C43[0][B] | Din_cry_0[6]/I0 |
| 3.202 | 0.364 | tINS | RF | 1 | R47C43[0][B] | Din_cry_0[6]/SUM |
| 3.202 | 0.000 | tNET | FF | 1 | R47C43[0][B] | Din_Z[6]/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R47C43[0][B] | Din_Z[6]/CLK |
| 2.634 | 0.000 | tUnc | Din_Z[6] | |||
| 2.645 | 0.011 | tHld | 1 | R47C43[0][B] | Din_Z[6] |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
| Arrival Data Path Delay | cell: 0.364, 64.034%; route: 0.002, 0.430%; tC2Q: 0.202, 35.536% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path22
Path Summary:
| Slack | 0.559 |
| Data Arrival Time | 3.203 |
| Data Required Time | 2.645 |
| From | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[6] |
| To | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[6] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R47C53[0][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[6]/CLK |
| 2.836 | 0.202 | tC2Q | RR | 3 | R47C53[0][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[6]/Q |
| 2.839 | 0.004 | tNET | RR | 2 | R47C53[0][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_cry_0[6]/I0 |
| 3.203 | 0.364 | tINS | RF | 1 | R47C53[0][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_cry_0[6]/SUM |
| 3.203 | 0.000 | tNET | FF | 1 | R47C53[0][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[6]/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R47C53[0][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[6]/CLK |
| 2.634 | 0.000 | tUnc | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[6] | |||
| 2.645 | 0.011 | tHld | 1 | R47C53[0][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[6] |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
| Arrival Data Path Delay | cell: 0.364, 63.897%; route: 0.004, 0.644%; tC2Q: 0.202, 35.459% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path23
Path Summary:
| Slack | 0.559 |
| Data Arrival Time | 3.203 |
| Data Required Time | 2.645 |
| From | ADDR_Z[6] |
| To | ADDR_Z[6] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R47C39[0][B] | ADDR_Z[6]/CLK |
| 2.836 | 0.202 | tC2Q | RR | 10 | R47C39[0][B] | ADDR_Z[6]/Q |
| 2.839 | 0.004 | tNET | RR | 2 | R47C39[0][B] | ADDR_3_cry_6_0/I0 |
| 3.203 | 0.364 | tINS | RF | 1 | R47C39[0][B] | ADDR_3_cry_6_0/SUM |
| 3.203 | 0.000 | tNET | FF | 1 | R47C39[0][B] | ADDR_Z[6]/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R47C39[0][B] | ADDR_Z[6]/CLK |
| 2.634 | 0.000 | tUnc | ADDR_Z[6] | |||
| 2.645 | 0.011 | tHld | 1 | R47C39[0][B] | ADDR_Z[6] |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
| Arrival Data Path Delay | cell: 0.364, 63.897%; route: 0.004, 0.644%; tC2Q: 0.202, 35.459% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path24
Path Summary:
| Slack | 0.559 |
| Data Arrival Time | 3.203 |
| Data Required Time | 2.645 |
| From | ADDR_Z[8] |
| To | ADDR_Z[8] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R47C39[1][B] | ADDR_Z[8]/CLK |
| 2.836 | 0.202 | tC2Q | RR | 13 | R47C39[1][B] | ADDR_Z[8]/Q |
| 2.839 | 0.004 | tNET | RR | 2 | R47C39[1][B] | ADDR_3_s_8_0/I0 |
| 3.203 | 0.364 | tINS | RF | 1 | R47C39[1][B] | ADDR_3_s_8_0/SUM |
| 3.203 | 0.000 | tNET | FF | 1 | R47C39[1][B] | ADDR_Z[8]/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R47C39[1][B] | ADDR_Z[8]/CLK |
| 2.634 | 0.000 | tUnc | ADDR_Z[8] | |||
| 2.645 | 0.011 | tHld | 1 | R47C39[1][B] | ADDR_Z[8] |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
| Arrival Data Path Delay | cell: 0.364, 63.897%; route: 0.004, 0.644%; tC2Q: 0.202, 35.459% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path25
Path Summary:
| Slack | 0.559 |
| Data Arrival Time | 3.203 |
| Data Required Time | 2.645 |
| From | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[0] |
| To | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[0] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R47C52[0][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[0]/CLK |
| 2.836 | 0.202 | tC2Q | RR | 3 | R47C52[0][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[0]/Q |
| 2.839 | 0.004 | tNET | RR | 2 | R47C52[0][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_cry_0[0]/I0 |
| 3.203 | 0.364 | tINS | RF | 1 | R47C52[0][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_cry_0[0]/SUM |
| 3.203 | 0.000 | tNET | FF | 1 | R47C52[0][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[0]/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R47C52[0][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[0]/CLK |
| 2.634 | 0.000 | tUnc | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[0] | |||
| 2.645 | 0.011 | tHld | 1 | R47C52[0][B] | u_RAM_based_shift_reg/u_RAM_based_shift_reg/wbin_Z[0] |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 1 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
| Arrival Data Path Delay | cell: 0.364, 63.897%; route: 0.004, 0.644%; tC2Q: 0.202, 35.459% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R9C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R9C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z | |||
| 8.253 | -0.035 | tSu | 1 | R9C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path2
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/genblk1.u_ao_match_0/match_sep |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R8C7[2][A] | u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R8C7[2][A] | u_la0_top/genblk1.u_ao_match_0/match_sep/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/genblk1.u_ao_match_0/match_sep | |||
| 8.253 | -0.035 | tSu | 1 | R8C7[2][A] | u_la0_top/genblk1.u_ao_match_0/match_sep |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path3
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R5C11[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R5C11[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0] | |||
| 8.253 | -0.035 | tSu | 1 | R5C11[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0] |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path4
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R5C3[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R5C3[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8] | |||
| 8.253 | -0.035 | tSu | 1 | R5C3[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8] |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path5
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R11C10[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R11C10[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2] | |||
| 8.253 | -0.035 | tSu | 1 | R11C10[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2] |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path6
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_loop_Z |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R9C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R9C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_loop_Z | |||
| 8.253 | -0.035 | tSu | 1 | R9C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_Z |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path7
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/trigger_seq_start_Z |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R7C10[0][A] | u_la0_top/trigger_seq_start_Z/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R7C10[0][A] | u_la0_top/trigger_seq_start_Z/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/trigger_seq_start_Z | |||
| 8.253 | -0.035 | tSu | 1 | R7C10[0][A] | u_la0_top/trigger_seq_start_Z |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path8
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R8C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R8C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6] | |||
| 8.253 | -0.035 | tSu | 1 | R8C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6] |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path9
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R4C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R4C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9] | |||
| 8.253 | -0.035 | tSu | 1 | R4C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9] |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path10
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R8C9[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R8C9[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5] | |||
| 8.253 | -0.035 | tSu | 1 | R8C9[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5] |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path11
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R5C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R5C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6] | |||
| 8.253 | -0.035 | tSu | 1 | R5C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6] |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path12
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R7C9[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R7C9[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1] | |||
| 8.253 | -0.035 | tSu | 1 | R7C9[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1] |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path13
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R7C9[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R7C9[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0] | |||
| 8.253 | -0.035 | tSu | 1 | R7C9[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0] |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path14
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/capture_window_sel_Z[0] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R12C9[1][A] | u_la0_top/capture_window_sel_Z[0]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R12C9[1][A] | u_la0_top/capture_window_sel_Z[0]/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/capture_window_sel_Z[0] | |||
| 8.253 | -0.035 | tSu | 1 | R12C9[1][A] | u_la0_top/capture_window_sel_Z[0] |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path15
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/capture_window_sel_Z[1] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R12C9[1][B] | u_la0_top/capture_window_sel_Z[1]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R12C9[1][B] | u_la0_top/capture_window_sel_Z[1]/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/capture_window_sel_Z[1] | |||
| 8.253 | -0.035 | tSu | 1 | R12C9[1][B] | u_la0_top/capture_window_sel_Z[1] |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path16
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/capture_window_sel_Z[2] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R2C7[0][A] | u_la0_top/capture_window_sel_Z[2]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R2C7[0][A] | u_la0_top/capture_window_sel_Z[2]/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/capture_window_sel_Z[2] | |||
| 8.253 | -0.035 | tSu | 1 | R2C7[0][A] | u_la0_top/capture_window_sel_Z[2] |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path17
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R11C10[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R11C10[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3] | |||
| 8.253 | -0.035 | tSu | 1 | R11C10[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3] |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path18
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R8C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R8C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7] | |||
| 8.253 | -0.035 | tSu | 1 | R8C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7] |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path19
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R11C10[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R11C10[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4] | |||
| 8.253 | -0.035 | tSu | 1 | R11C10[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4] |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path20
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R9C10[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R9C10[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8] | |||
| 8.253 | -0.035 | tSu | 1 | R9C10[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8] |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path21
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/internal_reg_start_syn_Z[1] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R9C3[2][B] | u_la0_top/internal_reg_start_syn_Z[1]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/internal_reg_start_syn_Z[1]/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/internal_reg_start_syn_Z[1] | |||
| 8.253 | -0.035 | tSu | 1 | R9C3[2][B] | u_la0_top/internal_reg_start_syn_Z[1] |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path22
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/capture_window_sel[3] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R2C7[0][B] | u_la0_top/capture_window_sel[3]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R2C7[0][B] | u_la0_top/capture_window_sel[3]/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/capture_window_sel[3] | |||
| 8.253 | -0.035 | tSu | 1 | R2C7[0][B] | u_la0_top/capture_window_sel[3] |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path23
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R4C2[2][A] | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R4C2[2][A] | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z | |||
| 8.253 | -0.035 | tSu | 1 | R4C2[2][A] | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path24
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R8C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R8C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4] | |||
| 8.253 | -0.035 | tSu | 1 | R8C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4] |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Path25
Path Summary:
| Slack | -0.865 |
| Data Arrival Time | 9.118 |
| Data Required Time | 8.253 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.365 | 0.232 | tC2Q | FF | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 9.118 | 2.752 | tNET | FF | 1 | R9C10[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 5.556 | 5.556 | active clock edge time | ||||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 7.287 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 8.488 | 1.201 | tNET | RR | 1 | R9C10[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLK |
| 8.288 | -0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1] | |||
| 8.253 | -0.035 | tSu | 1 | R9C10[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1] |
Path Statistics:
| Clock Skew | -0.423 |
| Setup Relationship | 2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.228, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 2.752, 92.227%; tC2Q: 0.232, 7.773% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.201, 100.000% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 4.931 |
| Data Arrival Time | 7.776 |
| Data Required Time | 2.845 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 5.818 | 0.913 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.020 | 0.202 | tC2Q | FR | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 7.776 | 1.756 | tNET | RR | 1 | R9C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R9C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK |
| 2.834 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z | |||
| 2.845 | 0.011 | tHld | 1 | R9C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z |
Path Statistics:
| Clock Skew | -0.406 |
| Hold Relationship | -2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path2
Path Summary:
| Slack | 4.931 |
| Data Arrival Time | 7.776 |
| Data Required Time | 2.845 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_loop_Z |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 5.818 | 0.913 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.020 | 0.202 | tC2Q | FR | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 7.776 | 1.756 | tNET | RR | 1 | R9C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R9C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_Z/CLK |
| 2.834 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_loop_Z | |||
| 2.845 | 0.011 | tHld | 1 | R9C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_loop_Z |
Path Statistics:
| Clock Skew | -0.406 |
| Hold Relationship | -2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path3
Path Summary:
| Slack | 4.931 |
| Data Arrival Time | 7.776 |
| Data Required Time | 2.845 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 5.818 | 0.913 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.020 | 0.202 | tC2Q | FR | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 7.776 | 1.756 | tNET | RR | 1 | R11C10[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R11C10[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4]/CLK |
| 2.834 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4] | |||
| 2.845 | 0.011 | tHld | 1 | R11C10[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[4] |
Path Statistics:
| Clock Skew | -0.406 |
| Hold Relationship | -2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path4
Path Summary:
| Slack | 4.931 |
| Data Arrival Time | 7.776 |
| Data Required Time | 2.845 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 5.818 | 0.913 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.020 | 0.202 | tC2Q | FR | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 7.776 | 1.756 | tNET | RR | 1 | R4C2[2][A] | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R4C2[2][A] | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z/CLK |
| 2.834 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z | |||
| 2.845 | 0.011 | tHld | 1 | R4C2[2][A] | u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_Z |
Path Statistics:
| Clock Skew | -0.406 |
| Hold Relationship | -2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path5
Path Summary:
| Slack | 4.931 |
| Data Arrival Time | 7.776 |
| Data Required Time | 2.845 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 5.818 | 0.913 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.020 | 0.202 | tC2Q | FR | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 7.776 | 1.756 | tNET | RR | 1 | R5C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R5C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6]/CLK |
| 2.834 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6] | |||
| 2.845 | 0.011 | tHld | 1 | R5C2[2][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[6] |
Path Statistics:
| Clock Skew | -0.406 |
| Hold Relationship | -2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path6
Path Summary:
| Slack | 4.931 |
| Data Arrival Time | 7.776 |
| Data Required Time | 2.845 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 5.818 | 0.913 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.020 | 0.202 | tC2Q | FR | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 7.776 | 1.756 | tNET | RR | 1 | R8C9[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R8C9[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5]/CLK |
| 2.834 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5] | |||
| 2.845 | 0.011 | tHld | 1 | R8C9[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[5] |
Path Statistics:
| Clock Skew | -0.406 |
| Hold Relationship | -2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path7
Path Summary:
| Slack | 4.931 |
| Data Arrival Time | 7.776 |
| Data Required Time | 2.845 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 5.818 | 0.913 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.020 | 0.202 | tC2Q | FR | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 7.776 | 1.756 | tNET | RR | 1 | R9C10[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R9C10[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8]/CLK |
| 2.834 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8] | |||
| 2.845 | 0.011 | tHld | 1 | R9C10[0][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[8] |
Path Statistics:
| Clock Skew | -0.406 |
| Hold Relationship | -2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path8
Path Summary:
| Slack | 4.931 |
| Data Arrival Time | 7.776 |
| Data Required Time | 2.845 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 5.818 | 0.913 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.020 | 0.202 | tC2Q | FR | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 7.776 | 1.756 | tNET | RR | 1 | R4C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R4C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9]/CLK |
| 2.834 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9] | |||
| 2.845 | 0.011 | tHld | 1 | R4C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[9] |
Path Statistics:
| Clock Skew | -0.406 |
| Hold Relationship | -2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path9
Path Summary:
| Slack | 4.931 |
| Data Arrival Time | 7.776 |
| Data Required Time | 2.845 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 5.818 | 0.913 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.020 | 0.202 | tC2Q | FR | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 7.776 | 1.756 | tNET | RR | 1 | R7C10[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R7C10[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7]/CLK |
| 2.834 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7] | |||
| 2.845 | 0.011 | tHld | 1 | R7C10[1][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[7] |
Path Statistics:
| Clock Skew | -0.406 |
| Hold Relationship | -2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path10
Path Summary:
| Slack | 4.931 |
| Data Arrival Time | 7.776 |
| Data Required Time | 2.845 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 5.818 | 0.913 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.020 | 0.202 | tC2Q | FR | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 7.776 | 1.756 | tNET | RR | 1 | R9C10[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R9C10[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1]/CLK |
| 2.834 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1] | |||
| 2.845 | 0.011 | tHld | 1 | R9C10[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[1] |
Path Statistics:
| Clock Skew | -0.406 |
| Hold Relationship | -2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path11
Path Summary:
| Slack | 4.931 |
| Data Arrival Time | 7.776 |
| Data Required Time | 2.845 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 5.818 | 0.913 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.020 | 0.202 | tC2Q | FR | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 7.776 | 1.756 | tNET | RR | 1 | R5C11[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R5C11[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0]/CLK |
| 2.834 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0] | |||
| 2.845 | 0.011 | tHld | 1 | R5C11[2][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[0] |
Path Statistics:
| Clock Skew | -0.406 |
| Hold Relationship | -2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path12
Path Summary:
| Slack | 4.931 |
| Data Arrival Time | 7.776 |
| Data Required Time | 2.845 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 5.818 | 0.913 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.020 | 0.202 | tC2Q | FR | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 7.776 | 1.756 | tNET | RR | 1 | R11C10[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/PRESET |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R11C10[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3]/CLK |
| 2.834 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3] | |||
| 2.845 | 0.011 | tHld | 1 | R11C10[0][B] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[3] |
Path Statistics:
| Clock Skew | -0.406 |
| Hold Relationship | -2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path13
Path Summary:
| Slack | 4.931 |
| Data Arrival Time | 7.776 |
| Data Required Time | 2.845 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 5.818 | 0.913 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.020 | 0.202 | tC2Q | FR | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 7.776 | 1.756 | tNET | RR | 1 | R7C9[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R7C9[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0]/CLK |
| 2.834 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0] | |||
| 2.845 | 0.011 | tHld | 1 | R7C9[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[0] |
Path Statistics:
| Clock Skew | -0.406 |
| Hold Relationship | -2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path14
Path Summary:
| Slack | 4.931 |
| Data Arrival Time | 7.776 |
| Data Required Time | 2.845 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 5.818 | 0.913 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.020 | 0.202 | tC2Q | FR | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 7.776 | 1.756 | tNET | RR | 1 | R11C10[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R11C10[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2]/CLK |
| 2.834 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2] | |||
| 2.845 | 0.011 | tHld | 1 | R11C10[1][A] | u_la0_top/u_ao_mem_ctrl/capture_length_Z[2] |
Path Statistics:
| Clock Skew | -0.406 |
| Hold Relationship | -2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path15
Path Summary:
| Slack | 4.931 |
| Data Arrival Time | 7.776 |
| Data Required Time | 2.845 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 5.818 | 0.913 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.020 | 0.202 | tC2Q | FR | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 7.776 | 1.756 | tNET | RR | 1 | R7C9[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R7C9[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2]/CLK |
| 2.834 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2] | |||
| 2.845 | 0.011 | tHld | 1 | R7C9[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[2] |
Path Statistics:
| Clock Skew | -0.406 |
| Hold Relationship | -2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path16
Path Summary:
| Slack | 4.931 |
| Data Arrival Time | 7.776 |
| Data Required Time | 2.845 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 5.818 | 0.913 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.020 | 0.202 | tC2Q | FR | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 7.776 | 1.756 | tNET | RR | 1 | R7C9[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R7C9[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1]/CLK |
| 2.834 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1] | |||
| 2.845 | 0.011 | tHld | 1 | R7C9[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[1] |
Path Statistics:
| Clock Skew | -0.406 |
| Hold Relationship | -2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path17
Path Summary:
| Slack | 4.931 |
| Data Arrival Time | 7.776 |
| Data Required Time | 2.845 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 5.818 | 0.913 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.020 | 0.202 | tC2Q | FR | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 7.776 | 1.756 | tNET | RR | 1 | R8C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R8C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4]/CLK |
| 2.834 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4] | |||
| 2.845 | 0.011 | tHld | 1 | R8C2[0][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[4] |
Path Statistics:
| Clock Skew | -0.406 |
| Hold Relationship | -2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path18
Path Summary:
| Slack | 4.931 |
| Data Arrival Time | 7.776 |
| Data Required Time | 2.845 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 5.818 | 0.913 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.020 | 0.202 | tC2Q | FR | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 7.776 | 1.756 | tNET | RR | 1 | R8C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R8C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5]/CLK |
| 2.834 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5] | |||
| 2.845 | 0.011 | tHld | 1 | R8C2[1][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[5] |
Path Statistics:
| Clock Skew | -0.406 |
| Hold Relationship | -2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path19
Path Summary:
| Slack | 4.931 |
| Data Arrival Time | 7.776 |
| Data Required Time | 2.845 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 5.818 | 0.913 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.020 | 0.202 | tC2Q | FR | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 7.776 | 1.756 | tNET | RR | 1 | R8C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R8C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3]/CLK |
| 2.834 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3] | |||
| 2.845 | 0.011 | tHld | 1 | R8C2[0][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[3] |
Path Statistics:
| Clock Skew | -0.406 |
| Hold Relationship | -2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path20
Path Summary:
| Slack | 4.931 |
| Data Arrival Time | 7.776 |
| Data Required Time | 2.845 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 5.818 | 0.913 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.020 | 0.202 | tC2Q | FR | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 7.776 | 1.756 | tNET | RR | 1 | R8C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R8C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7]/CLK |
| 2.834 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7] | |||
| 2.845 | 0.011 | tHld | 1 | R8C2[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[7] |
Path Statistics:
| Clock Skew | -0.406 |
| Hold Relationship | -2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path21
Path Summary:
| Slack | 4.931 |
| Data Arrival Time | 7.776 |
| Data Required Time | 2.845 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 5.818 | 0.913 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.020 | 0.202 | tC2Q | FR | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 7.776 | 1.756 | tNET | RR | 1 | R8C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R8C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6]/CLK |
| 2.834 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6] | |||
| 2.845 | 0.011 | tHld | 1 | R8C2[1][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[6] |
Path Statistics:
| Clock Skew | -0.406 |
| Hold Relationship | -2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path22
Path Summary:
| Slack | 4.931 |
| Data Arrival Time | 7.776 |
| Data Required Time | 2.845 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 5.818 | 0.913 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.020 | 0.202 | tC2Q | FR | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 7.776 | 1.756 | tNET | RR | 1 | R5C3[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R5C3[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9]/CLK |
| 2.834 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9] | |||
| 2.845 | 0.011 | tHld | 1 | R5C3[2][B] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[9] |
Path Statistics:
| Clock Skew | -0.406 |
| Hold Relationship | -2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path23
Path Summary:
| Slack | 4.931 |
| Data Arrival Time | 7.776 |
| Data Required Time | 2.845 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/genblk1.u_ao_match_0/match_sep |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 5.818 | 0.913 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.020 | 0.202 | tC2Q | FR | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 7.776 | 1.756 | tNET | RR | 1 | R8C7[2][A] | u_la0_top/genblk1.u_ao_match_0/match_sep/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R8C7[2][A] | u_la0_top/genblk1.u_ao_match_0/match_sep/CLK |
| 2.834 | 0.200 | tUnc | u_la0_top/genblk1.u_ao_match_0/match_sep | |||
| 2.845 | 0.011 | tHld | 1 | R8C7[2][A] | u_la0_top/genblk1.u_ao_match_0/match_sep |
Path Statistics:
| Clock Skew | -0.406 |
| Hold Relationship | -2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path24
Path Summary:
| Slack | 4.931 |
| Data Arrival Time | 7.776 |
| Data Required Time | 2.845 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 5.818 | 0.913 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.020 | 0.202 | tC2Q | FR | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 7.776 | 1.756 | tNET | RR | 1 | R5C3[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R5C3[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8]/CLK |
| 2.834 | 0.200 | tUnc | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8] | |||
| 2.845 | 0.011 | tHld | 1 | R5C3[2][A] | u_la0_top/u_ao_mem_ctrl/capture_mem_addr_Z[8] |
Path Statistics:
| Clock Skew | -0.406 |
| Hold Relationship | -2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Path25
Path Summary:
| Slack | 4.931 |
| Data Arrival Time | 7.776 |
| Data Required Time | 2.845 |
| From | u_la0_top/rst_ao_Z |
| To | u_la0_top/internal_reg_start_syn_Z[1] |
| Launch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[F] |
| Latch Clk | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 2.778 | 2.778 | active clock edge time | ||||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 4.905 | 2.127 | tCL | FF | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 5.818 | 0.913 | tNET | FF | 1 | R7C10[2][A] | u_la0_top/rst_ao_Z/CLK |
| 6.020 | 0.202 | tC2Q | FR | 43 | R7C10[2][A] | u_la0_top/rst_ao_Z/Q |
| 7.776 | 1.756 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/internal_reg_start_syn_Z[1]/CLEAR |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||||
| 1.732 | 1.732 | tCL | RR | 127 | PLL_L[0] | GW_PLL_inst/pll_inst/CLKOUT |
| 2.634 | 0.902 | tNET | RR | 1 | R9C3[2][B] | u_la0_top/internal_reg_start_syn_Z[1]/CLK |
| 2.834 | 0.200 | tUnc | u_la0_top/internal_reg_start_syn_Z[1] | |||
| 2.845 | 0.011 | tHld | 1 | R9C3[2][B] | u_la0_top/internal_reg_start_syn_Z[1] |
Path Statistics:
| Clock Skew | -0.406 |
| Hold Relationship | -2.778 |
| Logic Level | 0 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.913, 100.000% |
| Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.756, 89.683%; tC2Q: 0.202, 10.317% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.902, 100.000% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
| Slack: | 1.056 |
| Actual Width: | 2.056 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk |
| Objects: | Din_Z[7] |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 2.778 | 0.000 | active clock edge time | ||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||
| 4.905 | 2.127 | tCL | FF | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | Din_Z[7]/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 5.556 | 0.000 | active clock edge time | ||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||
| 7.287 | 1.732 | tCL | RR | GW_PLL_inst/pll_inst/CLKOUT |
| 8.189 | 0.902 | tNET | RR | Din_Z[7]/CLK |
MPW2
MPW Summary:
| Slack: | 1.056 |
| Actual Width: | 2.056 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk |
| Objects: | Din_Z[5] |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 2.778 | 0.000 | active clock edge time | ||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||
| 4.905 | 2.127 | tCL | FF | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | Din_Z[5]/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 5.556 | 0.000 | active clock edge time | ||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||
| 7.287 | 1.732 | tCL | RR | GW_PLL_inst/pll_inst/CLKOUT |
| 8.189 | 0.902 | tNET | RR | Din_Z[5]/CLK |
MPW3
MPW Summary:
| Slack: | 1.056 |
| Actual Width: | 2.056 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk |
| Objects: | Din_Z[1] |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 2.778 | 0.000 | active clock edge time | ||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||
| 4.905 | 2.127 | tCL | FF | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | Din_Z[1]/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 5.556 | 0.000 | active clock edge time | ||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||
| 7.287 | 1.732 | tCL | RR | GW_PLL_inst/pll_inst/CLKOUT |
| 8.189 | 0.902 | tNET | RR | Din_Z[1]/CLK |
MPW4
MPW Summary:
| Slack: | 1.056 |
| Actual Width: | 2.056 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk |
| Objects: | cnt_Z[0] |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 2.778 | 0.000 | active clock edge time | ||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||
| 4.905 | 2.127 | tCL | FF | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | cnt_Z[0]/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 5.556 | 0.000 | active clock edge time | ||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||
| 7.287 | 1.732 | tCL | RR | GW_PLL_inst/pll_inst/CLKOUT |
| 8.189 | 0.902 | tNET | RR | cnt_Z[0]/CLK |
MPW5
MPW Summary:
| Slack: | 1.056 |
| Actual Width: | 2.056 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk |
| Objects: | u_RAM_based_shift_reg/u_RAM_based_shift_reg/rbin_num_Z[0] |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 2.778 | 0.000 | active clock edge time | ||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||
| 4.905 | 2.127 | tCL | FF | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | u_RAM_based_shift_reg/u_RAM_based_shift_reg/rbin_num_Z[0]/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 5.556 | 0.000 | active clock edge time | ||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||
| 7.287 | 1.732 | tCL | RR | GW_PLL_inst/pll_inst/CLKOUT |
| 8.189 | 0.902 | tNET | RR | u_RAM_based_shift_reg/u_RAM_based_shift_reg/rbin_num_Z[0]/CLK |
MPW6
MPW Summary:
| Slack: | 1.056 |
| Actual Width: | 2.056 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk |
| Objects: | u_la0_top/triger_level_cnt_Z[0] |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 2.778 | 0.000 | active clock edge time | ||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||
| 4.905 | 2.127 | tCL | FF | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | u_la0_top/triger_level_cnt_Z[0]/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 5.556 | 0.000 | active clock edge time | ||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||
| 7.287 | 1.732 | tCL | RR | GW_PLL_inst/pll_inst/CLKOUT |
| 8.189 | 0.902 | tNET | RR | u_la0_top/triger_level_cnt_Z[0]/CLK |
MPW7
MPW Summary:
| Slack: | 1.056 |
| Actual Width: | 2.056 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk |
| Objects: | u_la0_top/u_ao_mem_ctrl/mem_mem_0_1 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 2.778 | 0.000 | active clock edge time | ||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||
| 4.905 | 2.127 | tCL | FF | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | u_la0_top/u_ao_mem_ctrl/mem_mem_0_1/CLKA |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 5.556 | 0.000 | active clock edge time | ||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||
| 7.287 | 1.732 | tCL | RR | GW_PLL_inst/pll_inst/CLKOUT |
| 8.189 | 0.902 | tNET | RR | u_la0_top/u_ao_mem_ctrl/mem_mem_0_1/CLKA |
MPW8
MPW Summary:
| Slack: | 1.056 |
| Actual Width: | 2.056 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk |
| Objects: | u_la0_top/u_ao_mem_ctrl/mem_mem_0_0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 2.778 | 0.000 | active clock edge time | ||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||
| 4.905 | 2.127 | tCL | FF | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | u_la0_top/u_ao_mem_ctrl/mem_mem_0_0/CLKA |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 5.556 | 0.000 | active clock edge time | ||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||
| 7.287 | 1.732 | tCL | RR | GW_PLL_inst/pll_inst/CLKOUT |
| 8.189 | 0.902 | tNET | RR | u_la0_top/u_ao_mem_ctrl/mem_mem_0_0/CLKA |
MPW9
MPW Summary:
| Slack: | 1.056 |
| Actual Width: | 2.056 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk |
| Objects: | u_la0_top/triger_level_cnt_Z[1] |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 2.778 | 0.000 | active clock edge time | ||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||
| 4.905 | 2.127 | tCL | FF | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | u_la0_top/triger_level_cnt_Z[1]/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 5.556 | 0.000 | active clock edge time | ||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||
| 7.287 | 1.732 | tCL | RR | GW_PLL_inst/pll_inst/CLKOUT |
| 8.189 | 0.902 | tNET | RR | u_la0_top/triger_level_cnt_Z[1]/CLK |
MPW10
MPW Summary:
| Slack: | 1.056 |
| Actual Width: | 2.056 |
| Required Width: | 1.000 |
| Type: | Low Pulse Width |
| Clock: | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk |
| Objects: | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 2.778 | 0.000 | active clock edge time | ||
| 2.778 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||
| 4.905 | 2.127 | tCL | FF | GW_PLL_inst/pll_inst/CLKOUT |
| 6.133 | 1.228 | tNET | FF | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 5.556 | 0.000 | active clock edge time | ||
| 5.556 | 0.000 | GW_PLL_inst/pll_inst/CLKOUT.default_gen_clk(shadow) | ||
| 7.287 | 1.732 | tCL | RR | GW_PLL_inst/pll_inst/CLKOUT |
| 8.189 | 0.902 | tNET | RR | u_la0_top/u_ao_mem_ctrl/capture_mem_wr_Z/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
| FANOUT | NET NAME | WORST SLACK | MAX DELAY |
|---|---|---|---|
| 58 | clk | -0.679 | 1.228 |
| 22 | rbin_num13 | -0.613 | 0.728 |
| 18 | addr_ch_N_7_mux | -0.679 | 0.697 |
| 8 | cnt12_4 | 1.713 | 0.422 |
| 8 | cnt12_5 | 1.259 | 0.433 |
| 8 | cnt12_6 | 1.611 | 0.445 |
| 7 | ADDR[8] | -0.679 | 0.679 |
| 7 | ADDR[1] | -0.533 | 0.827 |
| 7 | ADDR[3] | -0.612 | 1.054 |
| 6 | wbin[1] | 1.993 | 0.707 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
| GRID LOC | ROUTE CONGESTIONS |
|---|---|
| R46C48 | 0.458 |
| R46C49 | 0.347 |
| R47C48 | 0.306 |
| R47C44 | 0.264 |
| R46C37 | 0.250 |
| R47C52 | 0.250 |
| R47C38 | 0.250 |
| R47C39 | 0.250 |
| R46C39 | 0.236 |
| R47C45 | 0.236 |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
| SDC Command Type | State | Detail Command |
|---|