#Build: Synplify Pro (R) O-2018.09G-Beta1, Build 019R, Sep 3 2018 #install: D:\Gowin\1.8\SynplifyPro #OS: Windows 7 6.1 #Hostname: GW-SW-042 # Wed Sep 19 08:39:49 2018 #Implementation: rev_1 Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta1 Install: D:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-042 Implementation : rev_1 Synopsys HDL Compiler, Version comp2018q3p1, Build 019R, Built Sep 3 2018 10:06:59 @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta1 Install: D:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-042 Implementation : rev_1 Synopsys Verilog Compiler, Version comp2018q3p1, Build 019R, Built Sep 3 2018 10:06:59 @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @N:CG1350 : | Running Verilog Compiler in Multiple File Compilation Unit mode @I::"D:\Gowin\1.8\SynplifyPro\lib\generic\gw2a.v" (library work) @I::"D:\Gowin\1.8\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"D:\Gowin\1.8\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"D:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"D:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Fixed_ex\project\impl\temp\gao\ao_0\gw_ao_parameter.v" (library work) @I::"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Fixed_ex\project\impl\temp\gao\ao_0\gw_ao_top_define.v" (library work) @I::"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Fixed_ex\project\impl\temp\gao\ao_0\gw_ao_expression.v" (library work) @I::"D:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v" (library work) @I::"D:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_define.v" (library work) @I::"D:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v" (library work) @W:CG1337 : gw_ao_match.v(109) | Net match_m0_en_reg_wr is not declared. @W:CG1337 : gw_ao_match.v(110) | Net match_m1_en_reg_wr is not declared. @W:CG1337 : gw_ao_match.v(111) | Net match_m2_en_reg_wr is not declared. @W:CG1337 : gw_ao_match.v(112) | Net match_ctl_en_reg_wr is not declared. @W:CG1337 : gw_ao_match.v(113) | Net match_cnt_reg_wr is not declared. @I::"D:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v" (library work) @W:CG1337 : gw_ao_mem_ctrl.v(122) | Net capture_length_zero is not declared. @I::"D:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v" (library work) @W:CG1337 : gw_ao_top.v(500) | Net start_reg_wr is not declared. @W:CG1337 : gw_ao_top.v(503) | Net trig_level_max_reg_wr is not declared. @W:CG1337 : gw_ao_top.v(504) | Net capture_mem_addr_max_wr is not declared. @W:CG1337 : gw_ao_top.v(505) | Net capture_mem_addr_rem_wr is not declared. @W:CG1337 : gw_ao_top.v(506) | Net capture_windows_num_wr is not declared. @W:CG1337 : gw_ao_top.v(1717) | Net match_en_0 is not declared. @W:CG1337 : gw_ao_top.v(1718) | Net match_en_1 is not declared. @W:CG1337 : gw_ao_top.v(1719) | Net match_en_2 is not declared. @W:CG1337 : gw_ao_top.v(1720) | Net match_en_3 is not declared. @W:CG1337 : gw_ao_top.v(1721) | Net match_en_4 is not declared. @W:CG1337 : gw_ao_top.v(1722) | Net match_en_5 is not declared. @W:CG1337 : gw_ao_top.v(1723) | Net match_en_6 is not declared. @W:CG1337 : gw_ao_top.v(1724) | Net match_en_7 is not declared. @W:CG1337 : gw_ao_top.v(1725) | Net match_en_8 is not declared. @W:CG1337 : gw_ao_top.v(1726) | Net match_en_9 is not declared. @W:CG1337 : gw_ao_top.v(1727) | Net match_en_10 is not declared. @W:CG1337 : gw_ao_top.v(1728) | Net match_en_11 is not declared. @W:CG1337 : gw_ao_top.v(1729) | Net match_en_12 is not declared. @W:CG1337 : gw_ao_top.v(1730) | Net match_en_13 is not declared. @W:CG1337 : gw_ao_top.v(1731) | Net match_en_14 is not declared. @W:CG1337 : gw_ao_top.v(1732) | Net match_en_15 is not declared. @W:CG1337 : gw_ao_top.v(2213) | Net stop_reg is not declared. Verilog syntax check successful! @N:CG364 : gw_ao_parameter.v(1) | Synthesizing module work_E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Fixed_ex\project\impl\temp\gao\ao_0\gw_ao_parameter.v_unit in library work. Selecting top level module ao_top_0 Running optimization stage 1 on ao_mem_ctrl_0_1024s_17s_10s ....... Running optimization stage 1 on ao_crc32_0 ....... Running optimization stage 1 on ao_match_0_0s_8s_17s_4_1_0_1_2_3_4 ....... Running optimization stage 1 on ao_top_0 ....... Running optimization stage 2 on ao_match_0_0s_8s_17s_4_1_0_1_2_3_4 ....... Running optimization stage 2 on ao_top_0 ....... Extracted state machine for register module_state State machine has 11 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1001 1010 1011 Running optimization stage 2 on ao_crc32_0 ....... Running optimization stage 2 on ao_mem_ctrl_0_1024s_17s_10s ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 79MB peak: 88MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Sep 19 08:39:50 2018 ###########################################################] ###########################################################[ Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta1 Install: D:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-042 Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp2018q3p1, Build 019R, Built Sep 3 2018 10:06:59 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Sep 19 08:39:50 2018 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Sep 19 08:39:50 2018 ###########################################################] ###########################################################[ Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta1 Install: D:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-042 Database state : E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Fixed_ex\project\impl\temp\gao\ao_0\rev_1\synwork\|rev_1 Synopsys Synopsys Netlist Linker, Version comp2018q3p1, Build 019R, Built Sep 3 2018 10:06:59 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Sep 19 08:39:52 2018 ###########################################################] Premap Report # Wed Sep 19 08:39:52 2018 Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta1 Install: D:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-042 Implementation : rev_1 Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1167R, Built Sep 4 2018 10:03:38 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @A:MF827 : | No constraint file specified. @N:MF284 : | Setting synthesis effort to medium for the design Linked File: ao_0_scck.rpt Printing clock summary report in "E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Fixed_ex\project\impl\temp\gao\ao_0\rev_1\ao_0_scck.rpt" file @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) @N:BN133 : | Ignoring syn_hier=hard property on top-level design. Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 103MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB) @N:MF284 : | Setting synthesis effort to medium for the design @N:MH105 : | UMR3 is only supported for HAPS-80. @N:MH105 : | UMR3 is only supported for HAPS-80. Beginning opaque latch detection (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB) Finished opaque latch marking step (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB) Rerun analysis in 0 latches Finished opaque latch detection step 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB) @N:MF974 : | Total number of latches (multibit) processed = 0 @N:MF975 : | Total number of latches (bit blasted) processed = 0 @N:MF976 : | Total number of (multibit) opaque latches found = 0 @N:MF977 : | Total number of (bit blasted) opaque latches found = 0 Finished opaque latch detection (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB) Detailed report for transparent and observable latches in design: Linked File: ao_0_prem_latch_transparency_report.log Encoding state machine module_state[10:0] (in view: work.ao_top_0(verilog)) original code -> new code 0000 -> 00000000001 0001 -> 00000000010 0010 -> 00000000100 0011 -> 00000001000 0100 -> 00000010000 0101 -> 00000100000 0110 -> 00001000000 0111 -> 00010000000 1001 -> 00100000000 1010 -> 01000000000 1011 -> 10000000000 Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB) Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB) Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB) Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB) syn_allowed_resources : blockrams=140 set on top level netlist ao_top_0 Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB) Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load ---------------------------------------------------------------------------------------------------------- 0 - ao_top_0|control[0] 186.5 MHz 5.362 inferred Autoconstr_clkgroup_1 268 0 - ao_top_0|clk_i 237.7 MHz 4.207 inferred Autoconstr_clkgroup_0 75 ========================================================================================================== Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example -------------------------------------------------------------------------------------------------------------------------------------- ao_top_0|control[0] 268 control[0](port) data_register[37:0].C - - ao_top_0|clk_i 75 clk_i(port) internal_reg_force_triger_syn[1:0].C - clk_ao.I[0](keepbuf) ====================================================================================================================================== ICG Latch Removal Summary: Number of ICG latches removed: 0 Number of ICG latches not removed: 0 @S |Clock Optimization Summary #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ 2 non-gated/non-generated clock tree(s) driving 327 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks ============================= Non-Gated/Non-Generated Clocks ============================= Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ------------------------------------------------------------------------------------------ ClockId_0_0 ENCRYPTED Unconstrained_port 59 ENCRYPTED ClockId_0_1 ENCRYPTED Unconstrained_io_port 268 ENCRYPTED ========================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ###### @N:FX1143 : | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Fixed_ex\project\impl\temp\gao\ao_0\rev_1\ao_0.sap. Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 193MB) Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 193MB) None None Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 193MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 107MB peak: 193MB) Process took 0h:00m:02s realtime, 0h:00m:01s cputime # Wed Sep 19 08:39:54 2018 ###########################################################] Map & Optimize Report # Wed Sep 19 08:39:54 2018 Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta1 Install: D:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-042 Implementation : rev_1 Synopsys Generic Technology Mapper, Version mapgw, Build 1167R, Built Sep 4 2018 10:03:38 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @N:MF284 : | Setting synthesis effort to medium for the design @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB) @N:MF284 : | Setting synthesis effort to medium for the design Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 191MB peak: 192MB) Available hyper_sources - for debug and ip models None Found @N:MT206 : | Auto Constrain mode is enabled Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 190MB peak: 192MB) Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 194MB) Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 201MB peak: 202MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 198MB peak: 202MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 198MB peak: 202MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 198MB peak: 202MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 198MB peak: 202MB) Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 198MB peak: 202MB) Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 220MB peak: 222MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:02s -2.87ns 465 / 303 2 0h:00m:02s -2.87ns 468 / 303 3 0h:00m:02s -2.60ns 468 / 303 Timing driven replication report Added 1 Registers via timing driven replication Added 1 LUTs via timing driven replication 4 0h:00m:03s -2.46ns 490 / 304 5 0h:00m:03s -2.73ns 491 / 304 6 0h:00m:03s -2.60ns 491 / 304 7 0h:00m:03s -2.60ns 491 / 304 8 0h:00m:03s -2.73ns 492 / 304 9 0h:00m:03s -2.46ns 491 / 304 Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 222MB peak: 223MB) @N:FX164 : | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. Finished restoring hierarchy (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 222MB peak: 223MB) Start Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 151MB peak: 223MB) Writing Analyst data base E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_RAM_Based_Shift_Register_IP_RefDesign\Fixed_ex\project\impl\temp\gao\ao_0\rev_1\synwork\ao_0_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 220MB peak: 223MB) Writing Verilog Simulation files Writing scf file... (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 220MB peak: 223MB) @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 219MB peak: 223MB) Start final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 220MB peak: 223MB) @W:MT420 : | Found inferred clock ao_top_0|clk_i with period 4.43ns. Please declare a user-defined clock on port clk_i. @W:MT420 : | Found inferred clock ao_top_0|control[0] with period 6.21ns. Please declare a user-defined clock on port control[0]. ##### START OF TIMING REPORT #####[ # Timing Report written on Wed Sep 19 08:40:01 2018 # Top view: ao_top_0 Requested Frequency: 161.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: -1.096 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------------------- ao_top_0|clk_i 225.9 MHz 192.0 MHz 4.426 5.207 -0.781 inferred Autoconstr_clkgroup_0 ao_top_0|control[0] 161.0 MHz 136.8 MHz 6.212 7.309 -1.096 inferred Autoconstr_clkgroup_1 System 150.0 MHz 228.2 MHz 6.667 4.382 2.284 system system_clkgroup ============================================================================================================================= Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise --------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack --------------------------------------------------------------------------------------------------------------------------------- System ao_top_0|clk_i | 4.426 2.284 | No paths - | No paths - | No paths - System ao_top_0|control[0] | 6.212 4.296 | No paths - | No paths - | No paths - ao_top_0|clk_i System | 4.426 3.648 | No paths - | No paths - | No paths - ao_top_0|clk_i ao_top_0|clk_i | 4.426 -0.781 | 4.426 3.587 | No paths - | 2.213 1.374 ao_top_0|clk_i ao_top_0|control[0] | Diff grp - | No paths - | No paths - | No paths - ao_top_0|control[0] System | 6.212 5.251 | No paths - | No paths - | No paths - ao_top_0|control[0] ao_top_0|clk_i | Diff grp - | No paths - | No paths - | No paths - ao_top_0|control[0] ao_top_0|control[0] | 6.212 -1.096 | No paths - | No paths - | No paths - ================================================================================================================================= Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: ao_top_0|clk_i ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------- triger_level_cnt[3] ao_top_0|clk_i DFFC Q triger_level_cnt[3] 0.243 -0.781 triger_level_cnt[2] ao_top_0|clk_i DFFC Q triger_level_cnt[2] 0.243 -0.760 capture_window_sel[2] ao_top_0|clk_i DFFC Q capture_window_sel[2] 0.243 -0.720 internal_reg_force_triger_syn[1] ao_top_0|clk_i DFFC Q internal_reg_force_triger_syn[1] 0.243 -0.716 capture_window_sel[0] ao_top_0|clk_i DFFC Q capture_window_sel[0] 0.243 -0.699 genblk1\.u_ao_match_0.match_sep ao_top_0|clk_i DFFC Q match 0.243 -0.695 capture_window_sel[1] ao_top_0|clk_i DFFC Q capture_window_sel[1] 0.243 -0.608 triger_level_cnt[0] ao_top_0|clk_i DFFC Q triger_level_cnt[0] 0.243 -0.608 triger_level_cnt[1] ao_top_0|clk_i DFFC Q triger_level_cnt[1] 0.243 -0.517 u_ao_mem_ctrl.capture_length[0] ao_top_0|clk_i DFFC Q capture_length[0] 0.243 -0.414 ================================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------- u_ao_mem_ctrl.capture_mem_wr ao_top_0|clk_i DFFCE CE un1_start_reg 4.365 -0.781 u_ao_mem_ctrl.mem_addr_inc_en ao_top_0|clk_i DFFCE CE mem_addr_inc_en_RNO 4.365 -0.690 u_ao_mem_ctrl.mem_addr_inc_en ao_top_0|clk_i DFFCE D mem_addr_inc_en7 4.365 -0.117 triger_level_cnt[2] ao_top_0|clk_i DFFC D triger_level_cnt_4[2] 4.365 -0.056 u_ao_mem_ctrl.capture_length[0] ao_top_0|clk_i DFFC D capture_length_5[0] 4.365 -0.009 u_ao_mem_ctrl.capture_length[1] ao_top_0|clk_i DFFC D capture_length_5[1] 4.365 -0.009 u_ao_mem_ctrl.capture_length[2] ao_top_0|clk_i DFFC D capture_length_5[2] 4.365 -0.009 u_ao_mem_ctrl.capture_length[3] ao_top_0|clk_i DFFP D capture_length_5[3] 4.365 -0.009 u_ao_mem_ctrl.capture_length[4] ao_top_0|clk_i DFFC D capture_length_5[4] 4.365 -0.009 u_ao_mem_ctrl.capture_length[5] ao_top_0|clk_i DFFC D capture_length_5[5] 4.365 -0.009 ====================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 4.426 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.365 - Propagation time: 5.146 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.781 Number of logic level(s): 5 Starting point: triger_level_cnt[3] / Q Ending point: u_ao_mem_ctrl.capture_mem_wr / CE The start point is clocked by ao_top_0|clk_i [rising] on pin CLK The end point is clocked by ao_top_0|clk_i [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------- triger_level_cnt[3] DFFC Q Out 0.243 0.243 - triger_level_cnt[3] Net - - 0.535 - 4 triger_level_cnt13_1 LUT2 I1 In - 0.778 - triger_level_cnt13_1 LUT2 F Out 0.570 1.348 - triger_level_cnt13_1 Net - - 0.401 - 1 triger_level_cnt13 LUT4 I1 In - 1.749 - triger_level_cnt13 LUT4 F Out 0.570 2.319 - triger_level_cnt13 Net - - 0.535 - 5 triger_level_cnt_0_sqmuxa LUT3 I2 In - 2.854 - triger_level_cnt_0_sqmuxa LUT3 F Out 0.462 3.316 - triger_level_cnt_0_sqmuxa Net - - 0.596 - 15 u_ao_mem_ctrl.un1_start_reg_1 LUT4 I2 In - 3.912 - u_ao_mem_ctrl.un1_start_reg_1 LUT4 F Out 0.462 4.374 - un1_start_reg_1 Net - - 0.401 - 1 u_ao_mem_ctrl.un1_start_reg LUT4 I3 In - 4.775 - u_ao_mem_ctrl.un1_start_reg LUT4 F Out 0.371 5.146 - un1_start_reg Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_wr DFFCE CE In - 5.146 - ============================================================================================= Total path delay (propagation time + setup) of 5.207 is 2.739(52.6%) logic and 2.468(47.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 4.426 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.365 - Propagation time: 5.125 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.760 Number of logic level(s): 5 Starting point: triger_level_cnt[2] / Q Ending point: u_ao_mem_ctrl.capture_mem_wr / CE The start point is clocked by ao_top_0|clk_i [rising] on pin CLK The end point is clocked by ao_top_0|clk_i [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------- triger_level_cnt[2] DFFC Q Out 0.243 0.243 - triger_level_cnt[2] Net - - 0.535 - 5 triger_level_cnt13_1 LUT2 I0 In - 0.778 - triger_level_cnt13_1 LUT2 F Out 0.549 1.327 - triger_level_cnt13_1 Net - - 0.401 - 1 triger_level_cnt13 LUT4 I1 In - 1.728 - triger_level_cnt13 LUT4 F Out 0.570 2.298 - triger_level_cnt13 Net - - 0.535 - 5 triger_level_cnt_0_sqmuxa LUT3 I2 In - 2.833 - triger_level_cnt_0_sqmuxa LUT3 F Out 0.462 3.295 - triger_level_cnt_0_sqmuxa Net - - 0.596 - 15 u_ao_mem_ctrl.un1_start_reg_1 LUT4 I2 In - 3.891 - u_ao_mem_ctrl.un1_start_reg_1 LUT4 F Out 0.462 4.353 - un1_start_reg_1 Net - - 0.401 - 1 u_ao_mem_ctrl.un1_start_reg LUT4 I3 In - 4.754 - u_ao_mem_ctrl.un1_start_reg LUT4 F Out 0.371 5.125 - un1_start_reg Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_wr DFFCE CE In - 5.125 - ============================================================================================= Total path delay (propagation time + setup) of 5.186 is 2.718(52.4%) logic and 2.468(47.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 4.426 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.365 - Propagation time: 5.085 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.720 Number of logic level(s): 5 Starting point: capture_window_sel[2] / Q Ending point: u_ao_mem_ctrl.capture_mem_wr / CE The start point is clocked by ao_top_0|clk_i [rising] on pin CLK The end point is clocked by ao_top_0|clk_i [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------- capture_window_sel[2] DFFC Q Out 0.243 0.243 - capture_window_sel[2] Net - - 0.535 - 5 un6_start_reg_ac0_5_c_2 LUT4 I1 In - 0.778 - un6_start_reg_ac0_5_c_2 LUT4 F Out 0.570 1.348 - un6_start_reg_ac0_5_c_2 Net - - 0.401 - 1 un6_start_reg_ac0_5_0_0 LUT4 I2 In - 1.749 - un6_start_reg_ac0_5_0_0 LUT4 F Out 0.462 2.211 - un6_start_reg_ac0_5_0_0 Net - - 0.535 - 2 start_reg LUT4 I2 In - 2.746 - start_reg LUT4 F Out 0.462 3.208 - start_reg Net - - 0.535 - 4 u_ao_mem_ctrl.un1_start_reg_1 LUT4 I1 In - 3.743 - u_ao_mem_ctrl.un1_start_reg_1 LUT4 F Out 0.570 4.313 - un1_start_reg_1 Net - - 0.401 - 1 u_ao_mem_ctrl.un1_start_reg LUT4 I3 In - 4.714 - u_ao_mem_ctrl.un1_start_reg LUT4 F Out 0.371 5.085 - un1_start_reg Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_wr DFFCE CE In - 5.085 - ============================================================================================= Total path delay (propagation time + setup) of 5.146 is 2.739(53.2%) logic and 2.407(46.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 4.426 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.365 - Propagation time: 5.081 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.716 Number of logic level(s): 5 Starting point: internal_reg_force_triger_syn[1] / Q Ending point: u_ao_mem_ctrl.capture_mem_wr / CE The start point is clocked by ao_top_0|clk_i [rising] on pin CLK The end point is clocked by ao_top_0|clk_i [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------ internal_reg_force_triger_syn[1] DFFC Q Out 0.243 0.243 - internal_reg_force_triger_syn[1] Net - - 0.535 - 1 un1_match_final_3 LUT4 I1 In - 0.778 - un1_match_final_3 LUT4 F Out 0.570 1.348 - un1_match_final_3 Net - - 0.535 - 2 triger_level_cnt13 LUT4 I3 In - 1.883 - triger_level_cnt13 LUT4 F Out 0.371 2.254 - triger_level_cnt13 Net - - 0.535 - 5 triger_level_cnt_0_sqmuxa LUT3 I2 In - 2.789 - triger_level_cnt_0_sqmuxa LUT3 F Out 0.462 3.251 - triger_level_cnt_0_sqmuxa Net - - 0.596 - 15 u_ao_mem_ctrl.un1_start_reg_1 LUT4 I2 In - 3.847 - u_ao_mem_ctrl.un1_start_reg_1 LUT4 F Out 0.462 4.309 - un1_start_reg_1 Net - - 0.401 - 1 u_ao_mem_ctrl.un1_start_reg LUT4 I3 In - 4.710 - u_ao_mem_ctrl.un1_start_reg LUT4 F Out 0.371 5.081 - un1_start_reg Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_wr DFFCE CE In - 5.081 - ================================================================================================ Total path delay (propagation time + setup) of 5.142 is 2.540(49.4%) logic and 2.602(50.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 4.426 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.365 - Propagation time: 5.064 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.699 Number of logic level(s): 5 Starting point: capture_window_sel[0] / Q Ending point: u_ao_mem_ctrl.capture_mem_wr / CE The start point is clocked by ao_top_0|clk_i [rising] on pin CLK The end point is clocked by ao_top_0|clk_i [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------- capture_window_sel[0] DFFC Q Out 0.243 0.243 - capture_window_sel[0] Net - - 0.535 - 7 un6_start_reg_ac0_5_c_2 LUT4 I0 In - 0.778 - un6_start_reg_ac0_5_c_2 LUT4 F Out 0.549 1.327 - un6_start_reg_ac0_5_c_2 Net - - 0.401 - 1 un6_start_reg_ac0_5_0_0 LUT4 I2 In - 1.728 - un6_start_reg_ac0_5_0_0 LUT4 F Out 0.462 2.190 - un6_start_reg_ac0_5_0_0 Net - - 0.535 - 2 start_reg LUT4 I2 In - 2.725 - start_reg LUT4 F Out 0.462 3.187 - start_reg Net - - 0.535 - 4 u_ao_mem_ctrl.un1_start_reg_1 LUT4 I1 In - 3.722 - u_ao_mem_ctrl.un1_start_reg_1 LUT4 F Out 0.570 4.292 - un1_start_reg_1 Net - - 0.401 - 1 u_ao_mem_ctrl.un1_start_reg LUT4 I3 In - 4.693 - u_ao_mem_ctrl.un1_start_reg LUT4 F Out 0.371 5.064 - un1_start_reg Net - - 0.000 - 1 u_ao_mem_ctrl.capture_mem_wr DFFCE CE In - 5.064 - ============================================================================================= Total path delay (propagation time + setup) of 5.125 is 2.718(53.0%) logic and 2.407(47.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: ao_top_0|control[0] ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------ internal_register_select[9] ao_top_0|control[0] DFFCE Q internal_register_select[9] 0.243 -1.096 internal_register_select[7] ao_top_0|control[0] DFFCE Q internal_register_select[7] 0.243 -1.075 internal_register_select[10] ao_top_0|control[0] DFFCE Q internal_register_select[10] 0.243 -0.988 internal_register_select[11] ao_top_0|control[0] DFFCE Q internal_register_select[11] 0.243 -0.897 word_count[13] ao_top_0|control[0] DFFCE Q word_count[13] 0.243 -0.792 word_count[1] ao_top_0|control[0] DFFCE Q word_count[1] 0.243 -0.771 word_count[10] ao_top_0|control[0] DFFCE Q word_count[10] 0.243 -0.771 word_count[0] ao_top_0|control[0] DFFCE Q word_count[0] 0.243 -0.750 word_count[3] ao_top_0|control[0] DFFCE Q word_count[3] 0.243 -0.684 word_count[14] ao_top_0|control[0] DFFCE Q word_count[14] 0.243 -0.684 ============================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------- data_out_shift_reg[3] ao_top_0|control[0] DFFCE D data_out_shift_reg_4[3] 6.151 -1.096 data_out_shift_reg[4] ao_top_0|control[0] DFFCE D data_out_shift_reg_4[4] 6.151 -1.096 data_out_shift_reg[5] ao_top_0|control[0] DFFCE D data_out_shift_reg_4[5] 6.151 -1.096 data_out_shift_reg[6] ao_top_0|control[0] DFFCE D data_out_shift_reg_4[6] 6.151 -1.096 data_out_shift_reg[7] ao_top_0|control[0] DFFCE D data_out_shift_reg_4[7] 6.151 -1.096 data_out_shift_reg[1] ao_top_0|control[0] DFFCE D data_out_shift_reg_4[1] 6.151 -1.025 data_out_shift_reg[0] ao_top_0|control[0] DFFCE D data_out_shift_reg_4[0] 6.151 -0.955 address_counter[0] ao_top_0|control[0] DFFCE CE addr_ct_en 6.151 -0.792 address_counter[1] ao_top_0|control[0] DFFCE CE addr_ct_en 6.151 -0.792 address_counter[2] ao_top_0|control[0] DFFCE CE addr_ct_en 6.151 -0.792 =================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 6.212 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 6.151 - Propagation time: 7.248 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.096 Number of logic level(s): 7 Starting point: internal_register_select[9] / Q Ending point: data_out_shift_reg[4] / D The start point is clocked by ao_top_0|control[0] [rising] on pin CLK The end point is clocked by ao_top_0|control[0] [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------- internal_register_select[9] DFFCE Q Out 0.243 0.243 - internal_register_select[9] Net - - 0.535 - 1 match_unit_rd_en_2_4[0] LUT4 I1 In - 0.778 - match_unit_rd_en_2_4[0] LUT4 F Out 0.570 1.348 - match_unit_rd_en_2_4[0] Net - - 0.535 - 1 match_unit_rd_en_2[0] MUX2_LUT5 S0 In - 1.883 - match_unit_rd_en_2[0] MUX2_LUT5 O Out 0.269 2.152 - internal_reg_start_m_14 Net - - 0.596 - 18 data_from_internal_reg79 LUT3 I2 In - 2.748 - data_from_internal_reg79 LUT3 F Out 0.462 3.210 - data_from_internal_reg79 Net - - 0.596 - 16 data_from_ao_reg_1[4] LUT4 I1 In - 3.806 - data_from_ao_reg_1[4] LUT4 F Out 0.570 4.376 - data_from_ao_reg_1[4] Net - - 0.401 - 1 data_from_ao_reg_2[4] LUT4 I1 In - 4.777 - data_from_ao_reg_2[4] LUT4 F Out 0.570 5.347 - data_from_ao_reg_2[4] Net - - 0.401 - 1 data_out_shift_reg_4_0[4] LUT4 I0 In - 5.748 - data_out_shift_reg_4_0[4] LUT4 F Out 0.549 6.297 - N_424 Net - - 0.401 - 1 data_out_shift_reg_4[4] LUT3 I0 In - 6.699 - data_out_shift_reg_4[4] LUT3 F Out 0.549 7.248 - data_out_shift_reg_4[4] Net - - 0.000 - 1 data_out_shift_reg[4] DFFCE D In - 7.248 - =============================================================================================== Total path delay (propagation time + setup) of 7.309 is 3.843(52.6%) logic and 3.466(47.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 6.212 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 6.151 - Propagation time: 7.248 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.096 Number of logic level(s): 7 Starting point: internal_register_select[9] / Q Ending point: data_out_shift_reg[3] / D The start point is clocked by ao_top_0|control[0] [rising] on pin CLK The end point is clocked by ao_top_0|control[0] [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------- internal_register_select[9] DFFCE Q Out 0.243 0.243 - internal_register_select[9] Net - - 0.535 - 1 match_unit_rd_en_2_4[0] LUT4 I1 In - 0.778 - match_unit_rd_en_2_4[0] LUT4 F Out 0.570 1.348 - match_unit_rd_en_2_4[0] Net - - 0.535 - 1 match_unit_rd_en_2[0] MUX2_LUT5 S0 In - 1.883 - match_unit_rd_en_2[0] MUX2_LUT5 O Out 0.269 2.152 - internal_reg_start_m_14 Net - - 0.596 - 18 data_from_internal_reg80 LUT3 I2 In - 2.748 - data_from_internal_reg80 LUT3 F Out 0.462 3.210 - data_from_internal_reg80 Net - - 0.596 - 16 data_from_ao_reg_0[3] LUT4 I1 In - 3.806 - data_from_ao_reg_0[3] LUT4 F Out 0.570 4.376 - data_from_ao_reg_0[3] Net - - 0.401 - 1 data_from_ao_reg_4[3] LUT4 I1 In - 4.777 - data_from_ao_reg_4[3] LUT4 F Out 0.570 5.347 - data_from_ao_reg_4[3] Net - - 0.401 - 1 data_out_shift_reg_4_0[3] LUT4 I0 In - 5.748 - data_out_shift_reg_4_0[3] LUT4 F Out 0.549 6.297 - N_423 Net - - 0.401 - 1 data_out_shift_reg_4[3] LUT3 I0 In - 6.699 - data_out_shift_reg_4[3] LUT3 F Out 0.549 7.248 - data_out_shift_reg_4[3] Net - - 0.000 - 1 data_out_shift_reg[3] DFFCE D In - 7.248 - =============================================================================================== Total path delay (propagation time + setup) of 7.309 is 3.843(52.6%) logic and 3.466(47.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 6.212 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 6.151 - Propagation time: 7.248 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.096 Number of logic level(s): 7 Starting point: internal_register_select[9] / Q Ending point: data_out_shift_reg[6] / D The start point is clocked by ao_top_0|control[0] [rising] on pin CLK The end point is clocked by ao_top_0|control[0] [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------- internal_register_select[9] DFFCE Q Out 0.243 0.243 - internal_register_select[9] Net - - 0.535 - 1 match_unit_rd_en_2_4[0] LUT4 I1 In - 0.778 - match_unit_rd_en_2_4[0] LUT4 F Out 0.570 1.348 - match_unit_rd_en_2_4[0] Net - - 0.535 - 1 match_unit_rd_en_2[0] MUX2_LUT5 S0 In - 1.883 - match_unit_rd_en_2[0] MUX2_LUT5 O Out 0.269 2.152 - internal_reg_start_m_14 Net - - 0.596 - 18 data_from_internal_reg79 LUT3 I2 In - 2.748 - data_from_internal_reg79 LUT3 F Out 0.462 3.210 - data_from_internal_reg79 Net - - 0.596 - 16 data_from_ao_reg_1[6] LUT4 I1 In - 3.806 - data_from_ao_reg_1[6] LUT4 F Out 0.570 4.376 - data_from_ao_reg_1[6] Net - - 0.401 - 1 data_from_ao_reg_2[6] LUT4 I1 In - 4.777 - data_from_ao_reg_2[6] LUT4 F Out 0.570 5.347 - data_from_ao_reg_2[6] Net - - 0.401 - 1 data_out_shift_reg_4_0[6] LUT4 I0 In - 5.748 - data_out_shift_reg_4_0[6] LUT4 F Out 0.549 6.297 - N_426 Net - - 0.401 - 1 data_out_shift_reg_4[6] LUT3 I0 In - 6.699 - data_out_shift_reg_4[6] LUT3 F Out 0.549 7.248 - data_out_shift_reg_4[6] Net - - 0.000 - 1 data_out_shift_reg[6] DFFCE D In - 7.248 - =============================================================================================== Total path delay (propagation time + setup) of 7.309 is 3.843(52.6%) logic and 3.466(47.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 6.212 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 6.151 - Propagation time: 7.248 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.096 Number of logic level(s): 7 Starting point: internal_register_select[9] / Q Ending point: data_out_shift_reg[7] / D The start point is clocked by ao_top_0|control[0] [rising] on pin CLK The end point is clocked by ao_top_0|control[0] [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------- internal_register_select[9] DFFCE Q Out 0.243 0.243 - internal_register_select[9] Net - - 0.535 - 1 match_unit_rd_en_2_4[0] LUT4 I1 In - 0.778 - match_unit_rd_en_2_4[0] LUT4 F Out 0.570 1.348 - match_unit_rd_en_2_4[0] Net - - 0.535 - 1 match_unit_rd_en_2[0] MUX2_LUT5 S0 In - 1.883 - match_unit_rd_en_2[0] MUX2_LUT5 O Out 0.269 2.152 - internal_reg_start_m_14 Net - - 0.596 - 18 data_from_internal_reg79 LUT3 I2 In - 2.748 - data_from_internal_reg79 LUT3 F Out 0.462 3.210 - data_from_internal_reg79 Net - - 0.596 - 16 data_from_ao_reg_1[7] LUT4 I1 In - 3.806 - data_from_ao_reg_1[7] LUT4 F Out 0.570 4.376 - data_from_ao_reg_1[7] Net - - 0.401 - 1 data_from_ao_reg_2[7] LUT4 I1 In - 4.777 - data_from_ao_reg_2[7] LUT4 F Out 0.570 5.347 - data_from_ao_reg_2[7] Net - - 0.401 - 1 data_out_shift_reg_4_0[7] LUT4 I0 In - 5.748 - data_out_shift_reg_4_0[7] LUT4 F Out 0.549 6.297 - N_427 Net - - 0.401 - 1 data_out_shift_reg_4[7] LUT3 I0 In - 6.699 - data_out_shift_reg_4[7] LUT3 F Out 0.549 7.248 - data_out_shift_reg_4[7] Net - - 0.000 - 1 data_out_shift_reg[7] DFFCE D In - 7.248 - =============================================================================================== Total path delay (propagation time + setup) of 7.309 is 3.843(52.6%) logic and 3.466(47.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 6.212 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 6.151 - Propagation time: 7.248 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.096 Number of logic level(s): 7 Starting point: internal_register_select[9] / Q Ending point: data_out_shift_reg[5] / D The start point is clocked by ao_top_0|control[0] [rising] on pin CLK The end point is clocked by ao_top_0|control[0] [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------- internal_register_select[9] DFFCE Q Out 0.243 0.243 - internal_register_select[9] Net - - 0.535 - 1 match_unit_rd_en_2_4[0] LUT4 I1 In - 0.778 - match_unit_rd_en_2_4[0] LUT4 F Out 0.570 1.348 - match_unit_rd_en_2_4[0] Net - - 0.535 - 1 match_unit_rd_en_2[0] MUX2_LUT5 S0 In - 1.883 - match_unit_rd_en_2[0] MUX2_LUT5 O Out 0.269 2.152 - internal_reg_start_m_14 Net - - 0.596 - 18 data_from_internal_reg79 LUT3 I2 In - 2.748 - data_from_internal_reg79 LUT3 F Out 0.462 3.210 - data_from_internal_reg79 Net - - 0.596 - 16 data_from_ao_reg_1[5] LUT4 I1 In - 3.806 - data_from_ao_reg_1[5] LUT4 F Out 0.570 4.376 - data_from_ao_reg_1[5] Net - - 0.401 - 1 data_from_ao_reg_2[5] LUT4 I1 In - 4.777 - data_from_ao_reg_2[5] LUT4 F Out 0.570 5.347 - data_from_ao_reg_2[5] Net - - 0.401 - 1 data_out_shift_reg_4_0[5] LUT4 I0 In - 5.748 - data_out_shift_reg_4_0[5] LUT4 F Out 0.549 6.297 - N_425 Net - - 0.401 - 1 data_out_shift_reg_4[5] LUT3 I0 In - 6.699 - data_out_shift_reg_4[5] LUT3 F Out 0.549 7.248 - data_out_shift_reg_4[5] Net - - 0.000 - 1 data_out_shift_reg[5] DFFCE D In - 7.248 - =============================================================================================== Total path delay (propagation time + setup) of 7.309 is 3.843(52.6%) logic and 3.466(47.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------- u_ao_mem_ctrl.capture_mem_wr_RNIQKR6 System INV O capture_end 0.000 2.284 address_counter_cry_0_RNO[0] System INV O address_counter 0.000 4.296 ============================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------- capture_window_sel[2] System DFFC D capture_window_sel_3[2] 4.365 2.284 capture_window_sel[3] System DFFC D capture_window_sel_3[3] 4.365 2.284 capture_window_sel[1] System DFFC D capture_window_sel_3[1] 4.365 2.509 capture_window_sel[0] System DFFC D capture_window_sel_3[0] 4.365 3.281 internal_reg_start_dly[0] System DFFC D internal_reg_start_dly_2[0] 4.365 3.281 capture_end_dly System DFFP D capture_end 4.365 3.830 address_counter[9] System DFFCE D address_counter_s[9] 6.151 4.296 address_counter[8] System DFFCE D address_counter_s[8] 6.151 4.331 address_counter[7] System DFFCE D address_counter_s[7] 6.151 4.366 address_counter[6] System DFFCE D address_counter_s[6] 6.151 4.401 ================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 4.426 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.365 - Propagation time: 2.081 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 2.284 Number of logic level(s): 2 Starting point: u_ao_mem_ctrl.capture_mem_wr_RNIQKR6 / O Ending point: capture_window_sel[2] / D The start point is clocked by System [rising] The end point is clocked by ao_top_0|clk_i [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------- u_ao_mem_ctrl.capture_mem_wr_RNIQKR6 INV O Out 0.000 0.000 - capture_end Net - - 0.535 - 6 un1_capture_window_sel_ac0_1 LUT4 I0 In - 0.535 - un1_capture_window_sel_ac0_1 LUT4 F Out 0.549 1.084 - un1_capture_window_sel_c2 Net - - 0.535 - 2 capture_window_sel_3[2] LUT3 I2 In - 1.619 - capture_window_sel_3[2] LUT3 F Out 0.462 2.081 - capture_window_sel_3[2] Net - - 0.000 - 1 capture_window_sel[2] DFFC D In - 2.081 - =================================================================================================== Total path delay (propagation time + setup) of 2.142 is 1.072(50.0%) logic and 1.070(50.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied None Finished final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 220MB peak: 223MB) Finished timing report (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 220MB peak: 223MB) --------------------------------------- Resource Usage Report for ao_top_0 Mapping to part: gw2a_55pbga484-8 Cell usage: ALU 85 uses DFF 16 uses DFFC 44 uses DFFCE 207 uses DFFNP 2 uses DFFP 3 uses DFFPE 32 uses GSR 1 use INV 2 uses MUX2_LUT5 8 uses MUX2_LUT6 3 uses SDPX9 1 use LUT2 48 uses LUT3 111 uses LUT4 270 uses I/O ports: 35 I/O primitives: 35 IBUF 33 uses OBUF 2 uses I/O Register bits: 0 Register bits not including I/Os: 304 of 41040 (0%) RAM/ROM usage summary Block Rams : 1 of 140 (0%) Total load per clock: ao_top_0|clk_i: 1 ao_top_0|control[0]: 247 @S |Mapping Summary: Total LUTs: 429 (0%) Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 45MB peak: 223MB) Process took 0h:00m:07s realtime, 0h:00m:06s cputime # Wed Sep 19 08:40:01 2018 ###########################################################]