@W: MT246 :"d:\user-bak\users\fdell\desktop\gowin_ram_based_shift_register_ip_refdesign\fixed_ex\project\src\gw_pll\gw_pll.v":26:4:26:11|Blackbox PLL is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT420 |Found inferred clock GW_PLL|clkout_inferred_clock with period 2.21ns. Please declare a user-defined clock on net GW_PLL_inst.clk.
