rtl_dir:=		../../../project/1_Board_project_AXI4_LITE_32bit/src
tb_dir:=		../../../tb
tb_file:=		$(tb_dir)/AXI_Stream_FIFO_TB.v								
wave_file:=		signal_wave.rc
define_file:=	master_define.v
vcs:
	vcs -debug_all -R -full64 -fsdb -sverilog 			\
	-v $(tb_dir)/prim_sim.v 							\
	$(define_file)										\
	$(tb_file)											\
	$(rtl_dir)/axi_stream_fifo/axi_stream_fifo.vo								\
	 -cm line+cond+fsm+branch+tgl


vd:
	verdi -nologo -sverilog										\
	-v $(tb_dir)/prim_sim.v 							\
	$(tb_file)											\
	$(rtl_dir)/axi_stream_fifo/axi_stream_fifo.vo								\
	-ssf test.fsdb										\
	-sswr												\
	$(wave_file) 							\
	&
#reVd:
#	./repair.sh tb
#	verdi -ssr signal_wave.ses &
#----------------------------------------------------------------------------------------------------
# Rule to clean temp files
#----------------------------------------------------------------------------------------------------
clean:
	rm -rf csrc simv.daidir simv.vdb verdiLog cm.log novas.conf novas.rc *.log simv verilog.fsdb ucli.key wave.ses.png 	./repair.sh tb
