Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\AXI_STREAM_FIFO\data\AXI_Stream_FIFO_Top.v D:\Gowin\Gowin_V1.9.9Beta-3\IDE\ipcore\AXI_STREAM_FIFO\data\AXI_Stream_FIFO.v |
| GowinSynthesis Constraints File | --- |
| Version | V1.9.9 Beta-3 |
| Part Number | GW2A-LV55PG484C8/I7 |
| Device | GW2A-55 |
| Device Version | C |
| Created Time | Fri Jul 28 16:16:33 2023 |
| Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | AXI_Stream_FIFO_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.437s, Elapsed time = 0h 0m 0.452s, Peak memory usage = 50.332MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 50.332MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.08s, Peak memory usage = 50.332MB Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.044s, Peak memory usage = 50.332MB Optimizing Phase 2: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.109s, Peak memory usage = 50.332MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.03s, Peak memory usage = 50.332MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 50.332MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 50.332MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 50.332MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.139s, Peak memory usage = 50.332MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.038s, Peak memory usage = 50.332MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 50.332MB Tech-Mapping Phase 3: CPU time = 0h 0m 8s, Elapsed time = 0h 0m 8s, Peak memory usage = 63.641MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.312s, Peak memory usage = 63.641MB Generate output files: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.108s, Peak memory usage = 63.641MB |
| Total Time and Memory Usage | CPU time = 0h 0m 9s, Elapsed time = 0h 0m 9s, Peak memory usage = 63.641MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 539 |
| I/O Buf | 403 |
| IBUF | 209 |
| OBUF | 194 |
| Register | 1036 |
| DFF | 36 |
| DFFE | 199 |
| DFFR | 2 |
| DFFRE | 1 |
| DFFP | 4 |
| DFFPE | 15 |
| DFFC | 163 |
| DFFCE | 616 |
| LUT | 2221 |
| LUT2 | 192 |
| LUT3 | 912 |
| LUT4 | 1117 |
| ALU | 36 |
| ALU | 36 |
| INV | 8 |
| INV | 8 |
| BSRAM | 4 |
| SDPB | 4 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 2265(2229 LUTs, 36 ALUs) / 54720 | 5% |
| Register | 1036 / 41997 | 3% |
| --Register as Latch | 0 / 41997 | 0% |
| --Register as FF | 1036 / 41997 | 3% |
| BSRAM | 4 / 140 | 3% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| S_axi_aclk | Base | 10.000 | 100.0 | 0.000 | 5.000 | S_axi_aclk_ibuf/I |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | S_axi_aclk | 100.0(MHz) | 162.0(MHz) | 8 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 3.826 |
| Data Arrival Time | 7.001 |
| Data Required Time | 10.828 |
| From | AXI_Stream_FIFO_inst/tlr_mem_data[1]_1_s1 |
| To | AXI_Stream_FIFO_inst/isr_tse_reg_s1 |
| Launch Clk | S_axi_aclk[R] |
| Latch Clk | S_axi_aclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | S_axi_aclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | S_axi_aclk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 1044 | S_axi_aclk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | AXI_Stream_FIFO_inst/tlr_mem_data[1]_1_s1/CLK |
| 1.095 | 0.232 | tC2Q | RF | 2 | AXI_Stream_FIFO_inst/tlr_mem_data[1]_1_s1/Q |
| 1.332 | 0.237 | tNET | FF | 1 | AXI_Stream_FIFO_inst/n3127_s36/I1 |
| 1.887 | 0.555 | tINS | FF | 1 | AXI_Stream_FIFO_inst/n3127_s36/F |
| 2.124 | 0.237 | tNET | FF | 1 | AXI_Stream_FIFO_inst/n3127_s32/I0 |
| 2.227 | 0.103 | tINS | FF | 1 | AXI_Stream_FIFO_inst/n3127_s32/O |
| 2.464 | 0.237 | tNET | FF | 1 | AXI_Stream_FIFO_inst/n3127_s30/I0 |
| 2.566 | 0.103 | tINS | FF | 1 | AXI_Stream_FIFO_inst/n3127_s30/O |
| 2.803 | 0.237 | tNET | FF | 1 | AXI_Stream_FIFO_inst/n3127_s29/I0 |
| 2.906 | 0.103 | tINS | FF | 18 | AXI_Stream_FIFO_inst/n3127_s29/O |
| 3.143 | 0.237 | tNET | FF | 1 | AXI_Stream_FIFO_inst/n5127_s15/I1 |
| 3.698 | 0.555 | tINS | FF | 5 | AXI_Stream_FIFO_inst/n5127_s15/F |
| 3.935 | 0.237 | tNET | FF | 1 | AXI_Stream_FIFO_inst/n5127_s20/I1 |
| 4.490 | 0.555 | tINS | FF | 1 | AXI_Stream_FIFO_inst/n5127_s20/F |
| 4.727 | 0.237 | tNET | FF | 1 | AXI_Stream_FIFO_inst/n5127_s11/I2 |
| 5.181 | 0.453 | tINS | FF | 1 | AXI_Stream_FIFO_inst/n5127_s11/F |
| 5.418 | 0.237 | tNET | FF | 1 | AXI_Stream_FIFO_inst/n5127_s6/I1 |
| 5.972 | 0.555 | tINS | FF | 1 | AXI_Stream_FIFO_inst/n5127_s6/F |
| 6.209 | 0.237 | tNET | FF | 1 | AXI_Stream_FIFO_inst/n5127_s4/I1 |
| 6.764 | 0.555 | tINS | FF | 1 | AXI_Stream_FIFO_inst/n5127_s4/F |
| 7.001 | 0.237 | tNET | FF | 1 | AXI_Stream_FIFO_inst/isr_tse_reg_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | S_axi_aclk | |||
| 10.000 | 0.000 | tCL | RR | 1 | S_axi_aclk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 1044 | S_axi_aclk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | AXI_Stream_FIFO_inst/isr_tse_reg_s1/CLK |
| 10.828 | -0.035 | tSu | 1 | AXI_Stream_FIFO_inst/isr_tse_reg_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 3.537, 57.615%; route: 2.370, 38.606%; tC2Q: 0.232, 3.779% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:| Slack | 4.881 |
| Data Arrival Time | 5.947 |
| Data Required Time | 10.828 |
| From | AXI_Stream_FIFO_inst/rfifo_ween_s0 |
| To | AXI_Stream_FIFO_inst/fifo_add_receive1/fifo_sc_inst/Empty_s0 |
| Launch Clk | S_axi_aclk[R] |
| Latch Clk | S_axi_aclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | S_axi_aclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | S_axi_aclk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 1044 | S_axi_aclk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | AXI_Stream_FIFO_inst/rfifo_ween_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 30 | AXI_Stream_FIFO_inst/rfifo_ween_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | AXI_Stream_FIFO_inst/fifo_add_receive1/fifo_sc_inst/wbin_next_2_s4/I1 |
| 1.887 | 0.555 | tINS | FF | 5 | AXI_Stream_FIFO_inst/fifo_add_receive1/fifo_sc_inst/wbin_next_2_s4/F |
| 2.124 | 0.237 | tNET | FF | 1 | AXI_Stream_FIFO_inst/fifo_add_receive1/fifo_sc_inst/wbin_next_3_s4/I1 |
| 2.679 | 0.555 | tINS | FF | 5 | AXI_Stream_FIFO_inst/fifo_add_receive1/fifo_sc_inst/wbin_next_3_s4/F |
| 2.916 | 0.237 | tNET | FF | 1 | AXI_Stream_FIFO_inst/fifo_add_receive1/fifo_sc_inst/wbin_next_6_s6/I0 |
| 3.433 | 0.517 | tINS | FF | 4 | AXI_Stream_FIFO_inst/fifo_add_receive1/fifo_sc_inst/wbin_next_6_s6/F |
| 3.670 | 0.237 | tNET | FF | 1 | AXI_Stream_FIFO_inst/fifo_add_receive1/fifo_sc_inst/wbin_next_6_s3/I1 |
| 4.225 | 0.555 | tINS | FF | 2 | AXI_Stream_FIFO_inst/fifo_add_receive1/fifo_sc_inst/wbin_next_6_s3/F |
| 4.462 | 0.237 | tNET | FF | 1 | AXI_Stream_FIFO_inst/fifo_add_receive1/fifo_sc_inst/n265_s0/I1 |
| 5.032 | 0.570 | tINS | FR | 1 | AXI_Stream_FIFO_inst/fifo_add_receive1/fifo_sc_inst/n265_s0/COUT |
| 5.032 | 0.000 | tNET | RR | 1 | AXI_Stream_FIFO_inst/fifo_add_receive1/fifo_sc_inst/n266_s0/CIN |
| 5.067 | 0.035 | tINS | RF | 1 | AXI_Stream_FIFO_inst/fifo_add_receive1/fifo_sc_inst/n266_s0/COUT |
| 5.067 | 0.000 | tNET | FF | 1 | AXI_Stream_FIFO_inst/fifo_add_receive1/fifo_sc_inst/n267_s0/CIN |
| 5.102 | 0.035 | tINS | FF | 1 | AXI_Stream_FIFO_inst/fifo_add_receive1/fifo_sc_inst/n267_s0/COUT |
| 5.339 | 0.237 | tNET | FF | 1 | AXI_Stream_FIFO_inst/fifo_add_receive1/fifo_sc_inst/rempty_val_s2/I3 |
| 5.710 | 0.371 | tINS | FF | 1 | AXI_Stream_FIFO_inst/fifo_add_receive1/fifo_sc_inst/rempty_val_s2/F |
| 5.947 | 0.237 | tNET | FF | 1 | AXI_Stream_FIFO_inst/fifo_add_receive1/fifo_sc_inst/Empty_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | S_axi_aclk | |||
| 10.000 | 0.000 | tCL | RR | 1 | S_axi_aclk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 1044 | S_axi_aclk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | AXI_Stream_FIFO_inst/fifo_add_receive1/fifo_sc_inst/Empty_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | AXI_Stream_FIFO_inst/fifo_add_receive1/fifo_sc_inst/Empty_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 3.193, 62.808%; route: 1.659, 32.629%; tC2Q: 0.232, 4.563% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:| Slack | 4.884 |
| Data Arrival Time | 5.944 |
| Data Required Time | 10.828 |
| From | AXI_Stream_FIFO_inst/rfifo_add_cnt_7_s1 |
| To | AXI_Stream_FIFO_inst/rfifo_add_cnt_24_s1 |
| Launch Clk | S_axi_aclk[R] |
| Latch Clk | S_axi_aclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | S_axi_aclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | S_axi_aclk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 1044 | S_axi_aclk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | AXI_Stream_FIFO_inst/rfifo_add_cnt_7_s1/CLK |
| 1.095 | 0.232 | tC2Q | RF | 6 | AXI_Stream_FIFO_inst/rfifo_add_cnt_7_s1/Q |
| 1.332 | 0.237 | tNET | FF | 1 | AXI_Stream_FIFO_inst/n9112_s3/I1 |
| 1.887 | 0.555 | tINS | FF | 1 | AXI_Stream_FIFO_inst/n9112_s3/F |
| 2.124 | 0.237 | tNET | FF | 1 | AXI_Stream_FIFO_inst/n9070_s14/I1 |
| 2.679 | 0.555 | tINS | FF | 2 | AXI_Stream_FIFO_inst/n9070_s14/F |
| 2.916 | 0.237 | tNET | FF | 1 | AXI_Stream_FIFO_inst/n9070_s10/I2 |
| 3.369 | 0.453 | tINS | FF | 9 | AXI_Stream_FIFO_inst/n9070_s10/F |
| 3.606 | 0.237 | tNET | FF | 1 | AXI_Stream_FIFO_inst/n9060_s12/I0 |
| 4.123 | 0.517 | tINS | FF | 7 | AXI_Stream_FIFO_inst/n9060_s12/F |
| 4.360 | 0.237 | tNET | FF | 1 | AXI_Stream_FIFO_inst/n9059_s10/I1 |
| 4.915 | 0.555 | tINS | FF | 1 | AXI_Stream_FIFO_inst/n9059_s10/F |
| 5.152 | 0.237 | tNET | FF | 1 | AXI_Stream_FIFO_inst/n9059_s8/I1 |
| 5.707 | 0.555 | tINS | FF | 1 | AXI_Stream_FIFO_inst/n9059_s8/F |
| 5.944 | 0.237 | tNET | FF | 1 | AXI_Stream_FIFO_inst/rfifo_add_cnt_24_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | S_axi_aclk | |||
| 10.000 | 0.000 | tCL | RR | 1 | S_axi_aclk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 1044 | S_axi_aclk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | AXI_Stream_FIFO_inst/rfifo_add_cnt_24_s1/CLK |
| 10.828 | -0.035 | tSu | 1 | AXI_Stream_FIFO_inst/rfifo_add_cnt_24_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 3.190, 62.783%; route: 1.659, 32.651%; tC2Q: 0.232, 4.566% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:| Slack | 4.922 |
| Data Arrival Time | 5.906 |
| Data Required Time | 10.828 |
| From | AXI_Stream_FIFO_inst/rfifo_add_cnt_7_s1 |
| To | AXI_Stream_FIFO_inst/rfifo_add_cnt_20_s1 |
| Launch Clk | S_axi_aclk[R] |
| Latch Clk | S_axi_aclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | S_axi_aclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | S_axi_aclk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 1044 | S_axi_aclk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | AXI_Stream_FIFO_inst/rfifo_add_cnt_7_s1/CLK |
| 1.095 | 0.232 | tC2Q | RF | 6 | AXI_Stream_FIFO_inst/rfifo_add_cnt_7_s1/Q |
| 1.332 | 0.237 | tNET | FF | 1 | AXI_Stream_FIFO_inst/n9112_s3/I1 |
| 1.887 | 0.555 | tINS | FF | 1 | AXI_Stream_FIFO_inst/n9112_s3/F |
| 2.124 | 0.237 | tNET | FF | 1 | AXI_Stream_FIFO_inst/n9070_s14/I1 |
| 2.679 | 0.555 | tINS | FF | 2 | AXI_Stream_FIFO_inst/n9070_s14/F |
| 2.916 | 0.237 | tNET | FF | 1 | AXI_Stream_FIFO_inst/n9070_s10/I2 |
| 3.369 | 0.453 | tINS | FF | 9 | AXI_Stream_FIFO_inst/n9070_s10/F |
| 3.606 | 0.237 | tNET | FF | 1 | AXI_Stream_FIFO_inst/n9065_s12/I0 |
| 4.123 | 0.517 | tINS | FF | 5 | AXI_Stream_FIFO_inst/n9065_s12/F |
| 4.360 | 0.237 | tNET | FF | 1 | AXI_Stream_FIFO_inst/n9063_s9/I1 |
| 4.915 | 0.555 | tINS | FF | 1 | AXI_Stream_FIFO_inst/n9063_s9/F |
| 5.152 | 0.237 | tNET | FF | 1 | AXI_Stream_FIFO_inst/n9063_s8/I0 |
| 5.669 | 0.517 | tINS | FF | 1 | AXI_Stream_FIFO_inst/n9063_s8/F |
| 5.906 | 0.237 | tNET | FF | 1 | AXI_Stream_FIFO_inst/rfifo_add_cnt_20_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | S_axi_aclk | |||
| 10.000 | 0.000 | tCL | RR | 1 | S_axi_aclk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 1044 | S_axi_aclk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | AXI_Stream_FIFO_inst/rfifo_add_cnt_20_s1/CLK |
| 10.828 | -0.035 | tSu | 1 | AXI_Stream_FIFO_inst/rfifo_add_cnt_20_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 3.152, 62.503%; route: 1.659, 32.897%; tC2Q: 0.232, 4.600% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:| Slack | 4.986 |
| Data Arrival Time | 5.842 |
| Data Required Time | 10.828 |
| From | AXI_Stream_FIFO_inst/rfifo_add_cnt_7_s1 |
| To | AXI_Stream_FIFO_inst/rfifo_add_cnt_19_s1 |
| Launch Clk | S_axi_aclk[R] |
| Latch Clk | S_axi_aclk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | S_axi_aclk | |||
| 0.000 | 0.000 | tCL | RR | 1 | S_axi_aclk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 1044 | S_axi_aclk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | AXI_Stream_FIFO_inst/rfifo_add_cnt_7_s1/CLK |
| 1.095 | 0.232 | tC2Q | RF | 6 | AXI_Stream_FIFO_inst/rfifo_add_cnt_7_s1/Q |
| 1.332 | 0.237 | tNET | FF | 1 | AXI_Stream_FIFO_inst/n9112_s3/I1 |
| 1.887 | 0.555 | tINS | FF | 1 | AXI_Stream_FIFO_inst/n9112_s3/F |
| 2.124 | 0.237 | tNET | FF | 1 | AXI_Stream_FIFO_inst/n9070_s14/I1 |
| 2.679 | 0.555 | tINS | FF | 2 | AXI_Stream_FIFO_inst/n9070_s14/F |
| 2.916 | 0.237 | tNET | FF | 1 | AXI_Stream_FIFO_inst/n9070_s10/I2 |
| 3.369 | 0.453 | tINS | FF | 9 | AXI_Stream_FIFO_inst/n9070_s10/F |
| 3.606 | 0.237 | tNET | FF | 1 | AXI_Stream_FIFO_inst/n9065_s12/I0 |
| 4.123 | 0.517 | tINS | FF | 5 | AXI_Stream_FIFO_inst/n9065_s12/F |
| 4.360 | 0.237 | tNET | FF | 1 | AXI_Stream_FIFO_inst/n9064_s10/I1 |
| 4.915 | 0.555 | tINS | FF | 1 | AXI_Stream_FIFO_inst/n9064_s10/F |
| 5.152 | 0.237 | tNET | FF | 1 | AXI_Stream_FIFO_inst/n9064_s8/I2 |
| 5.605 | 0.453 | tINS | FF | 1 | AXI_Stream_FIFO_inst/n9064_s8/F |
| 5.842 | 0.237 | tNET | FF | 1 | AXI_Stream_FIFO_inst/rfifo_add_cnt_19_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | S_axi_aclk | |||
| 10.000 | 0.000 | tCL | RR | 1 | S_axi_aclk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 1044 | S_axi_aclk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | AXI_Stream_FIFO_inst/rfifo_add_cnt_19_s1/CLK |
| 10.828 | -0.035 | tSu | 1 | AXI_Stream_FIFO_inst/rfifo_add_cnt_19_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 3.088, 62.020%; route: 1.659, 33.320%; tC2Q: 0.232, 4.660% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |